T he P rocessing Unit

THE PROCESSING UNIT

REVIEW OF SOME FUNDAMENTAL CONCEPTS

 The processing unit executes machine

instructions and coordinates the activities of
other units. This unit is often called the
Instruction Set Processor (ISP), or simply the
processor.

 The processing unit used to be called the central

processing unit (CPU). The term “central” is less
appropriate today because many modern
computer systems include several processing
units.

 The instructions constituting a program to be

executed by a computer are loaded in sequential
locations in the main memory.

 To execute this program, the processor fetches

one instruction at a time and performs the
functions specified.

 Instructions are fetched from successive memory

locations until a branch or a jump instruction is
executed.

 The processor keeps track of the address of the

memory location containing the next instruction
by using a dedicated register, referred to as the
program counter (PC).

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 After fetching an instruction, the contents of the

PC are updated to point to the next instruction in
the sequence.

 In order to fetch/read an instruction or data from

main memory:

1. The processor first sends the address of the

memory location to be read.

2. The processor then issues or sends the read

signal to the memory.

3. The word is then read out of memory and is

loaded into a processor internal register.

 In order to store/write data into main memory:

1. The processor first sends the address of the

memory location to be written.

2. The processor then sends the write signal

together with the word to be written to
memory.

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 Connections between the processor and the main

memory:

Mai n Me mory

MAR MDR
Control
PC
R0
IR R1
ALU
.
.
CPU .
Rn-1
n Ge ne ral Purpos e
Re gi s te rs

The PC (Program Counter) contains the memory

address of the instruction to be executed. During
execution, the contents of the PC are updated to
point to the next instruction.

The MAR (Memory Address Register) holds the

address of the location to or from which data are
to be transferred.

The MDR (Memory Data Register) contains the

data to be written or read out of the addressed
location.

The IR (Instruction Register) contains the

instruction that is being executed.

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 Operating Steps:

1. PC is set to point to the first instruction of

the program (the operating system loads the
memory address of the first instruction).
2. The contents of the PC are transferred to the
MAR (which are automatically transmitted to
the MM) and a Read signal is sent to the MM.
3. The addressed word is read out of MM and
loaded into the MDR.
4. The contents of MDR are transferred to the
IR. The instruction is ready to be decoded
and executed.
5. During execution, the contents of the PC are
incremented or updated to point to the next
instruction.
If operand or data needed by the instruction
resides in MM:
1. It will have to be fetched by sending
its address to the MAR and
initiating a read cycle.
2. When the operand has been read
from MM into the MDR, it may be
transferred from the MDR to the
ALU
If result is to be stored in MM:
1. The result is sent to the MDR.
2. The address of the location where
the result is to be stored is sent to
the MAR and a write cycle is
initiated.

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 Steps in instruction execution:

1. Fetch the contents of the memory location

pointed to be the PC. The contents of this
location are interpreted as an instruction to
be executed. Hence, they are loaded into the
IR.

IR  [ [PC] ]

2. Increment the contents of the PC by 1.

PC  [PC] + 1

3. Carry out the actions specified by the

instruction in the IR.

Note: If the instruction occupies more than

one word, steps 1 and 2 are repeated as
many times as necessary to fetch the
complete instruction

Steps 1 and 2 are usually referred to as

the fetch phase; step 3 constitutes the
execution phase.

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 Single-bus organization of the data paths inside

the processing unit:

Instructi on
De code r Inte rnal
Proce ssor
Bus
IR

PC

Addre ss Line s
MAR
Me mory
Bus Data Line s
MDR

R0

R1
.
.
.

Rn-1

1 Y

S e le ct MUX

ALU Add A B
S ub ALU
Control :
Line s XOR Carry-in

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In this organization, the arithmetic and logic unit

(ALU) and all the registers are interconnected via
a single common bus. This bus is internal to the
processor and should not be confused with the
external bus that connects the processor to the
memory and I/O devices.

The data and address lines of the external

memory bus are connected to the internal
processor via the MDR and the MAR respectively.

Two registers (Y and Z) have not been mentioned

before. These registers are transparent to the
programmer; that is, the programmer need not be
concerned with them, because they are never
referenced directly by any instruction. They are
used only by the processor for temporary storage
during execution of some instructions.

The multiplexer (MUX) selects either the output of

register Y or a constant 1 to be provided as input
A of the ALU. The constant 1 is used to
increment the contents of the program counter.

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The instruction decoder unit is responsible for

implementing the actions specified by the
instruction loaded in the IR register. The decoder
generates the control signals needed to select the
registers involved and direct the transfer of data.

The registers, the ALU, and the interconnecting

bus are collectively referred to as the data path.

 With a few exceptions, an instruction can be

executed by performing one or more of the
following operations in some specified sequence:

1. Transfer a word of data from one processor

register to another or to the ALU.

2. Perform an arithmetic or logic operation and

store the result in a processor register.

3. Fetch the contents of a given memory

location and load them into a processor
register.

4. Store a word of data from a processor register

into a given memory location.

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 Register Transfers

To enable data transfers between various blocks

in a common data bus, input and output gating
must be provided. The input and output gates for
register Ri are controlled by the signals Riin and
Riout, respectively.

If Riin = 1, the data available on the common bus

is loaded into Ri.

If Riout = 1, the contents of register Ri are placed

on the bus.

Ri in

Internal
Ri Processor
Bus

Ri out

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Example:
R4  [R1]

- Enable the output gate of register R1 by

setting R1out to 1. This places the
contents of R1 on the processor bus.

- Enable the input gate of register R4 by

setting R4in to 1. This loads data from
the processor bus into register R4.

Input and Output Gating for the ALU

Yi n

Y
1

S e le ct MUX

A B
ALU

Zin

Zout

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 Performing an Arithmetic or Logic Operation

The ALU is a combinational circuit that has no

internal storage. It performs arithmetic and logic
operations on the two operands applied to its A
and B inputs. One of the operands is the output
of the multiplexer MUX (which is either 1 or the
contents of register Y) and the other operand is
obtained directly from the bus. The result is
stored temporarily in register Z.

Example: R3  [R1] + [R2]

1. R1out, Yin

2. R2out, SelectY, Add, Zin

3. Zout, R3in

The signals whose names are given in any step

are activated for the duration of the clock cycle
corresponding to that step. All other signals are
inactive.

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In step 1, the output of register R1 and the input

of register Y are enabled, causing the contents of
R1 to be transferred over the bus to Y.

In step 2, the multiplexer’s Select signal is set to

SelectY, causing the multiplexer to gate the
contents of register Y to input A of the ALU. At
the same time, the contents of register R2 are
gated onto the bus and, hence to input B.

The function of the ALU depends on the signals

applied to its control lines. In this case, the Add
line is set to 1 (activated), causing the output of
the ALU to be the sum of the two numbers at
inputs A and B. This sum is loaded into register
Z because its input control signal is activated.

In step 3, the contents of register Z are

transferred to the destination register R3. This
last transfer cannot be carried out during step 2,
because only one register output can be
connected to the bus during any clock cycle.

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 Fetching a Word from Memory

To fetch a word from main memory, the processor

has to specify the address of the memory location
where it is stored and request a read operation.
This applies whether the information to be
fetched represents an instruction in a program or
an operand specified by an instruction.

The processor transfers the required address to

the MAR, whose output is connected to the
address lines of the memory bus. At the same
time, the processor uses the control lines of the
memory bus to indicate that a Read operation is
needed. When the requested data are received
from the memory they are stored in register MDR,
from where they can be transferred to other
registers in the processor.

The connections for register MDR:

MDRoutE MDRin

Me mory-bus Inte rnal

MDR Proce ssor
Data Line s
Bus

MDRinE MDRout

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Register MDR has four control signals: MDR in and

MDRout control the connection to the internal bus,
and MDRinE and MDRoutE control the connection
to the external bus.

During the Read and Write, the timing of internal

processor operations must be coordinated with
the response of the addressed device on the
memory bus. The processor completes one
internal data transfer in one clock cycle. The
speed of operation of the addressed device, on the
other hand, varies with the device.

To accommodate the variability in response time,

the processor waits until it receives an indication
that the requested Read operation has been
completed. There is a control signal called
Memory-Function-Complete (MFC) that is used
for this purpose. The addressed device sets this
signal to 1 to indicate that the contents of the
specified location have been read and are
available on the data lines of the memory bus.

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Example:

Assume that the address of the memory

location to be accessed is in R1 and the
memory data is to be loaded into R2. The
actions needed to execute this instruction
are:

1. MAR  [R1]

2. Start a Read operation on the

memory bus

3. Wait for the MFC response from the

memory

4. Load MDR from the memory bus

5. R2  [MDR]

The actions may be carried out as separate

steps, but some can be combined into a
single step. Each action can be completed in
one clock cycle, except action 3 which
requires one or more clock cycles, depending
on the speed of the addressed device.

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Assume for simplicity that the output of the

MAR is enabled all the time (when a new
address is loaded into MAR, it will appear on
the memory bus).

When a new address is loaded into MAR, it

will appear on the memory bus. A Read
signal is activated at the same time MAR is
loaded. This signal will cause the bus
interface circuit to send a read command on
the bus. With this arrangement, actions 1
and 2 above are combined into a single
control step. Actions 3 and 4 can also be
combined by activating control signal MDRinE
while waiting for a response from memory.
Thus, the data received from the memory are
loaded into MDR at the end of the clock in
which the MFC signal is received. In the next
clock cycle, MDRout is activated to transfer
the data to register R2. This means that the
memory read operation requires three steps,
which can be described by the signals being
activated as follows:

1. R1out, MARin, Read

2. MDRinE, WMFC
3. MDRout, R2in

where WMFC is the control signal that

causes the processor’s control circuitry to
wait for the arrival of the MFC signal.

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 Storing a Word into Memory

To store a word into main memory, load the

address into the MAR. Then, the data to be
written to memory is loaded into MDR and a Write
command is issued.

Example:

Assume that the data word to be stored in

memory is in R2 and the memory address is
in R1.

1. R1out, MARin

2. R2out, MDRin, Write

3. MDRoutE, WMFC

As in the case of the read operation, the Write

control signal causes the memory bus interface to
issue a Write command on the memory bus. The
processor remains in step 3 until the memory
operation is completed and an MFC response is
received.

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EXECUTION OF A COMPLETE INSTRUCTION

 Assume the following instruction:

R1  [R1] + [[R2]]

The contents of register R1 are added to the

contents of a memory location (the address of
which is in register R2) and store the results in
register R1.

Executing this instruction requires the following

actions:

1. Fetch the instruction.

2. Fetch the first operand (the contents of
the memory location pointed to by R2).
3. Perform the addition.
4. Load the result into R1.

Control Sequence for R1  [R1] + [[R2]]

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R2out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End

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Step 1. The instruction fetch operation is

initiated by loading the contents of the
PC into the MAR and sending a Read
request to the memory. The select signal
is set to Select1, which causes the
multiplexer MUX to select the constant
1. This value is added to the operand at
input B, which is the contents of the PC,
and the result is stored in register Z (the
PC is incremented by 1).

Step 2. The updated value of the PC (which is in

register Z) is moved back to the PC.
Note that step 2 begins immediately
after the memory Read is requested,
without waiting for the memory function
to be completed. Step 3, however, has to
be delayed until the MFC signal is
received.

Step 3. The word fetched from the memory is

loaded into the IR. The instruction
decoding circuit interprets the contents
of the IR at the beginning of step 4. This
enables the control circuitry to choose
the appropriate signals for the
remainder of the control sequence.

Steps 1 through 3 constitute the instruction fetch

phase, which is the same for all instructions.
Steps 4 through 7 constitutes the execution
phase.

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The contents of register R3 are transferred to the

MAR in step 4, and a memory read is initiated.

Then the contents of R1 are transferred to register

Y in step 5, to prepare for the addition operation.

When the Read operation is completed, the

memory operand is available in register MDR, and
the addition operation is performed in step 6.
The contents of the MDR are gated to the bus,
and thus also to the B input of the ALU, and
register Y is selected as the second input to the
ALU by choosing SelectY. The sum is stored in
register Z.

The sum is then transferred to R1 in step 7. The

End signal causes a new instruction fetch cycle to
begin by returning to step 1.

Take note that in step 2, the updated contents of

PC are also loaded to register Y. This has no
purpose in the execution of the Add instruction.
But in Branch instructions the updated value of
PC is needed to compute the Branch target
address. To speed up the execution of Branch
instructions, this value is copied into register Y in
step 2. Since step 2 is part of the fetch phase, the
same action will be performed for all instructions.
This does not cause any harm because register Y
is not used for any other purpose at that time.

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 Assume the following instruction:

R1  [R1] + [LOC]

Executing this instruction requires the following

actions:

1. Fetch the instruction.

2. Fetch the first operand (the contents of
the memory location pointed to by the
address field of the instruction).
3. Perform the addition.
4. Load the result into R1.

Control Sequence for R1  [R1] + [LOC]

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC

3. MDRout, IRin

4. Offset-field-of-IRout, MARin, Read

5. R1out, Yin, WMFC

6. MDRout, SelectY, Add, Zin

7. Zout, R1in, End

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 Branching

Branching is accomplished by replacing the

current contents of the PC by the branch address,
that is, the address of the instruction to which
branching is required.

This branch address is usually obtained by

adding an offset X, which is given in the branch
instruction, to the updated value of the PC.

Control Sequence for Unconditional Branching

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC

3. MDRout, IRin

4. Offset-field-of-IRout, SelectY, Add, Zin

5. Zout, PCin, End

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For conditional branching, the only difference is

the need to check the status of the condition
codes before loading a new value into the PC.

Example:

Branching on Negative Instruction

(Jump if the sign flag = 1)

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC

3. MDRout, IRin

4. Offset-field-of-IRout, SelectY, Add, Zin,

if SF = 0 then End

5. Zout, PCin, End

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SEQUENCING OF CONTROL SIGNALS

 To execute instructions, the processor must have

some means of generating the control signals.
Computer designers have used a wide variety of
techniques to solve this problem.

 Most of these techniques, however, fall into one of

two categories: hardwired control and
microprogrammed control.

 Hardwired Control Unit

CLK Control S te p
Clock
Coun te r
. . .

S tatus Flags
.
De code r/
IR .
Encode r
.
Con di tion Code s

. . .

Control S i gnals

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The required control unit is based on the use of a

counter (control step counter) driven by a clock
signal (CLK). Each state or count of this counter
corresponds to one step in the execution of an
instruction.

The contents of the IR represent the current

instruction being executed.

The required control signals are uniquely

determined by following information:

1. the contents of the control counter

2. the contents of the instruction register

3. the contents of the condition code and

other status flags

The status flags refer to the signals representing

the states of various sections of the processor and
of various control lines connected to it. An
example is the MFC signal.

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The decoder-encoder block is a combinational

circuit that generates the required control
outputs depending on the state of all its inputs.

CLK
Cl ock Control S te p Re se t
Counte r
. . .

S te p De code r

T1 T2 . . . Tn
INS 1
INS 2 S tatus Fl ags
. .
Instructi on
IR . . Encode r
De code r
. .
INS m Condi ti on Code s

RUN . . . END

The step decoder provides a separate signal line

for each step, or time slot, in the control
sequence.

The output of the instruction decoder consists of

a separate line for each machine instruction. That
is, for any instruction loaded in the IR, one of the
output lines INS1 through INSm is set to 1, and all
other lines are set to 0.

All input signals to the encoder block should be

combined to generate the individual control
signals Yin, PCout, ADD, END, and so on.

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Examples:

INS1: R1  [R1] + [[R2]]

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. R2out, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End

INS2: R1  [R1] + [LOC]

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, MARin, Read
5. R1out, Yin, WMFC
6. MDRout, SelectY, Add, Zin
7. Zout, R1in, End

INS3: Unconditional Branching

1. PCout, MARin, Read, Select1, Add, Zin

2. Zout, PCin, Yin, WMFC
3. MDRout, IRin
4. Offset-field-of-IRout, SelectY, Add, Zin
5. Zout, PCin, End

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The control signal Zin, which enables the input to

register Z, is turned on (active) during the
following instances:

1. T1 of INS1
2. T6 of INS1
3. T1 of INS2
4. T6 of INS2
5. T1 of INS3
6. T4 of INS3

This means that Zin = 1 if:

1. (T1 = 1 and INS1 = 1) or

2. (T6 = 1 and INS1 = 1) or

3. (T1 = 1 and INS2 = 1) or

4. (T6 = 1 and INS2 = 1) or

5. (T1 = 1 and INS3 = 1) or

6. (T4 = 1 and INS3 = 1) or

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The logic equation for Zin is therefore:

Zin = (T1 and INS1) or (T6 and INS1) or (T1 and

INS2) or (T6 and INS2) or (T1 and INS3) or
(T4 and INS3)

The logic circuit for Zin:

T1
INS1
T6
INS1
T1
INS2
Zin
T6
INS2
T1
INS3

T4
INS3

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Simplification:

Since Zin is active at T1 for all instructions, it

can be concluded that Zin is active at T1 no
matter what instruction is being executed.
Likewise, it is also active at T6 for all
instructions (only INS1 and INS2 have T6). It
can be concluded that it is active at T6 no
matter what instruction is executed.
Therefore, the circuit can be simplified as:

T1
T6 Zin

T4
INS3

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 Microprogrammed Control

An alternative scheme in generating the control

signals is the microprogrammed control, in which
the control signals are generated by a program
similar to machine language programs.

A control word (CW) is a word whose individual

bits represent the various control signals. Each
of the control steps in the control sequence of an
instruction defines a unique combination of 1’s
and 0’s in the CW.

The CWs corresponding to the 7 steps of the

control sequence of the ADD instruction given
earlier, specifically, R1  [R1] + [[R2]].
MARi

WMF
MDR
Read

Selec
Selec
PCout

R1out

R2out

END
Step

PCin

Add

R1in
Zout
IRin
Yin

Zin

… …

1 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
4 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0
5 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

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A sequence of control words corresponding to the

control sequence of a machine instruction
constitutes a microroutine for the instruction.
The individual control words in this microroutine
are usually referred to as microinstructions.
Microroutines are stored in a special memory
called microprogram memory.

S tarti n g
IR Addre ss
Ge ne rator

CLK  PC

Microprogram
Me mory CW

To read control words sequentially, a

microprogram counter (PC) is used.

Everytime a new instruction is loaded into the IR,

the output of the starting address generator is
loaded into the PC which is then automatically
incremented by the clock causing successive
microinstructions to be read from the memory.

Hence the control signals will be delivered to

various parts of the processor in the correct
sequence.

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