0487
An Improved Interleaved DC-DC SEPIC Converter
Based on SiC-Cascode Power Devices for
Renewable Energy Applications
Salah S. Alharbi, Saleh S. Alharbi, and Mohammad Matin
Department of Electrical and Computer Engineering,
Daniel Felix Ritchie School of Engineering and Computer Science, University of Denver, Denver, Colorado 80208, USA
Email: salah.alharbi[saleh.s.alharbi][mohammad.matin]@du.edu
Abstract—The worldwide development of renewable energy
applications, especially those using solar photovoltaic (PV) panels
and fuel cells, poses increasing requirements for improving power
density, energy efficiency, and reliability of DC–DC power convert-
ers as they play a vital role in power conversion systems. Wide
bandgap (WBG) semiconductors, such as silicon carbide (SiC)
and gallium nitride (GaN), contain superior material properties
to replace conventional silicon (Si) materials, pushing the bound-
aries of power devices to handle higher power levels, blocking
voltages, switching frequencies, and operating temperatures. This
paper presents an improved interleaved DC–DC single-ended
primary-inductor converter (SEPIC) based on a new hybrid SiC-
JFET-cascode switch/SiC-Schottky diode for renewable energy
applications. To evaluate the effects of SiC power devices on
the switching behavior, total power loss, and efficiency of the
converter, both Si-based and SiC-based converters are designed
and compared under harsh operating conditions. The switching
behavior of the Si and SiC power devices is analyzed through
the double-pulse test (DPT), taking different switch currents and
gate resistance values into consideration. The total power loss
and energy efficiency of the two converters are calculated and
compared over a wide range of switching frequencies and input
voltages. The results reveal that the hybrid SiC-JFET-cascode
switch/SiC-Schottky diode substantially improved the converter
performance at a variety of operating conditions.
Index Terms—Wide bandgap semiconductor materials, SiC-
JFET-cascode switch, SiC-Schottky diode, Si-MOSFET, Si-diode,
DPT, switching behavior, SEPIC converter, energy efficiency.
I. I NTRODUCTION
Due to the environmental consequences of using fossil fuels
and their limited reserves, renewable energy sources–such as
solar photovoltaic (PV) panels, wind turbines, and fuel cells–
have attracted worldwide interest as a method of sustainable
power generation [1], [2]. Power electronic converters play a
crucial role in converting, controlling, and transferring electri-
cal energy from these sources to the DC load/utility grid [3].
Renewable energy applications, especially PV and fuel cells,
are facing practical challenges from high-input current ripples
and varying low-output voltages [4]. An interleaved, single-
ended, primary-isolator converter (SEPIC) can efficiently over-
come these challenges by regulating and boosting the out-
put voltage to a desired level [5]. Compared to different
interleaving DC–DC converter topologies, interleaved SEPIC
converters provide a step-up/step-down conversion ratio with
non-inverted output voltage and achieve higher efficiency with
978-1-5386-5398-2/18/$31.00 ©2018 IEEE
fewer components [6]. Therefore, interleaved SEPIC converters
are widely implemented in the aforementioned applications [7].
The global development of renewable energy applications,
particularly solar PV panels and fuel cells, requires DC–
DC power converters with improved power density, energy
efficiency, and reliability [8]. Power devices that operate ef-
ficiently under high blocking voltages, switching speeds, and
operating temperatures are needed to make existing converters
more efficient [9]. However, most current interleaved SEPIC
converters are based on conventional silicon (Si) power devices.
These devices are approaching theoretical and operational
limits because of their intrinsic material properties, imposing a
barrier to converter performance [10]. As a result, it is difficult
to improve the switching performance and energy efficiency of
the converters with existing Si technology.
Presently, alternative semiconductor materials with outstand-
ing characteristics are being developed by researchers and man-
ufacturers for next-generation power devices [11]. Emerging
wide bandgap (WBG) semiconductors, such as gallium nitride
(GaN) and silicon carbide (SiC), exhibit superior material
properties to replace traditional Si materials [12], [13]. SiC
power devices are the most mature WBG semiconductors
commercially available on the market [14]. Researchers have
studied the switching behavior of SiC devices and evaluated
their impacts on converter performance. Several studies [15]–
[18] have compared the performance of Si and SiC-Schottky
diodes in power converters. Detailed comparisons of Si-IGBTs
and SiC-MOSFETs used in T-type inverters, boost converters,
and three-level neutral-point-clamped converters were reported
in these studies [19]–[21]. Recent research studies [22], [23]
have focused on SiC-JFETs in cascode configuration because
of their high operating capabilities. However, few studies have
characterized the behavior of SiC-JFET-cascode switches at a
voltage level lower than 1.2-kV.
In this paper, the new hybrid 650-V SiC-JFET-cascode
switch/SiC-Schottky diode is integrated to improve the switch-
ing behavior, reduce power loss, and increase energy efficiency
of the interleaved SEPIC converter at an output voltage of 400-
V and a rated power of 600-W. These specifications are com-
patible with distributed renewable energy sources connected
to the DC bus, which typically has a voltage range of 350–
400 V. The impact of SiC devices on converter performance
is compared to a commonly used Si-MOSFET/Si-diode-based
 0488

converter and evaluated at different switching frequencies and where Iin and Iout are the input and output currents, ∆iL1
input voltages. and ∆iL2 are the peak-to-peak ripples in the inductor currents,
This research is organized in the following manner: Section L1 and L2 are the input inductors, L3 and L4 are the output
II describes the converter topology with design specifications, inductors, C1 and C2 are the middle capacitors, ∆vout is the
Section III presents semiconductor power devices with different peak-to-peak ripple of coupling capacitor voltage, and Cout is
technologies and analyzes power losses in these devices, Sec- the output capacitor.
tion IV assesses switching behavior and energy loss of power
devices used in the converter, Section V compares and evaluates
TABLE I
overall converter performance with different combinations of S PECIFICATIONS FOR THE I NTERLEAVED DC–DC S EPIC C ONVERTER
power devices to determine total power loss and energy effi-
ciency as the switching frequency and input voltage increase, Parameter Symbol Value
and Section VI summarizes the research findings.
Rated power Pout 600 W
II. I NTERLEAVED DC–DC S EPIC C ONVERTER Input voltage Vin 80 – 120 V
Interleaved SEPIC converters are widely implemented in Output voltage Vout 400 V
renewable energy applications, including PV and fuel cell sys- Duty ratio d 20 – 80 %
tems, which are facing the critical challenges of high-input cur- Switching frequency fsw 20 – 320 kHz
rent ripples and varying low-output voltages. These challenges
can be overcome by implementing the interleaved SEPIC
topology. The interleaving technique is a well-established con- The interleaved SEPIC converter is designed to operate in
cept that consists of phase shifting control signals of multi- continuous conduction mode (CCM) in order to investigate
converters in parallel operation mode at the same switching the effects of Si and SiC power devices on overall converter
frequency. This technique is applied to DC–DC converters in performance. The converter is evaluated at a rated power of
order to process more power, reduce the harmonic distortion, 600-W with an input voltage of 100-V, an output voltage of
and minimize electromagnetic interference filter components. 400-V, and a load resistance of 240-Ω. The sizes of the inductor
and capacitor vary when switching frequency changes. The
L2 C2 D2 different combinations of power devices were selected based
on their similarity in electrical specifications and compatibility
L1 C1 D1 with the designed converter. The parameters of these devices
are provided in Table II.

Vin Cin S1 S2 L3 L4 Cout R Vout

III. S I AND S I C P OWER D EVICES

Si and SiC semiconductors are the two major materials used

Fig. 1. Schematic of the Interleaved DC–DC SEPIC Converter.
to fabricate power devices. SiC power devices, such as SiC-
Compared to different interleaving DC–DC topologies, in- MOSFETs and SiC-JFETs, have the remarkable advantages of
terleaved SEPIC converters provide an excellent buck-boost operating at higher blocking voltages, junction temperatures,
conversion ratio with non-inverted output voltage and obtain and switching frequencies because of their outstanding ma-
higher energy efficiency with fewer components. Fig. 1 illus- terial properties. These properties include higher breakdown
trates a schematic of an interleaved SEPIC converter. Table electric field, wider bandgap energy, greater electron mobility,
I provides the converter specifications. In steady-state mode, increased thermal conductivity, and higher melting point [24].
the output voltage, inductor, and capacitor equations for the SiC technology significantly increases the operating capabilities
designed converter are presented as follows: of power devices and enables them to be more efficient,
compact, and robust.
Vout Iin d
= = (1) SiC-JFETs in cascode configuration are the most mature and
Vin Iout d−1 well established among different SiC devices. They feature a
higher operating temperature and switching speed with lower
(1 − d)Vout (1 − d)Vout
L1 = L2 = = (2) leakage current, smaller on-state resistance, negligible drain-
∆iL1 fsw ∆iL2 fsw source capacitance, and no gate oxide issues. A SiC-Schottky
diode is increasingly used in place of a Si-diode because of its
L1 L2 virtually zero reverse-recovery effect, low threshold voltage,
L3 = L4 = = (3)
2 2 ultra-fast turn-on speed, and high operating temperature. The
impact of a hybrid SiC-JFET-cascode switch/SiC-Schottky on
dIout
C1 = C2 = (4) the converter level is evaluated and compared against a common
∆vout fsw Si-MOSFET/Si-diode. The majority of a converter’s power
dissipation occurs within the power devices. Therefore, the
dPout
Cout = (5) conduction and switching losses of Si and SiC devices are
∆vripple Vout fsw determined at two different junction temperatures, as shown
 0489

TABLE II
M AIN PARAMETERS OF P OWER D EVICES

Devices SiC-JFET-cascode Si-MOSFET SiC-Schottky diode Si-diode

Manufacturer USCi Rohm Cree Rohm
Part number UJC06505K R6535ENZ1 C3D10060A RFV30TG6S
Package TO-247 TO-247 TO-220 TO-220
Blocking voltage 650 V 650 V 600 V 600 V
Rated current (Tj = 25◦ C) 36.5 A 30 A 30 A 30 A
Typical on-state resistance (Tj = 25◦ C) 34 mΩ 98 mΩ N/A N/A
Forward voltage (Tj = 25◦ C) N/A N/A 1.8 V 2.3 V
Max. junction temperature 150◦ C 150◦ C 175◦ C 150◦ C

in Fig. 2. The semiconductor loss (PQ ) is calculated by adding
conduction and switching losses, as expressed in
PQ = PS,con + PS,sw + PD,con
where PS,con and PS,sw are the conduction and switching
losses of SiC-JFET-cascode and Si-MOSFET switches, and
PD,con is the conduction loss of Si and SiC-Schottky diodes.
The switching loss of these diodes is disregarded because
they are insignificant. Table III provides a comparison of the
semiconductor loss for each combination of power devices at
junction temperatures of 25 and 125◦ C. SiC devices offer con-
siderably lower semiconductor loss due to their high thermal
conductivity and small on-state resistance.
IV. H ARD -S WITCHING C HARACTERIZATION OF P OWER
D EVICES
(6) The switching behavior and energy loss of different power
devices are characterized under the hard-switching condition
through the standard inductive-clamped load test circuit, which
is known as a double pulse test (DPT). In the meantime, a
600-V, 30-A SiC-Schottky diode is used to provide a free-
wheeling path (FWD) for the inductor current and improve
the switching performance of the Si-MOSFET and SiC-JEFT-
cascode devices. For a fair comparison, the two different power
devices are examined under identical junction temperatures,
switch currents, and input voltages. Also, these devices have the
same package structure to ensure they have the exact parasitic
inductance effects. Nevertheless, the gate–source voltage and
gate resistance of the two tested devices are selected based on
the datasheet recommendation.

400 30

300 20

200 10

100 0

400
30
300
20
200
10
100
0
0

Fig. 2. Switching and conduction losses of power devices in the interleaved

SEPIC converterat at fsw = 100 kHz for Tj = 25 and 125◦ C.
Fig. 3. Turn-on (top) and turn-off (bottom) characteristics of the Si-MOSFET
with Rg = 10-Ω and Vgs = ±20 V at Vsw = 200-V, Isw = 20-A, and Tj =
25◦ C.
TABLE III
S EMICONDUCTOR L OSS FOR EACH C OMBINATION OF P OWER D EVICES IN
VARIOUS J UNCTION T EMPERATURES
A. Si-MOSFET Switching Waveforms
Semiconductor SiC-JFET-cascode switch/ Si-MOSFET/ The 650-V, 35-A Si-MOSFET is tested with a gate–source
loss SiC-Schottky diode Si-diode voltage (Vgs ) of –20 to +20 V for the turn-off and turn-on
PQ at Tj = 25◦ C 10.4 W 14.6 W transitions, respectively. The gate resistance (Rg ) is set at 10-
PQ at Tj = 125◦ C 12.9 W 17.3 W
Ω to obtain an optimal low switching energy loss along with
a small overshoot. This device features fast switching speeds
 0490

with relatively low on-state resistance. Fig. 3 shows the turn-on increasing the switch current to provide an accurate method
(top) and turn-off (bottom) characteristics of the Si-MOSFET at of estimating switching energy loss. This loss is computed
a junction temperature of 25◦ C. Measured turn-on and turn-off by integrating the product of the measured drain–source (Vds )
energy losses are 102.5 and 165.7 µJ, respectively. The drain voltage and drain current (Id ) waveforms during turn-on (ton )
current waveform exhibits a considerable overshoot during the and turn-off (tof f ) transitions. The total energy loss (Etotal )
turn-on transition due to the capacitance of the FWD. In the is obtained by adding the turn-on (Eon ) and turn-off (Eof f )
turn-off transition, a small overshoot occurs in the drain–source energy losses, as described by
voltage waveform because of the stray inductance. The device Z
current and voltage waveforms during turn-off have a large Eon = vds (t)id (t)dt (7)
ringing, which can be minimized by controlling the current ton
commutation loop. Z
Eof f = vds (t)id (t)dt (8)
tof f
500
400 20
300 Etotal = Eon + Eof f (9)
200 10
100
0 0
-100

400
500
400 20
300
300
200 10
200
100
0 0 100
-100

Fig. 4. Turn-on (top) and turn-off (bottom) characteristics of the SiC-JFET-
cascode with Rg = 20-Ω and Vgs = 0 to +12 V at Vsw = 200-V, Isw =
20-A, and Tj = 25◦ C.
B. SiC-JFET-Cascode Switching Waveforms
The 650-V, 36.5-A cascode switch is composed of a low-
voltage Si-MOSFET and a high-voltage normally-on SiC-
JFET in series connection in order to achieve high operating
capabilities. The gate–source voltage of the SiC-JFET-cascode
is 0 V during the turn-off condition and +12 V during the turn-
on condition. This device has the advantages of an ultra-low on-
state resistance, very fast switching frequency, and low intrinsic
capacitance with excellent reverse recovery characteristics. Fig.
4 depicts the turn-on (top) and turn-off (bottom) characteristics
of the SiC-JFET-cascode using a 20-Ω gate resistance at a
junction temperature of 25◦ C. The measured energy losses
within turn-on and turn-off transients are 130.8 and 43.2 µJ,
respectively. During the turn-off transition, a small overshoot
appears in the drain–source waveform. The device current and
voltage waveforms during the turn-off condition show a short
period of ringing. The phenomenon of overshoot and ringing
that occurs in the current and voltage waveforms is caused by
the capacitance of the FWD and the total inductance of the
device commutation loop. The SiC-JFET-cascode reduces the
overshoot by 28.5% and the ringing by 52.2% compared to the
Si-MOSFET. As a result, the SiC-cascode device substantially
improves the switching performance.
C. Switching Energy Loss Comparison
The switching energy losses are determined through the DPT
circuit at two different gate resistance values as a function of
350
250
150
50
400
300
200
100
5 10 15 20 25
Fig. 5. Turn-on (top), turn-off (middle), and total (bottom) energy losses of
Si-MOSFET and SiC-JFET-cascode devices in different switch currents for two
gate resistance values at Vsw = 400-V, and Tj = 25◦ C.
Fig. 5 shows a comparison of the switching energy losses
for Si-MOSFET and SiC-JFET-cascode devices at two gate
resistance values of 5 and 15-Ω as the switch current is
increased from 5 to 25-A. The turn-on and turn-off energy
losses of these devices increase as the switch current is in-
creased. However, the SiC-JFET-cascode exhibits a remarkably
lower total energy loss than the Si-MOSFET throughout the
switch current increases. Furthermore, the gate resistance has
a major impact on the switching energy loss of both devices.
Here, the energy loss dramatically increases at higher gate
resistance. Lowering gate resistance reduces the transient time
 0491

of the switch. This process helps to minimize the switching
energy loss; nevertheless, a lower gate resistance can increase
the ringing of device voltage and current during turn-on and
turn-off transitions. At a switch current of 25-A and a gate
resistance of 5-Ω, the total energy loss of the SiC-JFET-cascode
is decreased by 36.7% compared to the Si-MOSFET. Therefore,
the SiC-cascode switch considerably improves the switching
behavior and reduces the total energy loss.
V. I NTERLEAVED DC-DC SEPIC C ONVERTER
E VALUATION
The interleaved DC–DC SEPIC converter performance with
two different semiconductor technologies is evaluated in terms
of total power loss and energy efficiency. The hybrid SiC-
JFET-cascode/SiC-Schottky diode-based converter is compared
against the commonly used Si-MOSFET/Si-diode-based con-
verter over a wide range of switching frequencies and input
voltages to simulate harsh operating conditions. The total power
loss (Ploss ) in the converter is obtained by adding power losses
in semiconductor devices, inductors (Pind ), and capacitors
(Pcap ). Based on the total loss and measured output power
(Pout ), the efficiency (η) is determined by
Ploss = PQ + Pind + Pcap
Pout
η= · 100%
Pout + Ploss
A. Converter Performance with Increased Switching Frequency
Since numerous applications demand more efficient, com-
pact, and cost-effective power converters, the Si-based and SiC-
based converters are investigated at fast switching speeds. Fig.
6 shows the total power loss and efficiency as a function of
increasing the switching frequency from 50 to 250 kHz at a
junction temperature of 25◦ C and an input voltage of 100-V.
The total power loss of the Si-based converter increases dras-
tically as the switching frequency is increased. This increasing
loss causes the converter to reach only 91.2% efficiency. On
the other hand, the total power loss of the SiC-based converter
increases only slightly as switching frequency is increased,
enabling the converter to achieve greater than 94.6% efficiency
throughout the switching frequencies tested. At a switching
frequency of 250 kHz and an input voltage of 100-V, the total
power loss in the SiC-based converter is reduced by 47.5%
compared to the Si-based converter. As a result, the hybrid
SiC-JFET-cascode/SiC-Schottky diode significantly improves
converter efficiency by 3.7% over the Si-MOSFET/Si-diode.
96
(10)
94
(11) 92
90

80 90 100 110 120

60
94

45 92

30 90

15 88

50 100 150 200 250 80 90 100 110 120

96
Fig. 7. Converter efficiency with SiC-JFET-cascode/SiC-Schottky diode and
94 Si-MOSFET/Si-diode with increasing input voltage at a junction temperature
of 25◦ C and switching frequencies of 100 and 200 kHz.

92
B. Converter Performance with Increased Input Voltage
90
The input voltage of the converter is often a critical factor
in how renewable energy applications operate because their
50 100 150 200 250 energies strongly rely upon weather conditions. Thus, converter
performance is assessed at different input voltages for two
switching frequencies. The input and output powers of each
converter are measured to determine efficiency as the input
Fig. 6. Total power loss (top) and efficiency (bottom) of SiC-JFET-
cascode/SiC-Schottky diode and Si-MOSFET/Si-diode based converters as voltage is increased from 80 to 120-V at two switching
switching frequency increases at a junction temperature of 25◦ C and an input frequencies of 100 and 200 kHz, as shown in Fig. 7. Here,
voltage of 100-V. the interleaved SEPIC converter operates efficiently around the
designed input voltage, which was discussed in Section II. This
 0492
means that the converter reaches peak efficiency at an input
voltage of 100-V. As the input voltage increases, the efficiency
of Si-based and SiC-based converters increases; however, their
efficiencies decrease dramatically after the input voltage of
100-V is exceeded. At a switching frequency of 200 kHz and
an input voltage of 120-V, the SiC-based converter achieves
92.9% efficiency, whereas the Si-based converter reaches only
90.1% efficiency. Therefore, the hybrid SiC-JFET-cascode/SiC-
Schottky diode substantially enhances the converter efficiency
by 3.1% over the Si-MOSFET/Si-diode.
VI. C ONCLUSION
In this paper, the improved interleaved DC–DC SEPIC
converter, based on a hybrid SiC-JFET-cascode switch/SiC-
Schottky diode, for renewable energy applications has been
presented. The investigation on the effects of SiC power devices
has been conducted through designing and comparing Si-based
and SiC-based converters over a wide range of operating condi-
tions. The conduction and switching losses of the two devices
were calculated at different junction temperatures. Because of
a small on-state resistance and energy loss, the SiC technology
has shown significantly low semiconductor losses. The DPT
circuit was used to study the switching behavior of two devices
and analyze their switching energy loss at different switch
currents and gate resistance values. Based on the DPT, the SiC-
JFET-cascode has demonstrated better switching performance
and lower energy losses than the Si-MOSFET. Furthermore, the
total power loss of the Si-based and SiC-based converters has
been determined to evaluate overall efficiency as a function of
increasing the switching frequency and input voltage. The SiC-
JFET-cascode/SiC-Schottky diode-based converter has shown
remarkably lower total power loss than the Si-MOSFET/Si-
diode-based converter. Therefore, SiC power devices have con-
siderably improved converter efficiency. The results revealed
that the switching performance and efficiency of the SEPIC
converter significantly improved when the hybrid SiC-JFET-
cascode switch/SiC-Schottky diode was used.
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