Lecture 5: Microwind/DCSH

CSCI 5330
Digital CMOS VLSI Design
Instructor: Saraju P. Mohanty, Ph. D.

NOTE: The figures, text etc included in slides are borrowed

from various books, websites, authors pages, and other
sources for academic purpose only. The instructor does
not claim any originality.

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 Lecture Outline

• Microwind Tool
• DCSH Tool
• Silicon Tool

Source:
1. http://www.microwind.org
2. Microwind Based Design (http://vsp2.ecs.umass.edu/vspg/658/
TA_Tools/microwind/Microwind.html)

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 Microwind and DSCH
• Microwind is a tool for designing and simulating circuits
at layout level. The tool features full editing facilities
(copy, cut, past, duplicate, move), various views (MOS
characteristics, 2D cross section, 3D process viewer),
and an analog simulator.
• DSCH is a software for logic design. Based on primitives,
a hierarchical circuit can be built and simulated. It also
includes delay and power consumption evaluation.
• Silicon is for 3D display of the atomic structure of silicon,
with emphasis on the silicon lattice, the dopants, and the
silicon dioxide.

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 Microwind and DSCH …
• Download the followings from
http://www.microwind.org/
–Microwind3
–DSCH3
– User Manual: http://intrage.insa-
toulouse.fr/~etienne/microwind/manual_lite.pdf
• Installation and Use:
– Unzip the files above to be able to work with
Microwind.
– Read the reference manual for the software.
– Double click on Microwind3.exe to start the layout
editor or on Dsch3.exe to start the schematic editor.

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 Tools from Microwind
http://www.microwind.org/
• Microwind
• DSCH
• Microwind3 Editor
• Microwind 2D viewer
• Microwind 3D viewer
• Microwind analog simulator
• Microwind tutorial on MOS devices
• View of Silicon Atoms

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 Microwind and DSCH : NOR Example
• We will learn both the design flow and the CAD
tools.

• The specifications we are going to see may be

different for different foundry and technology.

• Design Example (3 Levels) : NOR Gate

– Logic Design
– Circuit Design
– Layout Design

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 Microwind / DSCH NOR Example: Logic

• Open the Schematic

Editor in Microwind
(DSCH3). Click on the
transistor symbol in the
Symbol Library on the
right.
• Instantiate NMOS or
PMOS transistors from
the symbol library and
place them in the editor
window.

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 Microwind / DSCH NOR Example: Logic
• Instantiate 2 NMOS and 2 • Connect the drains and
PMOS transistors. sources of transistors.

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 Microwind / DSCH NOR Example: Logic
• Connect Vdd and GND • Connect input button and
to the schematic. output LED.

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 Microwind / DSCH NOR Example: Logic
• You now have NOR schematic
ready.
• Use your logic simulator to
verify the functionality of your
schematic.
• The next step is to simulate
the circuit and check for
functionality.
• Click on, Simulate -> Start
simulation.
• This brings up a Simulation
Control Window.
• Click on the input buttons to
set them to 1 or 0. Red color
in a switch indicates a '1'.
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 Microwind / DSCH NOR Example: Logic
• Inputs: 0 0 • Inputs: 0 1

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 Microwind / DSCH NOR Example: Logic
• Inputs: 1 0 • Inputs: 1 1

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 Microwind / DSCH NOR Example: Logic
• The simulation output can be observed as a waveform after the
application of the inputs as above. Click on the timing diagram icon in the
icon menu to see the timing diagram of the input and output waveforms.

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 Microwind / DSCH NOR Example: Circuit
• Simulate your system with • Click File -> Make Verilog
your hand calculated File. The Verilog,
Hierarchy and Netlist
transistor sizes. window appears. This
window shows the verilog
representation of NOR
gate. Click OK to save the
Verilog as a .txt file.

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 Microwind / DSCH NOR Example: Circuit
• Open the layout editor • Click on Compile ->
window in Microwind. Compile Verilog File. An
Click File -> Select Open Window appears.
Foundry and select X.rul. Select the .txt verilog file
This sets your layout saved before and open it.
designs in X technology.

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 Microwind / DSCH NOR Example: Circuit
• After selecting the .txt file, • Click on Size on the right
a new window appears top menus. This shows up
called Verilog file. the NMOS and PMOS
sizes. Set the sizes
according to choice.

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 Microwind / DSCH NOR Example: Circuit
• Click Compile and then Back • Add a capacitance to the
to editor in the Verilog File output of the design. The
Window. This creates a value of the capacitance
layout in layout editor depends on your choice.
window using automatic
layout generation procedure.

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 Microwind / DSCH NOR Example: Circuit
• Click on OK. The • Click on the label marked In1. A
capacitance is shown on window appears. Click on the
Pulse option in the window. Insert
the left bottom corner a 01 sequence for that specific
with a value of 0.015fF. input and click on Insert. Then
click on Assign. Perform this
assignment on the other inputs.

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 Microwind / DSCH NOR Example: Circuit
• Click Simulate -> Run simulation. A simulation window appears with
inputs and output, shows the tphl, tplh and tp of the circuit. The power
consumption is also shown on the right bottom portion of the window.
• If you are unable to meet the specifications of the circuit change the
transistor sizes. Generate the layout again and run the simulations till
you achieve your target delays.

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 Microwind / DSCH NOR Example: Layout
• Design the layout • Vdd and GND rails are of
manually Metal1. The top rail is used
• Open the layout editor as Vdd and the bottom one
window in Microwind. as GND. Click on Metal 1 in
Click File -> Select the palette and then create
Foundry and select X.rul the required rectangle in the
layout window.

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 Microwind / DSCH NOR Example: Layout

• The next step is to build • Then click on Generate

the NMOS transistors. device. The source of the
Click on the transistor transistor is connected to
symbol in the palette. Set the GND rail.
the W, L of the transistor.

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 Microwind / DSCH NOR Example: Layout
• Create another NMOS and • The next step is to place
place it in parallel to the first two PMOS transistors in
NMOS device. We share the series.
two devices' drain diffusions. A
DRC check can be run by
clicking on Analysis -> Design
Rule Checker.

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 Microwind / DSCH NOR Example: Layout
• Place the PMOs transistor on • The next step is to
layout close to the Vdd rail on the
top. To construct two PMOS connect the inputs and the
transistors in series, diffusions are output of the two
shifted to a side and another poly transistors.
line is added as second transistor.
The diffusion is shared to save
area and reduce capacitance.

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 Microwind / DSCH NOR Example: Layout

• The next step is to connect

• Poly inputs are connected the poly to metal1 and then
• Metal output is to metal2. The first symbol in
connected. the first row of the palette is
the poly to metal1 contact.

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 Microwind / DSCH NOR Example: Layout
• Then we connect the • The next step is to
metal1 to metal2 contact connect the output
to the previous contact. Metal1 to Metal2. Once
This is the 4th contact on again use the 4th
the first row. contact in the first row.

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 Microwind / DSCH NOR Example: Layout
• Now we connect metal2 to the two inputs and one output
and bring them to the top to go out of the cell.
• Observe the two inputs (left & right) and an output (middle)
above the Vdd rail in dark blue color.

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 Microwind / DSCH NOR Example: Layout
• Now we label the inputs and output as In1, In2 and out.
Click on Add a Pulse Symbol in the palette (5th from the
right in the 3rd row). Then click on the metal2 of one of the
inputs. A window appears. Change the name of the input
signal. Insert a 01 sequences and click on Insert. The click
on Assign. Similarly assign the 2nd input a pulse.

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 Microwind / DSCH NOR Example: Layout
• Now select the Visible Node symbol from the palette (7th
in the third row). Select it and click on the output. The 'Add
a Visible Property' window appears. Change the label
name to out. Select Visible in Simulation. Click on Assign.
Now the output is also labeled.

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 Microwind / DSCH NOR Example: Layout
• Select Vdd Supply and GND from the
palette (third row). Also click on the
capacitor (3rd in 2nd row) symbol and
add it to the output. Also, extend the p-
well into the Vdd Rail. The click on Edit
-> Generate -> Contacts. Select PATH
and then in Metal choose Metal1 and
N+ polarization.
CSCE 5730: Digital CMOS VLSI Design
• To run the Simulation of your
circuit, click on Simulate -> Start
Simulation. Depending on the input
sequences assigned at the input
the output is observed in the
simulation. The power value is also
given.
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 More Reading from Microwind Site
http://intrage.insa-toulouse.fr/~etienne/microwind/docs.html
• Introducing basic design rules. MOS design
rules, interconnect design rules, supply design
rules.
• Technology influence on design rules resistance
effect, capacitance effect, propagation.
• Specific design rules salicide, ldd, antenna ratio,
matching, supply rules, ESD.
• Introducing CMOS 90nm technology
• A very simple four-bit microprocessor designed
and simulated at gate level with DSCH3

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