KKR & KSR INSTITUTE OF TECHNOLOGY & SCIENCES

(Approved by AICTE, New Delhi, Affiliated to JNTUK Kakinada)

(Accredited by NBA , Accredited by NAAC – ‘A’ Grade )
B.Tech III Year II Sem. Regulation : R16

ECE
Date : 14/10/2020
Sections: I,II and III Academic Year :2018-19
Online Test No: 02 Max. Time : 20 Mnt

Sub Code :R1632043 Sub: VLSI Design Max Marks : 10

Answer all of the following Questions

1. In FPGA, vertical and horizontal directions are separated by [ ]

a) A line b) A channel c) A strobe d) A flip-flop
2. Which type of device FPGA are? [ ]
a) SLD b) SROM c) EPROM d) PLD
3. FPGA is [ ]
a) Digital logic design b) Analog design c)DC design d) AC design
4. In FPGA-based design, designers [ ]
(a) design the layout and fabricate the IC (b) download the bit stream to program the device.
(c) both (a) and (b) (d) none of the above
5. LUT is used in [ ]
(a) CPLD (b) ASIC (c) FPGA (d) SPLD
6. Which of the following is not a part of FPGA? [ ]
(a) RTL (b) I/O (c) PI (d) CLB
7. Different FPGA programming technologies are based on [ ]
(a) Anti-fuse (b) SRAM (c) EPROM (d) all of these
8. Testing cost is maximum at __________ level of testing. [ ]
(a) system (b) field (c) board (d) wafer
9. BIST means __________ . [ ]
(a)board integrated system testing (b) built-in system test
(c)built-in self test (d) board-in self test
10. An n-bit LFSR will cycle through __________ . [ ]
(a) 2n – 1 states (b) 2n states (c) 2n–1 states (d) 2! states
11. JTAG means __________ . [ ]
(a) joint test action group (b) joint telecom agency
(c) junior test activity guide (d) joint test activity group
12. BST was originally developed by __________ . [ ]
(a) JTAG (b) JETAG (c) IEEE (d) ANSI
13. Cost of the die depends on [ ]
(a) wafer cost (b) number of die per wafer (c) yield (d) all of these
14. Dynamic power does not depend on __________. [ ]
(a)transistor dimensions (b) load capacitance
(c)power supply voltage (d) switching activity
15. Short-circuit power dissipation does not depend on __________. [ ]
(a)power supply (b) load capacitance (c)rise/fall time (d) transistor dimensions
16. Leakage power is due to __________. [ ]
(a)subthreshold current (b) leakage current (c)both (a) and (b) (d) none of these
17. Standby mode __________ power dissipation. [ ]
(a)increases (b) decreases (c) does not cause (d) none of these
18. Battery operated devices must have __________ power dissipation. [ ]
(a)more (b) less (c) zero (d) none of these
19. Low Vt transistors consume [ ]
(a)more power (b) less power (c) no power (d) none of these
20. High Vt transistors have [ ]
(a)more speed (b) less speed (c) no speed (d) all of these