E3-238: Analog VLSI Circuits

LAB 2
Group Members: -
Abhishek Singh & Rahul Sharma

PART 1: - MOSFET CHARACTERIZATION

A) The complete small signal frequency model for the transistor about the
DC operating point is calculated as shown below: -
The gate to body, drain to body and source to body capacitances were not given
and hence taken as zero. And for the finding bulk junction built-in potential
between source/drain and substrate, the source/drain doping concentration
was assumed to be 1e20 cm -3. Then from the above analysis of the small signal
model, the parameters were for the model file were obtained as shown below: -
 Figure 1.1: - Model parameter file

B) The schematic for the various analysis based on the model template is
given below: -

Figure 1.2: -Schematic for nMOS analysis

Output Characteristics: -
For output characteristics, Vsb = 0V and Id – Vds is drawn for Vgs = linspace (0V,
VDD, 6V) and Vds = linspace (0V, VDD,100V), where VDD=1.8V.

Figure 1.3: -Output Characteristics

From the plot, we can see that as the gate voltage, Vgs, increases, output
current also increases.

Transfer Characteristics: -
For transfer characteristics, Vsb = 0V and Id – Vgs is drawn for Vds = linspace (0V,
VDD, 6V) and Vgs = linspace (0V, VDD,100V), where VDD=1.8V.

Figure 1.4: -Transfer Characteristics

From the above plot we can observe that as the drain voltage, Vds, increases,
the output current also increases, after the threshold voltage.

Back-gate Characteristics: -
For transfer characteristics, Vgs = 0V and Id – Vsb is drawn for Vds = linspace (0V,
VDD, 6V) and Vsb = linspace (0V, VDD,100V), where VDD=1.8V.

Figure 1.5: -Back-gate Characteristics

In this case the value of the current is in fA which is very small compared to
the other characteristics plot. This is because the gate terminal is grounded, so
only the leakage current is flowing.

C) Graphs for small signal quantities to bias parameters

Gm, ro, and fT v/s Vgs for Vds = 1.5V

Figure 1.6: - gm, ro and ft v/s Vgs

Gm, ro, ft v/s Id for Vds = 1.5V

Figure 1.7: -gm,ro and ft v/s Id

Gm/Id and fT v/s Id/W for Vds = 1.5V

Figure 1.8: -gm/Id v/s Id/W

Figure 1.9: -fT vs Id/W

REPEATING THE B) AND C) PART FOR nMOS OF THE
gpdk180 LIBRARY
B) Output Characteristics: -

Figure 1.10 Output Characteristics

Transfer Characteristics: -

Figure 1.11: Transfer Characteristics

Back-gate Characteristics: -

Figure 1.12: -Back-gate Characteristics

Gm, ro, and fT v/s Vgs for Vds = 1.5V

Figure 1.13: -gm and ft v/s Vgs

Figure 1.14: - ro v/s Vgs

In all the plot for output resistance, ro is taken on a log scale to have better
clarity about the range of output resistance.

Gm, ro, ft v/s Id for Vds = 1.5V

Figure 1.7: -gm and ft v/s Id

Figure 1.7: - ro v/s Id

Gm/Id and fT v/s Id/W for Vds = 1.5V

Figure 1.8: -gm/Id and ft v/s Id/W

From the various plot for nMOS of gpdk180 library and the model parameters
we had provided based on the DC operating point, we can observe there is a
difference between them.
Response by Abhishek Singh: - The square law model doesn’t take channel
length modulation into consideration. As the drain voltage keeps on increasing,
the depletion width in the substrate region also increases which changes the
effective channel length and causes pinch-off at drain voltage higher than
overdrive voltage. At this voltage, there is no channel connecting to the drain
well but due to the high electric field, the charge carriers are velocity saturated
and reaches the drain terminal making the current almost linear instead of
following the square law model.
Response by Rahul Sharma: - There is a deviation from the square law model
because of channel length modulation. When the drain to source voltage is
made greater than the overdrive voltage, the channel gets pinched off at the
drain side. This is because of the depletion width in the substrate resulting
from the reverse bias between drain and substrate. Even though the channel
gets pinched off, the current doesn’t become zero instead it becomes almost
constant because of high electric between the pinched off channel and drain
resulting in velocity saturation.
PART 2: - CURRENT MIRROR DESIGN
The nMOS used in this current mirror design is taken from the gpdk180
library.

A) To get the same current in the two nMOS i.e., Ii = Io, the W/L ratio of the
nMOS should be same. For this, we have fixed W to be 2µm and varied L
as per the question. The schematic for this part is shown below: -

Figure 2.1: -Schematic for Ii = Io

As we are providing reference current, Ii = 10µA, the current in the nMOS NM1
should also be equal to 10µA but as we are changing the output voltage, V out,
the current, Io will also change. So, by putting L = 180nm, the error
((𝐼𝑜,𝑠𝑖𝑚−𝐼𝑜)×100/𝐼o as a function of Vout is shown below: -
 Figure 2.2: - Error v/s Vout
% Error = (Io,sim – 10e-6) * 10e8; as Io = 10e-6 A.
In the above plot, y-axis shows the percentage error. It’s just that this value
was calculated in the calculator and as such had the same unit as that of
current. The curve shows the variation of error as the output voltage is varied
and one thing to note that around Vout = 0.6V, the error is zero. Therefore,
when the same current flows in nMOS NM1 as in nMOS NM0, the output
voltage is 0.6V.
Now by taking Vout as 1V, and by varying the length of the nMOS, the plot
between percentage error and length is obtained as shown below: -

Figure 2.3: - Error v/s Length

For plotting the above, the length of nMOS is varied from 180nm to 1µm and
from the figure 2.2, we can see that for output voltage, Vout = 1V, percentage
error in the Io is around 20% for L = 180nm. Therefore, in figure 2.3, the error
is starting from 20% and we can clearly see that as the length of the nMOS is
increasing, the error in the output current keeps on decreasing. Therefore, we
can reduce the error in Io by increasing the channel length, L.
As we know that channel length modulation is more dominant in small channel
as compared to long channel, therefore we should use comparatively longer
channel length to reduce the error as shown above.

B) For the plotting percentage change is output current, Io with respect to

temp, the temperature is swept from -40o C to 150o C as shown below: -

Figure 2.4: -Error v/s temperature

The change in temperature will cause the same change in the current of both
nMOS as their device parameters are same. And from the above plot, we can
observe that for Ii = Io as the temperature is increased, the percentage error in Io
decreases.
These errors are arising due to mismatch in the β (µn. Cox.W/L) value and
threshold voltage. By using the same transistor dimensions, we can eliminate
the β mismatch, but the threshold mismatch can be greatly reduced by
increasing the overdrive voltage, (Vov = Vgs – Vth).

C) Now the reference current, Ii = 100nA and the output current, Io = 1µA.
For the current to becomes 10 times the reference current, the W/L ratio
of nMOS NM1 should be 10 times of nMOS of NM0. In our experiment, we
have kept the length of both nMOS same and W of NM0 as 2µm and that
of NM1 as 20µm. The schematic for the same is shown below: -

Figure 2.5: -Schematic for Io = 10.Ii

Figure 2.6: - Error v/s Vout

For the error v/s Vout plot, length, L, is taken as 2µm and from the figure we
can see that error is zero near Vout 0.035V.
In the A) part, W = 2µm and L = 2µm. So, the estimated area of design can be
taken as: -
Area = 2 * W * L
 Area = 2 * 2 *2
 Area = 8e-12 m2
In the C) part, for NM0, W = 2µm & L = 2µm and for NM1, W = 20µm & L =
2µm. So, the estimated area of design can be taken as: -
Area = 2*2 + 20*2
 Area = 44e-12 m2

Figure 2.7: -Error v/s length

Figure 2.8: -Error v/s temperature

 D) Transient plot
The transient plot for Io = 10µA is shown below: -

Figure 2.9: -Transient plot for Io = 10µA

Figure 2.9: -Transient plot for Io = 1µA

From the above two transient plot, we observe that when the output current, I o
= 10µA, the transient period is in nA but when Io = 1µA, the transient period is
in µs. The above result can easily be explained as higher the current, lesser will
be the time taken by it to charge the gate capacitance.
PART 3: CMOS AMPLIFIER DESIGN
The derivation for the frequency dependent voltage gain, input impedances and
output impedance are shown below: -