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A B C D E

LCFC Confidential
1 1

CG413/CG513 MB Schematics Document


Intel Skylake-U22&U23/Kabylake-U22&U23 with DDR4
2 2

2016-06-12
REV:1.0

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Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 1 of 60
A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Power Plane Full ON HIGH HIGH HIGH ON ON ON ON

+3VALW +5VS S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

+5VALW +1.2V +3VS


S4 (Suspend to Disk) LOW LOW LOW ON OFF OFF OFF
1 +VCCIO 1

V20B+ +3VALW_PCH +2.5V_DDR +VCCSTG S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
+VCCSA
+1.8VALW +VCCST +VCC_GT
+1.0VALW +CPU_CORE
State +0.6VS
HSIO PORT Function BOM Structure BTO Item
1 USB3.0 Conn Left @ Not stuff
2 USB3.0 Conn Right(optional) 14@ For 14" part
3 3D Camera(optional) 15@ For 15" part
USB3.0
4 NC 14or15@ For 14" or 15" part
S0 O O O O 5 NC 14or17@ For 14" or 17" part
6 NC
1 USB3.0 Conn Left
S3 O O O X 2 USB2.0 Conn1 Right Cannonlake@ For Cannonlake part
3 USB2.0 Conn2 Right CD@ For C cost down

S3 4 Camera DUALMIC@ For Dual MIC part


2
Battery only O O O X USB2.0 5 Cardreader EMC@ For EMC part 2

6 Touch Panel EMC_15@ For EMC 15" part

S5 S4 7 Bluetooth EMC_NS@ For EMC nu-stuff part

AC Only O O X X 8 NC EMC_PX@ For EMC PX part


9 NC EMC_PXNS@ For EMC PX nu-stuff part

S5 S4 10 NC ES@ For ES CPU

Battery only O X X X 1 NC EXO@ For EXO GPU


2 NC

S5 S4 3 NC ME@ For ME part


4 NC NTS@ For nu-touch part
AC & Battery X X X X 5 LAN
don't exist
PCIE 6 WLAN
7 used as SATA
SMBUS Control Table 8 used as SATA PX@ For PX part
RANKA@ For VRAM rank A part
SOURCE BATT Charger DGPU IT8586E Memory PCH PMIC SODIMM Thermal WLAN RANKB@ For VRAM rank B part
Down Sensor WiMAX 9~12 DGPU
Realtek_SD@ For Realtek SD part
X4 PCIE
3
SINGLEMIC@ For single MIC part
3
EC_SMB_CK1 IT8586E
V V X V X X X X X X 0 HDD SINGLERANK@ For single VRAN rank part
EC_SMB_DA1 +3VL_EC +3VL_EC 1A ODD DUALRANK@ For dual VRAN rank part
SATA 1B used as PCIE TS@ For touch screen part
EC_SMB_CK2 IT8586E
X X V V X V X X V X 2 used as PCIE TPM@ For TPM part
EC_SMB_DA2 +3VS +3VG_AON +3VS +3VALW_PCH UMA@ For UMA part

EC_SMB_CK3 IT8586E
X X X V X X V X X X
EC_SMB_DA3 +3VL_EC +3VL_EC

PCH_SMB_CLK PCH
X X X X X V X V X V
PCH_SMB_DATA +3VALW_PCH +3VALW_PCH +3VS +3VS

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address


Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7718W) 1001_100xb PMIC need to update DDR4 SODIMM need to update
4 4
Charger 0001 0010 b PCH need to update W lan Reserved
DGPU need to update

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Notes List


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 3 of 60
A B C D E
5 4 3 2 1

SKL_ULT ?
UC1A
HDMI_TX2- E55 C47 CPU_EDP_TX0-
34 HDMI_TX2- HDMI_TX2+ DDI1_TXN[0] EDP_TXN[0] CPU_EDP_TX0+ CPU_EDP_TX0- 33
HDMI D2 34 HDMI_TX2+
F55
DDI1_TXP[0] EDP_TXP[0]
C46
CPU_EDP_TX0+ 33 confirmed with ITE, the HPD
D HDMI_TX1- E58 D46 CPU_EDP_TX1- D
34 HDMI_TX1- HDMI_TX1+ DDI1_TXN[1] EDP_TXN[1] CPU_EDP_TX1+ CPU_EDP_TX1- 33 pull down resistor should follow
HDMI D1 F58 C45 ITE recommended resistor 4.7k~10Kohm
34 HDMI_TX1+ HDMI_TX0- DDI1_TXP[1] EDP_TXP[1] CPU_EDP_TX1+ 33
F53 A45
34 HDMI_TX0- HDMI_TX0+ DDI1_TXN[2] EDP_TXN[2]
HDMI D0 G53 B45
34 HDMI_TX0+ HDMI_CLK- DDI1_TXP[2] EDP_TXP[2]
F56 A47
34 HDMI_CLK- HDMI_CLK+ DDI1_TXN[3] EDP_TXN[3]
HDMI CLK G56 B47
34 HDMI_CLK+ DDI1_TXP[3] EDP_TXP[3] +3VS
VGA_TX0- C50 E45 CPU_EDP_AUX#
35 VGA_TX0- VGA_TX0+ DDI2_TXN[0] DDI EDP_AUXN CPU_EDP_AUX CPU_EDP_AUX# 33
D50 EDP F45
35 VGA_TX0+ VGA_TX1- DDI2_TXP[0] EDP_AUXP CPU_EDP_AUX 33
DP TO VGA Converter C52
35 VGA_TX1- VGA_TX1+ DDI2_TXN[1] GPP_E15
D52 B52 RC1601 1 @ 2 10K_0402_5%
35 VGA_TX1+ DDI2_TXP[1] EDP_DISP_UTIL
A50
B50 DDI2_TXN[2] G50
D51 DDI2_TXP[2] DDI1_AUXN F50
DDI2_TXN[3] DDI1_AUXP VGA_AUX#

2
C51 E48
DDI2_TXP[3] DDI2_AUXN VGA_AUX VGA_AUX# 35
F48 RC37
DDI2_AUXP G46 VGA_AUX 35 100K_0402_5%
DISPLAY SIDEBANDS DDI3_AUXN F46
DDPB_CLK L13 DDI3_AUXP
GPP_E18/DDPB_CTRLCLK

1
34 DDPB_CLK DDPB_DATA L12 L9 HDMI_HPD
34 DDPB_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0 DP_VGA_HPD HDMI_HPD 34
L7
DDPC_CLK GPP_E14/DDPC_HPD1 GPP_E15 DP_VGA_HPD 35
N7 L6 RC181 1 @ 2 0_0402_5%
DDPC_DATA GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 EC_SCI# 44
N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3 L10 CPU_EDP_HPD
GPP_E17/EDP_HPD CPU_EDP_HPD 33
N11
GPP_E22/DDPD_CTRLCLK PCH_ENBKL

1
+VCCIO N12 R12
GPP_E23/DDPD_CTRLDATA EDP_BKLTEN PCH_EDP_PWM PCH_ENBKL 33
R11 RC13
RC4 2 1 24.9_0402_1% EDP_COMP E52 EDP_BKLTCTL U13 PCH_ENVDD PCH_EDP_PWM 33 100K_0402_5%
EDP_RCOMP EDP_VDDEN PCH_ENVDD 33
1 OF 20
+VCCIO&EDP_COMP : SKYLAKE-U_BGA1356

2
Trace Width: 20mil REV = 1 ?
+VCCST_CPU
Isolation Spacing: 25mil @
C C
Max length: 100mil

1
+VCCSTG
RC1625
@ 49.9_0402_1%
1

RC19 UC1D SKL_ULT ?

2
1K_0402_5% XDP_TCK RC1546 1 @ 2 0_0402_5% JTAGX RC1551 1 2 51_0402_5%
check PROCHOT# circuit with PWR CATERR# D63
H_PECI A54 CATERR# XDP_TDO RC1547 1 @ 2 0_0402_5% PCH_JTAG_TDO RC1543 1 2 51_0402_5%
44 H_PECI H_PROCHOT#_R PECI +VCCSTG
2

RC20 1 2 499 +-1% 0402 C65 JTAG


44,55 H_PROCHOT# H_THRMTRIP# PROCHOT#
C63
A65 THERMTRIP# B61 XDP_TCK 1 PAD @ XDP_TDI RC1548 1 @ 2 0_0402_5% PCH_JTAG_TDI
SKTOCC# PROC_TCK XDP_TDI TC15
CPU MISC D60 1 PAD @
XDP_BPM0# PROC_TDI XDP_TDO TC16 XDP_TMS PCH_JTAG_TMS
1

PAD @ TC11 1 C55 A61 1 PAD @ RC1549 1 @ 2 0_0402_5%


XDP_BPM1# BPM#[0] PROC_TDO XDP_TMS TC17
RC143 PAD @ TC12 1 D55 C60 1 PAD @
XDP_BPM2# BPM#[1] PROC_TMS XDP_TRST# TC18 XDP_TRST# PCH_JTAG_TRST#
1K_0402_5% PAD @ TC13 1 B54 B59 1 PAD @ RC1550 1 @ 2 0_0402_5%
XDP_BPM3# BPM#[2] PROC_TRST# TC27
PAD @ TC14 1 C56
BPM#[3] B56 PCH_JTAG_TCK 1 PAD @
GPP_E3 PCH_JTAG_TCK PCH_JTAG_TDI TC29
2

PAD @ TC162 1 A6 D59 1 PAD @ check JTAG circuit?


GPP_E7 GPP_E3/CPU_GP0 PCH_JTAG_TDI PCH_JTAG_TDO TC31
+VCCST_CPU PAD @ TC163 1 A7 A56 1 PAD @
GPP_E7/CPU_GP1 PCH_JTAG_TDO PCH_JTAG_TMS TC35
BA5 C59 1 PAD @
GPP_B3/CPU_GP2 PCH_JTAG_TMS PCH_JTAG_TRST# TC36
check H_THRMTRIP# if need to connector to EC AY5 C61 1 PAD @
GPP_B4/CPU_GP3 PCH_TRST# TC42
A59 JTAGX 1 PAD @
PROC_OPI_RCOMP JTAGX TC43
RC155 1 2 49.9_0402_1% AT16
RC156 1 2 49.9_0402_1% PCH_OPI_RCOMP AU16 PROC_POPIRCOMP
U23E@ RC157 1 2 49.9_0402_1% EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
U23E@ RC170 1 2 49.9_0402_1% EOPIO_RCOMP H65 OPCE_RCOMP
OPC_RCOMP

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

check DDPC_CLK pull high or not?


+3VS

RPC19
8 1 DDPC_CLK
7 2 DDPC_DATA
6 3 DDPB_CLK
5 4 DDPB_DATA

2.2K_0804_8P4R_5%

DDP*_CTRLDATA strapping sampled on the rising edge of PWROK

Port Strap Enable Disable


Pull up to 3.3 V
Port 1 DDPB_CTRLDATA with 2.2Kohm NC
Pull up to 3.3 V
Port 2 DDPC_CTRLDATA with 2.2Kohm NC

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDI,EDP)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 4 of 60
5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1B

AU53
17 DDRA_DQ[0..63] DDRA_DQ0 DDR0_CKN[0] DDRA_CLK0# 17
AL71 AT53
DDRA_DQ1 AL68 DDR0_DQ[0] DDR0_CKP[0] AU55 DDRA_CLK0 17
DDRA_DQ2 AN68 DDR0_DQ[1] DDR0_CKN[1] AT55
DDRA_DQ3 AN69 DDR0_DQ[2] DDR0_CKP[1]
DDRA_DQ4 AL70 DDR0_DQ[3] BA56
DDRA_DQ5 DDR0_DQ[4] DDR0_CKE[0] DDRA_CKE0 17
AL69 BB56
DDRA_DQ6 AN70 DDR0_DQ[5] DDR0_CKE[1] AW56
DDRA_DQ7 AN71 DDR0_DQ[6] DDR0_CKE[2] AY56
DDRA_DQ8 AR70 DDR0_DQ[7] DDR0_CKE[3]
D DDRA_DQ9 AR68 DDR0_DQ[8] AU45 D
DDRA_DQ10 DDR0_DQ[9] DDR0_CS#[0] DDRA_CS0# 17
AU71 AU43
DDRA_DQ11 AU68 DDR0_DQ[10] DDR0_CS#[1] AT45
DDRA_DQ12 AR71 DDR0_DQ[11] DDR0_ODT[0] AT43 DDRA_ODT0 17
DDRA_DQ13 AR69 DDR0_DQ[12] DDR0_ODT[1]
DDRA_DQ14 AU70 DDR0_DQ[13] BA51
DDRA_DQ15 DDR0_DQ[14] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDRA_MA5 17
AU69 BB54
DDRA_DQ16 BB65 DDR0_DQ[15] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] BA52 DDRA_MA9 17
DDRA_DQ17 AW65 DDR0_DQ[16]/DDR0_DQ[32] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] AY52 DDRA_MA6 17
DDRA_DQ18 AW63 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] AW52 DDRA_MA8 17
DDRA_DQ19 AY63 DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] AY55 DDRA_MA7 17
DDRA_DQ20 DDR0_DQ[19]/DDR0_DQ[35] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDRA_BG0 17
BA65 AW54
DDRA_DQ21 AY65 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDRA_MA12 17
BA54
DDRA_DQ22 BA63 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] BA55 DDRA_MA11 17
DDRA_DQ23 BB63 DDR0_DQ[22]/DDR0_DQ[38] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# AY54 DDRA_ACT# 17
DDRA_DQ24 BA61 DDR0_DQ[23]/DDR0_DQ[39] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDRA_DQ25 AW61 DDR0_DQ[24]/DDR0_DQ[40] AU46
DDRA_DQ26 BB59 DDR0_DQ[25]/DDR0_DQ[41] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] AU48 DDRA_MA13 17
DDRA_DQ27 AW59 DDR0_DQ[26]/DDR0_DQ[42] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] AT46 DDRA_MA15_CAS# 17
DDRA_DQ28 BB61 DDR0_DQ[27]/DDR0_DQ[43] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] AU50 DDRA_MA14_WE# 17
DDRA_DQ29 AY61 DDR0_DQ[28]/DDR0_DQ[44] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] AU52 DDRA_MA16_RAS# 17
DDRA_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDRA_BS0# 17
BA59 AY51
DDRA_DQ31 AY59 DDR0_DQ[30]/DDR0_DQ[46] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] AT48 DDRA_MA2 17
DDRA_DQ32 AY39 DDR0_DQ[31]/DDR0_DQ[47] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDRA_BS1# 17
AT50
DDRA_DQ33 AW39 DDR0_DQ[32]/DDR1_DQ[0] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDRA_MA10 17
BB50
DDRA_DQ34 AY37 DDR0_DQ[33]/DDR1_DQ[1] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDRA_MA1 17
AY50
DDRA_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDRA_MA0 17
AW37 BA50
DDRA_DQ36 BB39 DDR0_DQ[35]/DDR1_DQ[3] DDR0_MA[3] BB52 DDRA_MA3 17
DDRA_DQ37 BA39 DDR0_DQ[36]/DDR1_DQ[4] DDR0_MA[4] DDRA_MA4 17
DDRA_DQ38 BA37 DDR0_DQ[37]/DDR1_DQ[5] AM70 DDRA_DQS#0
DDRA_DQ39 BB37 DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQSN[0] AM69 DDRA_DQS0
DDRA_DQ40 AY35 DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQSP[0] AT69 DDRA_DQS#1
C DDRA_DQ41 AW35 DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQSN[1] AT70 DDRA_DQS1 C
DDRA_DQ42 AY33 DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQSP[1] BA64 DDRA_DQS#2
DDRA_DQ43 AW33 DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQSN[2]/DDR0_DQSN[4] AY64 DDRA_DQS2 DDRA_DQS#[0..7]
DDRA_DQ44 BB35 DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQSP[2]/DDR0_DQSP[4] AY60 DDRA_DQS#3 DDRA_DQS#[0..7] 17
DDRA_DQ45 BA35 DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQSN[3]/DDR0_DQSN[5] BA60 DDRA_DQS3 DDRA_DQS[0..7]
DDRA_DQ46 BA33 DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQSP[3]/DDR0_DQSP[5] BA38 DDRA_DQS#4 DDRA_DQS[0..7] 17
DDRA_DQ47 BB33 DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQSN[4]/DDR1_DQSN[0] AY38 DDRA_DQS4
DDRA_DQ48 AY31 DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQSP[4]/DDR1_DQSP[0] AY34 DDRA_DQS#5
DDRA_DQ49 AW31 DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQSN[5]/DDR1_DQSN[1] BA34 DDRA_DQS5
DDRA_DQ50 AY29 DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQSP[5]/DDR1_DQSP[1] BA30 DDRA_DQS#6
DDRA_DQ51 AW29 DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQSN[6]/DDR1_DQSN[4] AY30 DDRA_DQS6
DDRA_DQ52 BB31 DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQSP[6]/DDR1_DQSP[4] AY26 DDRA_DQS#7
DDRA_DQ53 BA31 DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQSN[7]/DDR1_DQSN[5] BA26 DDRA_DQS7
DDRA_DQ54 BA29 DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQSP[7]/DDR1_DQSP[5]
DDRA_DQ55 BB29 DDR0_DQ[54]/DDR1_DQ[38] AW50
DDRA_DQ56 AY27 DDR0_DQ[55]/DDR1_DQ[39] DDR0_ALERT# AT52 DDRA_ALERT# 17
DDRA_DQ57 AW27 DDR0_DQ[56]/DDR1_DQ[40] DDR0_PAR DDRA_PAR 17
DDRA_DQ58 DDR0_DQ[57]/DDR1_DQ[41] SMVREF
AY25 AY67 WIDTH:20MIL
DDRA_DQ59 AW25 DDR0_DQ[58]/DDR1_DQ[42] DDR_VREF_CA AY68 DDR_SA_VREFCA 17
DDRA_DQ60 DDR0_DQ[59]/DDR1_DQ[43] DDR0_VREF_DQ SPACING: 20MIL
BB27 DDR CH - A BA67
DDRA_DQ61 BA27 DDR0_DQ[60]/DDR1_DQ[44] DDR1_VREF_DQ DDR_SB_VREFCA 18
DDRA_DQ62 BA25 DDR0_DQ[61]/DDR1_DQ[45] AW67 DDR_VTT_CNTL
DDRA_DQ63 BB25 DDR0_DQ[62]/DDR1_DQ[46] DDR_VTT_CNTL
DDR0_DQ[63]/DDR1_DQ[47]
1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@

B B

+3VALW

RC30
100K_0402_5%
2

CPU_DRAMPG_CNTL 55
+1.2V
1

C
RC3 1 2 2 QC18
1K_0402_5% B
E
3

MMBT3904WH_SOT323-3

DDR_VTT_CNTL
2

RC29
10K_0402_5%
@
1

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 5 of 60
5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1C
18 DDRB_DQ[0..63]

DDRB_DQ0 AF65 AN45


DDRB_DQ1 AF64 DDR1_DQ[0]/DDR0_DQ[16] DDR1_CKN[0] AN46 DDRB_CLK0# 18
DDRB_DQ2 AK65 DDR1_DQ[1]/DDR0_DQ[17] DDR1_CKN[1] AP45 DDRB_CLK1# 18
DDRB_DQ3 AK64 DDR1_DQ[2]/DDR0_DQ[18] DDR1_CKP[0] AP46 DDRB_CLK0 18
DDRB_DQ4 AF66 DDR1_DQ[3]/DDR0_DQ[19] DDR1_CKP[1] DDRB_CLK1 18
D DDRB_DQ5 AF67 DDR1_DQ[4]/DDR0_DQ[20] AN56 D
DDRB_DQ6 AK67 DDR1_DQ[5]/DDR0_DQ[21] DDR1_CKE[0] AP55 DDRB_CKE0 18
DDRB_DQ7 AK66 DDR1_DQ[6]/DDR0_DQ[22] DDR1_CKE[1] AN55 DDRB_CKE1 18
DDRB_DQ8 AF70 DDR1_DQ[7]/DDR0_DQ[23] DDR1_CKE[2] AP53
DDRB_DQ9 AF68 DDR1_DQ[8]/DDR0_DQ[24] DDR1_CKE[3]
DDRB_DQ10 AH71 DDR1_DQ[9]/DDR0_DQ[25] BB42
DDRB_DQ11 AH68 DDR1_DQ[10]/DDR0_DQ[26] DDR1_CS#[0] AY42 DDRB_CS0# 18
DDRB_DQ12 AF71 DDR1_DQ[11]/DDR0_DQ[27] DDR1_CS#[1] BA42 DDRB_CS1# 18
DDRB_DQ13 AF69 DDR1_DQ[12]/DDR0_DQ[28] DDR1_ODT[0] AW42 DDRB_ODT0 18
DDRB_DQ14 AH70 DDR1_DQ[13]/DDR0_DQ[29] DDR1_ODT[1] DDRB_ODT1 18
DDRB_DQ15 AH69 DDR1_DQ[14]/DDR0_DQ[30] AY48
DDRB_DQ16 AT66 DDR1_DQ[15]/DDR0_DQ[31] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] AP50 DDRB_MA5 18
DDRB_DQ17 AU66 DDR1_DQ[16]/DDR0_DQ[48] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] BA48 DDRB_MA9 18
DDRB_DQ18 AP65 DDR1_DQ[17]/DDR0_DQ[49] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] BB48 DDRB_MA6 18
DDRB_DQ19 AN65 DDR1_DQ[18]/DDR0_DQ[50] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] AP48 DDRB_MA8 18
DDRB_DQ20 AN66 DDR1_DQ[19]/DDR0_DQ[51] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] AP52 DDRB_MA7 18
DDRB_DQ21 AP66 DDR1_DQ[20]/DDR0_DQ[52] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] AN50 DDRB_BG0 18
DDRB_DQ22 AT65 DDR1_DQ[21]/DDR0_DQ[53] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] AN48 DDRB_MA12 18
DDRB_DQ23 AU65 DDR1_DQ[22]/DDR0_DQ[54] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] AN53 DDRB_MA11 18
DDRB_DQ24 AT61 DDR1_DQ[23]/DDR0_DQ[55] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# AN52 DDRB_ACT# 18
DDRB_DQ25 AU61 DDR1_DQ[24]/DDR0_DQ[56] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDRB_BG1 18
DDRB_DQ26 AP60 DDR1_DQ[25]/DDR0_DQ[57] BA43
DDRB_DQ27 AN60 DDR1_DQ[26]/DDR0_DQ[58] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] AY43 DDRB_MA13 18
DDRB_DQ28 AN61 DDR1_DQ[27]/DDR0_DQ[59] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] AY44 DDRB_MA15_CAS# 18
DDRB_DQ29 AP61 DDR1_DQ[28]/DDR0_DQ[60] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] AW44 DDRB_MA14_WE# 18
DDRB_DQ30 AT60 DDR1_DQ[29]/DDR0_DQ[61] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] BB44 DDRB_MA16_RAS# 18
DDRB_DQ31 AU60 DDR1_DQ[30]/DDR0_DQ[62] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] AY47 DDRB_BS0# 18
DDRB_DQ32 AU40 DDR1_DQ[31]/DDR0_DQ[63] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] BA44 DDRB_MA2 18
DDRB_DQ33 AT40 DDR1_DQ[32]/DDR1_DQ[16] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] AW46 DDRB_BS1# 18
DDRB_DQ34 AT37 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] AY46 DDRB_MA10 18
DDRB_DQ35 AU37 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] BA46 DDRB_MA1 18
DDRB_DQ36 AR40 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] BB46 DDRB_MA0 18
C DDRB_DQ37 AP40 DDR1_DQ[36]/DDR1_DQ[20] DDR1_MA[3] BA47 DDRB_MA3 18 C
DDRB_DQ38 AP37 DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[4] DDRB_MA4 18
DDRB_DQ39 AR37 DDR1_DQ[38]/DDR1_DQ[22] AH66 DDRB_DQS#0
DDRB_DQ40 AT33 DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQSN[0]/DDR0_DQSN[2] AH65 DDRB_DQS0
DDRB_DQ41 AU33 DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQSP[0]/DDR0_DQSP[2] AG69 DDRB_DQS#1
DDRB_DQ42 AU30 DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQSN[1]/DDR0_DQSN[3] AG70 DDRB_DQS1
DDRB_DQ43 AT30 DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQSP[1]/DDR0_DQSP[3] AR66 DDRB_DQS#2
DDRB_DQ44 AR33 DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQSN[2]/DDR0_DQSN[6] AR65 DDRB_DQS2
DDRB_DQ45 AP33 DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQSP[2]/DDR0_DQSP[6] AR61 DDRB_DQS#3 DDRB_DQS#[0..7]
DDRB_DQ46 AR30 DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQSN[3]/DDR0_DQSN[7] AR60 DDRB_DQS3 DDRB_DQS#[0..7] 18
DDRB_DQ47 AP30 DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQSP[3]/DDR0_DQSP[7] AT38 DDRB_DQS#4 DDRB_DQS[0..7]
DDRB_DQ48 AU27 DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQSN[4]/DDR1_DQSN[2] AR38 DDRB_DQS4 DDRB_DQS[0..7] 18
DDRB_DQ49 AT27 DDR1_DQ[48] DDR1_DQSP[4]/DDR1_DQSP[2] AT32 DDRB_DQS#5
DDRB_DQ50 AT25 DDR1_DQ[49] DDR1_DQSN[5]/DDR1_DQSN[3] AR32 DDRB_DQS5
DDRB_DQ51 AU25 DDR1_DQ[50] DDR1_DQSP[5]/DDR1_DQSP[3] AR25 DDRB_DQS#6
DDRB_DQ52 AP27 DDR1_DQ[51] DDR1_DQSN[6] AR27 DDRB_DQS6
DDRB_DQ53 AN27 DDR1_DQ[52] DDR1_DQSP[6] AR22 DDRB_DQS#7
DDRB_DQ54 AN25 DDR1_DQ[53] DDR1_DQSN[7] AR21 DDRB_DQS7
DDRB_DQ55 AP25 DDR1_DQ[54] DDR1_DQSP[7]
DDRB_DQ56 AT22 DDR1_DQ[55] AN43
DDRB_DQ57 AU22 DDR1_DQ[56] DDR1_ALERT# AP43 DDRB_ALERT# 18
DDRB_DQ58 AU21 DDR1_DQ[57] DDR1_PAR AT13 CPU_DRAMRST#_R DDRB_PAR 18
DDRB_DQ59 AT21 DDR1_DQ[58] DRAM_RESET# AR18 SM_RCOMP_0 RC24 1 2 121_0402_1%
DDRB_DQ60 AN22 DDR1_DQ[59] DDR_RCOMP[0] AT18 SM_RCOMP_1 RC25 1 2 80.6_0402_1%
DDRB_DQ61 AP22 DDR1_DQ[60] DDR_RCOMP[1] AU18 SM_RCOMP_2 RC26 1 2 100_0402_1%
DDRB_DQ62 AP21 DDR1_DQ[61] DDR_RCOMP[2]
DDRB_DQ63 AN21 DDR1_DQ[62] DDR CH - B
DDR1_DQ[63]

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
B @ B

+1.2V

1
RC22
2 470_0402_5%

RC23 1 @ 2 0_0402_5% CPU_DRAMRST#_R


17,18 CPU_DRAMRST#
1
CC1
0.01U_0201_25V6-K
EMC_NS@
2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (DDR4)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 6 of 60
5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1E
+3VALW_PCH +3VS +3VS
SPI - FLASH
SMBUS, SMLINK
SPI_CLK RC1539 1 2 15_0402_5% SPI_CLK_R SPI_CLK_R AV2 R7 PCH_SMB_CLK
44 SPI_CLK SPI_CLK_1 SPI_SO_R SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA
RC1538 1 @ 2 33_0402_5% AW3 R8 DIMM, NGFF
SPI_SI_R AV3 SPI0_MISO GPP_C1/SMBDATA R10 SMB_ALERT#
SPI_WP#_R SPI0_MOSI GPP_C2/SMBALERT#

3
4

4
3
AW2
SPI_SO RC53 1 2 15_0402_5% SPI_SO_R SPI_HOLD#_R AU4 SPI0_IO2 R9 SML0_CLK RPC20 RPC24
44 SPI_SO SPI_SO_1 SPI_CS0#_R SPI0_IO3 GPP_C3/SML0CLK SML0_DATA

2
RC177 1 @ 2 33_0402_5% AU3 W2 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5%

G
D SPI_CS1#_R AU2 SPI0_CS0# GPP_C4/SML0DATA W1 SML0_ALERT# D
AU1 SPI0_CS1# GPP_C5/SML0ALERT#
SPI0_CS2# PCH_SML1_CLK

2
1

1
2
W3
SPI_SI RC52 1 2 15_0402_5% SPI_SI_R GPP_C6/SML1CLK V3 PCH_SML1_DAT PCH_SMB_CLK QC2A 6 1
44 SPI_SI GPP_C7/SML1DATA GPU, EC, Thermal Sensor SMB_CLK_S3 18,40

S
SPI_SI_1 RC175 1 @ 2 33_0402_5% SPI - TOUCH AM7 SML1_ALERT#

D
M2 GPP_B23/SML1ALERT#/PCHHOT# 2N7002KDWH_SOT363-6
GPP_D1/SPI1_CLK

5
M3

G
J4 GPP_D2/SPI1_MISO
SPI_CS0# RC51 1 @ 2 0_0402_5% SPI_CS0#_R V1 GPP_D3/SPI1_MOSI
44 SPI_CS0# SPI_CS1# SPI_CS1#_R GPP_D21/SPI1_IO2
RC174 1 @ 2 0_0402_5% V2
BOARD_ID4 M1 GPP_D22/SPI1_IO3 AY13 PCH_SMB_DATA QC2B 3 4
8 BOARD_ID4 LPC LPC_AD0 32,44 SMB_DATA_S3 18,40
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0

S
BA13

D
GPP_A2/LAD1/ESPI_IO1 LPC_AD1 32,44
BB13 2N7002KDWH_SOT363-6
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_AD2 32,44
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_AD3 32,44
G3 BA12
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT# LPC_FRAME# 32,44
G2 BA11 1
G1 CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET# TC81@
CL_RST#
AW9 CLK_PCI_EC_R RC173 2 1 22_0402_5%
+3V_SPI GPP_A9/CLKOUT_LPC0/ESPI_CLK CLK_PCI_TPM_R CLK_PCI_EC 44
KBRST# AW13 AY9 RC1541 2 TPM@ 1 22_0402_5%
44 KBRST# GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 PM_CLKRUN# CLK_PCI_TPM 32
AW11
GPP_A8/CLKRUN# PM_CLKRUN# 32 +3VALW_PCH
SERIRQ AY11
32,44 SERIRQ GPP_A6/SERIRQ

1 OF 20 SMB_ALERT#
1

2 1 RC1562
SKYLAKE-U_BGA1356
RC60 RC61 REV = 1 2.2K_0402_5%
?
1K_0402_5% 1K_0402_5%
Check with BIOS, SPI is Dual mode or quad mode @
2

SPI_WP#_R RC54 1 @ 2 15_0402_5% SPI_WP#


+3VALW_PCH
C +3V_SPI check CLKRUN# / SUS_STAT# signal if need to connect +3VS C
SPI_HOLD#_R RC55 1 @ 2 15_0402_5% SPI_HOLD# RPC23
+3VS +3VALW_PCH SML0_CLK 4 1
SML0_DATA 3 2
RC171 1 @ 2 0_0402_5% PM_CLKRUN# RC11 1 2 8.2K_0402_5%
2.2K_0404_4P2R_5%
RC172 1 @ 2 0_0402_5%
SERIRQ RC12 1 2 10K_0402_5%
+3V_SPI
* +3V_SPI
+3VALW_PCH
1. If support DS3, connect to +3VS and don't support EC mirror code; KBRST# RC10 1 2 10K_0402_5%
2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code.
SML0_ALERT#
1

RC1564 2 @ 1 2.2K_0402_5%
RC179 RC180
1K_0402_5% 1K_0402_5% KBRST# CC1255 1 2 1000P_0201_50V7-K
@ @ This signal has a weak internal pull-down.
EMC_NS@ 0 = LPC Is selected for EC. (Default)
2

SPI_WP#_R RC176 1 @ 2 33_0402_5% SPI_WP#_1 1 = eSPI Is selected for EC.


Notes:
1. The internal pull-down is disabled after RSMRST#
SPI_HOLD#_R RC178 1 @ 2 33_0402_5% SPI_HOLD#_1 de-asserts.
2. This signal is in the primary wel
+3V_SPI Rising edge of RSMRST#
+3VALW_PCH
UC3
SPI_CS0# 1 8
CS# VCC SML1_ALERT# RC1569 1 2 150K_0402_5%
SPI_SO 2 7 SPI_HOLD#
DO HOLD# 1
CC8
+3VALW_PCH Follow CRB, need to check the strap ? SPI_WP# 3 6 SPI_CLK 0.1u_0201_10V6K
B WP# CLK B
4 5 SPI_SI 2
RC1568 2 @ 1 20K_0402_5% SPI_SO_R GND DI +3VALW_PCH +3VS To enable Direct Connect Interface (DCI), a 150K pull up resistor will need to be
SPI_SI_R added to PCHHOT# pin. This pin must be low during the rising edge of RSMRST#.
RC1565 2 @ 1 20K_0402_5% W25Q64FVSSIQ_SO8
(Refer to WW52_MOW)
RC1578 2 @ 1 20K_0402_5% SPI_WP#_R

4
3
RC1580 2 @ 1 20K_0402_5% SPI_HOLD#_R RPC25
+3V_SPI

2
2.2K_0404_4P2R_5%

G
UC6
SPI_CS1#

1
2
1 8
SPI_SO_1 2 CS# VCC 7 SPI_HOLD#_1 PCH_SML1_CLK QC10A 6 1 @
DO HOLD# EC_SMB_CK2 39,44

S
SPI_WP#_1 3 6 SPI_CLK_1

D
WP# CLK SPI_SI_1 1
Follow CRB, need to check the strap ? 4 5 CC97 2N7002KDWH_SOT363-6
GND DI

5
0.1u_0201_10V6K

G
W25Q32FVSSIQ_SO8 @
RC1567 2 @ 1 4.7K_0402_5% SPI_SO_R @ 2

RC1566 2 @ 1 4.7K_0402_5% SPI_SI_R PCH_SML1_DAT QC10B 3 4 @


EC_SMB_DA2 39,44

S
D
RC1581 2 @ 1 4.7K_0402_5% SPI_WP#_R 2N7002KDWH_SOT363-6

RC64 1 ES@ 2 1K_0402_5% SPI_HOLD#_R

Based on WW36 SKL U&Y WOM, RC64 populated,


and RC61 de-populated for SKL U ES sample.
In this case, customers must ensure that the
A SPI flash device on the platform A
has HOLD functionality disabled by default.

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (MISC,JTAG,SPI,LPC,SMB)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 7 of 60
5 4 3 2 1
5 4 3 2 1

+3VS

DUALRANK@ DUALMIC@
SKL_ULT ?
UC1F

1 RC1615 2

1 RC1613 2

1 RC1611 2

1 RC1609 2

1 RC1606 2
17@ 15@ TS@ OPT@

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
LPSS ISH

RC1608
AN8 P2 BOARD_ID0
AP7 GPP_B15/GSPI0_CS# GPP_D9 P3 BOARD_ID1
GPP_B16/GSPI0_CLK GPP_D10

1
AP8 P4
RC1561 1 @ 2 2.2K_0402_5% GPP_B18 AR7 GPP_B17/GSPI0_MISO GPP_D11 P1 BOARD_ID3 BOARD_ID0
+3VS GPP_B18/GSPI0_MOSI GPP_D12 BOARD_ID1
AM5 M4 BOARD_ID6 BOARD_ID2
PCH_CMOS_ON# AN7 GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA N3 BOARD_ID5 9 BOARD_ID2 BOARD_ID3
33 PCH_CMOS_ON# AP5 GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL BOARD_ID4
D GPP_B21/GSPI1_MISO 7 BOARD_ID4 D
RC1563 1 @ 2 2.2K_0402_5% GPP_B22 AN5 N1 BOARD_ID7 BOARD_ID5
GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA N2 BOARD_ID8
AB1 GPP_D8/ISH_I2C1_SCL
40 UART_RX_DEBUG AB2 GPP_C8/UART0_RXD AD11 SINGLERANK@
SINGLEMIC@

10K_0402_5%
40 UART_TX_DEBUG GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA

1 RC1616 2

1 RC1614 2

1 RC1612 2

1 RC1610 2

1 RC1607 2

1 RC123 2
W4 AD12 14or15@ 14or17@ NTS@ UMA@

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
AB3 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_C11/UART0_CTS#
AD1 U1
RC1558 1 UMA@ 2 10K_0402_5% DGPU_PWROK AD2 GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA U2
DGPU_PWROK AD3 GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL U3
AD4 GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# U4
GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT#
AC1
U7 GPP_C12/UART1_RXD/ISH_UART1_RXD AC2
U6 GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD AC3
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# AB4
PCH_WLAN_OFF# U8 GPP_C15/UART1_CTS#/ISH_UART1_CTS#
40 PCH_WLAN_OFF# PCH_BT_OFF# U9 GPP_C18/I2C1_SDA AY8
40 PCH_BT_OFF# GPP_C19/I2C1_SCL GPP_A18/ISH_GP0 BA8
GPP_A19/ISH_GP1
Board ID Description Stuff R
AH9 BB7
AH10 GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 BA7
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3
00 14" RC1616 RC1614
AY7
AH11 GPP_A22/ISH_GP4 AW7
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5
Board_ID[0:1] 01 15" RC1616 RC1613
+3VS AH12 AP13
GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6
10 17" RC1615 RC1614
AF11
AF12 GPP_F8/I2C4_SDA
GPP_F9/I2C4_SCL
11 Reserved

PCH_CMOS_ON# 1 OF 20
Board_ID2 0 Non-touch RC1612
RC1595 2 @ 1 10K_0402_5% SKYLAKE-U_BGA1356
RC1596 2 1 10K_0402_5% PCH_WLAN_OFF#
PCH_BT_OFF#
REV = 1 ? 1 Touch RC1611
RC1597 2 1 10K_0402_5% @
UC1G SKL_ULT ? Board_ID3 0 UMA RC1610
double check if need the pull up resisor
AUDIO 1 DIS RC1609
RC43 1 2 33_0402_5% HDA_SYNC BA22
C 43 HDA_SYNC_AUDIO HDA_BCLK HDA_SYNC/I2S0_SFRM
Board_ID4 0 SingleRankRC1607 C
RC42 1 2 33_0402_5% AY22
+3VALW_PCH +3VS 43 HDA_BITCLK_AUDIO HDA_SDOUT BB22 HDA_BLK/I2S0_SCLK
HDA_SDIN0 HDA_SDO/I2S0_TXD
SDIO/SDXC 1 DualRank RC1608
BA21
43 HDA_SDIN0 HDA_SDI0/I2S0_RXD
RC1600 1 @ 2 1K_0402_5% AY21 AB11 Board_ID5 0 SingleMIC RC123
RC44 1 2 33_0402_5% HDA_RST# AW22 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB13
1 2 1K_0402_5% HDA_SDOUT 43 HDA_RST_AUDIO# J5 HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0 AB12
RC47 @
GPP_D23/I2S_MCLK GPP_G2/SD_DATA1
1 DualMIC RC1606
AY20 W12
* AW20 I2S1_SFRM
I2S1_TXD
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
W11
HDA_SDO This signal has a weak internal pull-down. W10 +3VS
AK7 GPP_G5/SD_CD# W8
0 = Enable security measures defined in the Flash Descriptor. GPP_F1/I2S2_SFRM GPP_G6/SD_CLK
AK6 W7
1 = Disable Flash Descriptor Security(override). This strap AK9 GPP_F0/I2S2_SCLK GPP_G7/SD_WP
should only be asserted high during external pull-up in AK10 GPP_F2/I2S2_TXD BA9 @ @ 510Z@ @ KBL@
manufacturing/debug environments ONLY. GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BB9
GPP_A16/SD_1P8_SEL

2 RC1631 1

2 RC1632 1

2 RC1633 1

2 RC1639 1

2 RC1651 1
10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
BOARD_ID10 H5 AB7 SD_RCOMP
BOARD_ID9 D7 GPP_D19/DMIC_CLK0 SD_RCOMP
GPP_D20/DMIC_DATA0

1
For EMI D8 AF13
HDA_SDIN0 C8 GPP_D17/DMIC_CLK1 GPP_F23 RC49
GPP_D18/DMIC_DATA1 200_0402_1% BOARD_ID6
PCH_BEEP AW5 BOARD_ID7
43 PCH_BEEP GPP_B14/SPKR BOARD_ID8
1

2
CC7 BOARD_ID9
10P_0201_50V8F BOARD_ID10
EMC_NS@ SKYLAKE-U_BGA1356 1 OF 20
2 REV = 1 @ @ 310G@ @ NKBL@
?
@

2 RC1634 1

2 RC1635 1

2 RC1636 1

2 RC1652 1
2 RC1640 1
10K_0402_5%

10K_0402_5%
10K_0402_5%

10K_0402_5%

10K_0402_5%
+3VS
RC45 1 2 33_0402_5% HDA_SDOUT
43 HDA_SDOUT_AUDIO
RC46 1 @ 2 0_0402_5%
44 ME_FLASH 1 2 2.2K_0402_5% PCH_BEEP
RC14 @
B B

Board ID Description Stuff R


Default When
Pin Name Strap Description Configuration Value Sampled Samsung 8Gb
000 2133 MT/s RC1634 RC1635 RC1640
Internal PD
0 = Disable “ Top Swap” Hynix 8Gb
SPKR / Top Swap 0 Rising edge 010 RC1634 RC1632 RC1640
GPP_B14 Override
mode. (Default)
1 = Enable “ Top Swap”
* of PCH_PWROK
2133 MT/s

mode. Micron 8Gb


100 2133 MT/s RC1631 RC1635 RC1640
Internal PD
0 = Disable “ No Reboot” 110 Reserved RC1631 RC1632 RC1640
GSPI0_MOSINo Reboot Board_ID
/GPP_B18
mode. (Default) *
1 = Enable “ No Reboot” 0 Rising edge [6,7,9] Samsung 8Gb
mode of PCH_PWROK 001 2400 MT/s RC1634 RC1635 RC1639
Hynix 8Gb
011 2400 MT/s RC1634 RC1632 RC1639
Internal PD Micron 8Gb
0 = SPI (Default) 101 2400 MT/s RC1631 RC1635 RC1639
GSPI1_MOSIBoot BIOS Rising edge
/GPP_B22 Strap Bit
1 = LPC * 0 of PCH_PWROK
BBS 111 Reserved RC1631 RC1632 RC1639

0 310G RC1636
Board_ID8
1 510Z RC1633
A A

0 Non-KBL RC1652
Board_ID10
1 KBL RC1651

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (LPSS,ISH,AUDIO,SDIO)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 8 of 60


5 4 3 2 1
5 4 3 2 1

D D

SKL_ULT
?
UC1H

SSIC / USB3
PCIE/USB3/SATA
H8 USB30_RX_N1
USB3_1_RXN G8 USB30_RX_P1 USB30_RX_N1 41
H13 USB3_1_RXP C13 USB30_TX_N1 USB30_RX_P1 41 LEFT USB (3.0)
G13 PCIE1_RXN/USB3_5_RXN USB3_1_TXN D13 USB30_TX_P1 USB30_TX_N1 41
B17 PCIE1_RXP/USB3_5_RXP USB3_1_TXP USB30_TX_P1 41
A17 PCIE1_TXN/USB3_5_TXN J6 USB30_RX_N2
PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN H6 USB30_RX_P2 USB30_RX_N2 45
G11 USB3_2_RXP/SSIC_1_RXP B13 USB30_TX_N2 USB30_RX_P2 45 Right USB (3.0) (Optional)
F11 PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN A13 USB30_TX_P2 USB30_TX_N2 45
D16 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP USB30_TX_P2 45
C16 PCIE2_TXN/USB3_6_TXN J10
PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN H10
H16 USB3_3_RXP/SSIC_2_RXP B15
G16 PCIE3_RXN USB3_3_TXN/SSIC_2_TXN A15
D17 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
C17 PCIE3_TXN E10
PCIE3_TXP USB3_4_RXN F10
G15 USB3_4_RXP C15
F15 PCIE4_RXN USB3_4_TXN D15
B19 PCIE4_RXP USB3_4_TXP
A19 PCIE4_TXN AB9 USB20_N1
PCIE4_TXP USB2N_1 AB10 USB20_P1 USB20_N1 41
PCIE_PRX_DTX_N5 F16 USB2P_1 USB20_P1 41 LEFT USB (3.0)
37 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PCIE5_RXN USB20_N2
E16 AD6
37 PCIE_PRX_DTX_P5 PCIE5_RXP USB2N_2 USB20_N2 45
CC22 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N5 C19 AD7 USB20_P2
LAN 37 PCIE_PTX_C_DRX_N5
CC23 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_P5 D19 PCIE5_TXN USB2P_2 USB20_P2 45 RIGHT USB (2.0)
C 37 PCIE_PTX_C_DRX_P5 PCIE5_TXP AH3 USB20_N3 C
PCIE_PRX_DTX_N6 G18 USB2N_3 AJ3 USB20_P3 USB20_N3 45
40 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 F18 PCIE6_RXN USB2P_3 USB20_P3 45 RIGHT USB (2.0)
40 PCIE_PRX_DTX_P6 PCIE6_RXP
WLAN CC24 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N6 D20 AD9 USB20_N4
40 PCIE_PTX_C_DRX_N6 2 0.1u_0201_10V6K PCIE_PTX_DRX_P6 PCIE6_TXN USB2N_4 USB20_P4 USB20_N4 33
CC25 1 C20 AD10
40 PCIE_PTX_C_DRX_P6 PCIE6_TXP USB2P_4 USB20_P4 33 Camera
SATA_PRX_DTX_N0 F20 AJ1 USB20_N5
42 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 E20 PCIE7_RXN/SATA0_RXN USB2N_5 AJ2 USB20_P5 USB20_N5 30
SATA HDD 42 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 B21 PCIE7_RXP/SATA0_RXP
USB2
USB2P_5 USB20_P5 30 Card reader
42 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 A21 PCIE7_TXN/SATA0_TXN AF6 USB20_N6
42 SATA_PTX_DRX_P0 PCIE7_TXP/SATA0_TXP USB2N_6 AF7 USB20_P6 USB20_N6 33
SATA_PRX_DTX_N1 G21 USB2P_6 USB20_P6 33 Touch panel
42 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 F21 PCIE8_RXN/SATA1A_RXN AH1 USB20_N7
42 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 D21 PCIE8_RXP/SATA1A_RXP USB2N_7 AH2 USB20_P7 USB20_N7 40
SATA ODD 42 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 C21 PCIE8_TXN/SATA1A_TXN USB2P_7 USB20_P7 40 BT
42 SATA_PTX_DRX_P1 PCIE8_TXP/SATA1A_TXP AF8
E22 USB2N_8 AF9
E23 PCIE9_RXN USB2P_8
B23 PCIE9_RXP AG1
A23 PCIE9_TXN USB2N_9 AG2
PCIE9_TXP USB2P_9
F25 AH7
E25 PCIE10_RXN USB2N_10 AH8
D23 PCIE10_RXP USB2P_10
C23 PCIE10_TXN AB6 USB2_COMP RC118 2 1 113_0402_1%
PCIE10_TXP USB2_COMP USB2_ID
USBRBIAS
AG3 RC1626 1 @ 2 0_0402_5% Width 20Mil
RC119 1 2 100_0402_1% PCIE_RCOMPN F5 USB2_ID AG4 USB2_VBUSSENSE RC1627 1 2 1K_0402_5%
PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE Space 15Mil
E5
PCIE_RCOMPP A9 USB_OC0# Length 500Mil
PCIE_RCOMPN and PCIE_RCOMPP PAD @ TC20 1 XDP_PRDY# D56 GPP_E9/USB2_OC0# C9 USB_OC1#
Trace Width: 12-15mil 1 XDP_PREQ# D61 PROC_PRDY# GPP_E10/USB2_OC1# D9 USB_OC2# USB_OC1# 41
DGPU Differential between RCOMPP/RCOMPN
PAD @ TC19
PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3# USB_OC2# 45
PIRQA# BB11 B9
B GPP_A7/PIRQA# GPP_E12/USB2_OC3# B
E28 J1 GPP_E4 RC1628 1 2 0_0402_5%
E27 PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0 J2 GPP_E5 1 EC_SMI# 44
D24 PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 J3 @ PAD TC202
C24 PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
PCIE11_TXP/SATA1B_TXP 2016/05/03: Implement as Power Button
E30 H2 SATA0GP
F30 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 H3 ODD_DETECT# function for Windows RedStone support
A25 PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 G4 SATA2GP
B25 PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2
PCIE12_TXP/SATA2_TXP H1 BOARD_ID2
GPP_E8/SATALED# BOARD_ID2 8

SKYLAKE-U_BGA1356 1 OF 20 +3VS
REV = 1 ?
@

GPP_E4 RC1617 2 @ 1 10K_0402_5%


+3VALW_PCH

+3VS
RPC2 RPC17
1 8 ODD_DETECT# USB_OC0# 8 1
2 7 SATA0GP USB_OC1# 7 2
3 6 SATA2GP USB_OC3# 6 3
4 5 PIRQA# USB_OC2# 5 4

10K_0804_8P4R_5% 10K_0804_8P4R_5%

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCIE,SATA,USB3,USB2)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 9 of 60
5 4 3 2 1
5 4 3 2 1

UC1I
SKL_ULT ?

CSI-2

A36 C37
B36 CSI2_DN0 CSI2_CLKN0 D37
C38 CSI2_DP0 CSI2_CLKP0 C32
D38 CSI2_DN1 CSI2_CLKN1 D32
C36 CSI2_DP1 CSI2_CLKP1 C29
D D36 CSI2_DN2 CSI2_CLKN2 D29 D
A38 CSI2_DP2 CSI2_CLKP2 B26
B38 CSI2_DN3 CSI2_CLKN3 A26
CSI2_DP3 CSI2_CLKP3
C31 E13 CSI2_COMP RC73 1 2 100_0402_1%
D31 CSI2_DN4 CSI2_COMP B7
C33 CSI2_DP4 GPP_D4/FLASHTRIG
D33 CSI2_DN5
A31 CSI2_DP5 EMMC

B31 CSI2_DN6 AP2


A33 CSI2_DP6 GPP_F13/EMMC_DATA0 AP1
B33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP3
CSI2_DP7 GPP_F15/EMMC_DATA2 AN3
A29 GPP_F16/EMMC_DATA3 AN1
B29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN2
check the Pull up resistor CSI2_DP8 GPP_F18/EMMC_DATA5
C28 AM4
D28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM1
+3VS A27 CSI2_DP9 GPP_F20/EMMC_DATA7
B27 CSI2_DN10 AM2
C27 CSI2_DP10 GPP_F21/EMMC_RCLK AM3
RPC4 D27 CSI2_DN11 GPP_F22/EMMC_CLK AP4
1 8 GPU_CLKREQ# CSI2_DP11 GPP_F12/EMMC_CMD
2 7 LAN_CLKREQ# AT1 EMMC_RCOMP RC50 1 2 200_0402_1%
3 6 EMMC_RCOMP
4 5 WLAN_CLKREQ# SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
10K_0804_8P4R_5% @

UC1J SKL_ULT ?

C CLOCK SIGNALS C

D42
C42 CLKOUT_PCIE_N0
PCIE CLK0 DGPU GPU_CLKREQ# CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
A42 CLKOUT_PCIE_N1 F43 CLK_PCIE_XDP# 1 TC85 @
AT7 CLKOUT_PCIE_P1 CLKOUT_ITPXDP_N E43 CLK_PCIE_XDP 1 TC87 @ SUSCLK RC95 1 @ 2 1K_0402_5%
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
D41 BA17 SUSCLK
C41 CLKOUT_PCIE_N2 GPD8/SUSCLK SUSCLK 40 DIFFCLK_BIASREF RC1555 1 2 60.4_0402_1%
AT8 CLKOUT_PCIE_P2 E37 XTAL24_IN Cannonlake@
GPP_B7/SRCCLKREQ2# XTAL24_IN E35 XTAL24_OUT +VCCCLK5
D40 XTAL24_OUT
C40 CLKOUT_PCIE_N3 E42 DIFFCLK_BIASREF RC72 1 2 2.7K_0402_1%
AT10 CLKOUT_PCIE_P3 XCLK_BIASREF
GPP_B8/SRCCLKREQ3# AM18 RTC_X1
CLK_PCIE_LAN# B40 RTCX1 AM20 RTC_X2
37 CLK_PCIE_LAN# CLK_PCIE_LAN A40 CLKOUT_PCIE_N4 RTCX2
PCIE CLK4 LAN 37 CLK_PCIE_LAN LAN_CLKREQ# CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
37 LAN_CLKREQ# GPP_B9/SRCCLKREQ4# SRTCRST# AM16 RTC_RST#
CLK_PCIE_WLAN# E40 RTCRST#
40 CLK_PCIE_WLAN# CLK_PCIE_WLAN E38 CLKOUT_PCIE_N5
PCIE CLK5 WLAN 40 CLK_PCIE_WLAN WLAN_CLKREQ# CLKOUT_PCIE_P5
AU7
40 WLAN_CLKREQ# GPP_B10/SRCCLKREQ5#
1
CC3
VCCRTC 1U_0402_6.3V6K
SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ? 2
@ RC33 1 2 20K_0402_1% SRTC_RST#
B RC34 1 2 20K_0402_1% RTC_RST# RC1624 1 @ 2 0_0402_5% B
EC_RTC_RST# 44
1

1
CC6 JCMOS1
1U_0402_6.3V6K SHORT PADS
@

2
2

RC71 2 1 1M_0402_5% RTC_X1

YC2
RC32 2 1 10M_0402_5% RTC_X2
2 3 XTAL24_OUT
GND1 OSC2 YC1
XTAL24_IN 1 4 1 2
OSC1 GND2
2 32.768KHZ_9PF_X1A0001410002 2
1 24MHZ_6PF_7V24000032 1
CC12 CC11 CC4 CC5
3.3P_0402_50V8-C 2.7P_0402_50V9-B 7P_0402_50V8J 7P_0402_50V8J
1 1
2 2
when single end external clock generator used,
this pin should be grounded

need to use 38.4MHz (30ohm) for Cannonlake-u


A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CSI2,EMMC,CLOCK)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 10 of 60
5 4 3 2 1
5 4 3 2 1

SKL_ULT
?
UC1K
SYSTEM POWER MANAGEMENT
AT11
GPP_B12/SLP_S0# AP15 PM_SLP_S3#_R RC96 1 @ 2 0_0402_5%
PLT_RST#_R GPD4/SLP_S3# PM_SLP_S4#_R PM_SLP_S3# 13,44
RC84 1 @ 2 0_0402_5% AN10 BA16 RC97 1 @ 2 0_0402_5%
32,37,40,44 PLT_RST# SYS_RESET# B5 GPP_B13/PLTRST# GPD5/SLP_S4# AY16 PM_SLP_S4# 44
D RC85 1 @ 2 0_0402_5% PCH_RSMRST#_R AY17 SYS_RESET# GPD10/SLP_S5# D
44 EC_RSMRST# RSMRST# AN15 PM_SLP_SUS#_R 1 2 0_0402_5%
PAD @ TC21 RC89 @
1 CPU_PROCPWRGD A68 SLP_SUS# AW15 PM_SLP_SUS# 44
VCCST_PWRGD_R RC93 1 2 60.4_0402_1% VCCST_PWRGD B65 PROCPWRGD SLP_LAN# BB17 Reserve for DS3
VCCST_PWRGD GPD9/SLP_WLAN# AN16
RC139 1 @ 2 0_0402_5% SYS_PWROK_R B6 GPD6/SLP_A#
44 SYS_PWROK 1 2 0_0402_5% PCH_PWROK_R BA20 SYS_PWROK BA15 PBTN_OUT#_R 1 2 0_0402_5% PBTN_OUT# 44
RC126 @ RC87 @
44 PCH_PWROK PCH_DPWROK_R BB20 PCH_PWROK GPD3/PWRBTN# AY15 AC_PRESENT_R
DSW_PWROK GPD1/ACPRESENT AU13 BATLOW#
RC86 1 @ 2 0_0402_5% SUSWARN#_R AR13 GPD0/BATLOW#
44 SUSWARN# 1 2 0_0402_5% SUSACK#_R AP11 GPP_A13/SUSWARN#/SUSPWRDNACK
RC79 @ VCCRTC
44 SUSACK# Reserve for DS3 GPP_A15/SUSACK# AU11 PME# @1 TC89
RC91 1 @ 2 0_0402_5% WAKE# BB15 GPP_A11/PME# AP16 INTVRMEN RC41 2 1 330K_0402_5%
37,40,44 PCIE_WAKE# PCH_LAN_WAKE# AM15 WAKE# INTRUDER#
AW17 GPD2/LAN_WAKE# AM10
AT15 GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# AM11
GPD7/RSVD GPP_B2/VRALERT#

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@
+3VALW

RC74 1 2 10K_0402_5% AC_PRESENT_R


RC88 1 @ 2 0_0402_5% AC_PRESENT_R
1 2 8.2K_0402_5% BATLOW# 44 AC_PRESENT
RC75

RC76 2 1 1K_0402_5% WAKE# Follow CRB change to 1kohm

PCH_LAN_WAKE#

1
RC90 1 2 10K_0402_5% D
C 2 QC8 C
44 ACIN# G 2N7002KW_SOT323-3
@
+3VALW_PCH S

3
RC78 1 @ 2 10K_0402_5% SUSWARN#_R
+VCCST_CPU +VCCSTG

+3VS

2
+3VALW RC137 RC1554
RC80 1 2 10K_0402_5% SYS_RESET# 1K_0402_5% 1K_0402_5%
@

1
RC136
10K_0402_5% VCCST_PWRGD_R
@
PCH_RSMRST#_R

3
1000P_0201_50V7-K 1 2 CC1254 D

1
EMC_NS@ 5 QC6B 2
Stuff to fix Reset&PWRGD test fail issue G 2N7002KDWH_SOT363-6 CC140
0.01U_0201_10V6K 1 2 CC104 PCH_PWROK @ 1000P_0201_50V7-K

6
D S EMC_NS@

4
RC138 1 @ 2 0_0402_5% 2 QC6A 1
PCH_DPWROK_R 44 EC_VCCST_PWRGD
1000P_0201_50V7-K 1 2 CC103 G 2N7002KDWH_SOT363-6
EMC_NS@ 1 @
CC46 S

1
47P_0201_25V8-J 1 2 CC101 SYS_PWROK 0.01U_0201_25V6-K
EMC_NS@
2
B 0.01U_0201_10V6K 1 2 CC1278 EC_RSMRST# B

Add to fix Reset&PWRGD test fail issue

RPC21 RC1599 1 @ 2 0_0402_5%


1 8 PCH_RSMRST#_R
2 7 PCH_PWROK
3 6 SYS_PWROK
4 5 PM_SLP_S3# DC4 1 2 @

10K_0804_8P4R_5% RB751V-40_SOD323-2

RC182 1 @ 2 0_0402_5% EC_RSMRST#


100K_0402_5% 2 1 RC92 PLT_RST#_R

100K_0402_1% 2 @ 1 RC94 PCH_DPWROK_R PCH_DPWROK_R RC81 1 @ 2 0_0402_5%


DPWROK_EC 44
Reserve for DS3

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (SYSTEM PWR MANAGEMENT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 11 of 60
5 4 3 2 1
5 4 3 2 1

+CPU_CORE ? +CPU_CORE +CPU_CORE +VCC_GT +VCC_GT


SKL_ULT SKL_ULT ?
UC1L +VCC_GT UC1M
CPU POWER 1 OF 4 VCORE_VCC_SEN VCCGT_VCC_SEN
RC77 1 2 100_0402_1% RC83 1 2 100_0402_1% CPU POWER 2 OF 4
A30 G32 N70
A34 VCC_A30 VCC_G32 G33 A48 VCCGT_N70 N71
A39 VCC_A34 VCC_G33 G35 VCORE_VSS_SEN RC82 1 2 100_0402_1% VCCGT_VSS_SEN RC98 1 2 100_0402_1% A53 VCCGT_A48 VCCGT_N71 R63
A44 VCC_A39 VCC_G35 G37 A58 VCCGT_A53 VCCGT_R63 R64
AK33 VCC_A44 VCC_G37 G38 A62 VCCGT_A58 VCCGT_R64 R65
AK35 VCC_AK33 VCC_G38 G40 A66 VCCGT_A62 VCCGT_R65 R66
AK37 VCC_AK35 VCC_G40 G42 AA63 VCCGT_A66 VCCGT_R66 R67
AK38 VCC_AK37 VCC_G42 J30 AA64 VCCGT_AA63 VCCGT_R67 R68
AK40 VCC_AK38 VCC_J30 J33 AA66 VCCGT_AA64 VCCGT_R68 R69
AL33 VCC_AK40 VCC_J33 J37 AA67 VCCGT_AA66 VCCGT_R69 R70
AL37 VCC_AL33 VCC_J37 J40 AA69 VCCGT_AA67 VCCGT_R70 R71
AL40 VCC_AL37 VCC_J40 K33 AA70 VCCGT_AA69 VCCGT_R71 T62
D VCC_AL40 VCC_K33 VCCGT_AA70 VCCGT_T62 D
AM32 K35 SVID +VCCST_CPU AA71 U65
AM33 VCC_AM32 VCC_K35 K37 AC64 VCCGT_AA71 VCCGT_U65 U68
AM35 VCC_AM33 VCC_K37 K38 AC65 VCCGT_AC64 VCCGT_U68 U71
AM37 VCC_AM35 VCC_K38 K40 AC66 VCCGT_AC65 VCCGT_U71 W63
AM38 VCC_AM37 VCC_K40 K42 AC67 VCCGT_AC66 VCCGT_W63 W64
G30 VCC_AM38 VCC_K42 K43 AC68 VCCGT_AC67 VCCGT_W64 W65
VCC_G30 VCC_K43 AC69 VCCGT_AC68 VCCGT_W65 W66
VCORE_VCC_SEN 1 VCCGT_AC69 VCCGT_W66
@ TC90 1 K32 E32 CC42 AC70 W67
RSVD_K32 VCC_SENSE VCORE_VSS_SEN VCORE_VCC_SEN 59 0.1u_0201_10V6K VCCGT_AC70 VCCGT_W67
E33 AC71 W68
VSS_SENSE VCORE_VSS_SEN 59 VCCGT_AC71 VCCGT_W68

1
1
AK32 @ J43 W69

56_0402_5%

100_0402_1%
100_0402_1%
RSVD_AK32 B63 CPU_SVID_ALERT#_R 2 J45 VCCGT_J43 VCCGT_W69 W70

RC131

RC132
RC1544
AB62 VIDALERT# A63 CPU_SVID_CLK_R J46 VCCGT_J45 VCCGT_W70 W71
P62 VCCOPC_AB62 VIDSCK D64 CPU_SVID_DAT_R J48 VCCGT_J46 VCCGT_W71 Y62
3.2A V62 VCCOPC_P62 VIDSOUT J50 VCCGT_J48 VCCGT_Y62 +VCC_GT
+VCCOPC_1.0V VCCOPC_V62 VCCGT_J50

2
2
G20 +VCCSTG J52
+1.8VALW +V1.8S_EDRAM H63 VCCSTG_G20 @ J53 VCCGT_J52 AK42
VCC_OPC_1P8_H63 J55 VCCGT_J53 VCCGTX_AK42 AK43
RC1641 1 U23E@ 2 0.05A G61 J56 VCCGT_J55 VCCGTX_AK43 AK45
VCC_OPC_1P8_G61 1 2 220_0402_1% CPU_SVID_ALERT#_R J58 VCCGT_J56 VCCGTX_AK45 AK46
0_0402_5%
57 VCCOPC_SENSE
VCCOPC_SENSE AC63
59 VR_SVID_ALRT# RC133
J60 VCCGT_J58 VCCGTX_AK46 AK48 For UMA 2+3e
VSSOPC_SENSE AE63 VCCOPC_SENSE K48 VCCGT_J60 VCCGTX_AK48 AK50
57 VSSOPC_SENSE VSSOPC_SENSE CPU_SVID_CLK_R VCCGT_K48 VCCGTX_AK50
RC134 1 @ 2 0_0402_5% K50 AK52
59 VR_SVID_CLK VCCGT_K50 VCCGTX_AK52
AE62 K52 AK53
AG62 VCCEOPIO_AE62 K53 VCCGT_K52 VCCGTX_AK53 AK55
+VCCEOPIO VCCEOPIO_AG62 CPU_SVID_DAT_R VCCGT_K53 VCCGTX_AK55
RC1545 1 @ 2 0_0402_5% K55 AK56
VCCEOPIO_SENSE 59 VR_SVID_DAT VCCGT_K55 VCCGTX_AK56
AL63 K56 AK58
VSSEOPIO_SENSE VCCEOPIO_SENSE VCCGT_K56 VCCGTX_AK58
AJ62
VSSEOPIO_SENSE
1, Alert# Route Between CLK and Data K58
VCCGT_K58 VCCGTX_AK60
AK60
For UMA 2+3e K60
L62 VCCGT_K60 VCCGTX_AK70
AK70
AL43
SKYLAKE-U_BGA1356 1 OF 20 L63 VCCGT_L62 VCCGTX_AL43 AL46
REV = 1 ? L64 VCCGT_L63 VCCGTX_AL46 AL50
@ L65 VCCGT_L64 VCCGTX_AL50 AL53
L66 VCCGT_L65 VCCGTX_AL53 AL56
L67 VCCGT_L66 VCCGTX_AL56 AL60
L68 VCCGT_L67 VCCGTX_AL60 AM48
+CPU_CORE L69 VCCGT_L68 VCCGTX_AM48 AM50
VCCGT_L69 VCCGTX_AM50
C +VCC_GT Backside Cap 8x10uF 0402, SIT update L70
VCCGT_L70 VCCGTX_AM52
AM52 C
13x10uF 0402, SIT update to 0603 package L71
VCCGT_L71 VCCGTX_AM53
AM53
M62 AM56
N63 VCCGT_M62 VCCGTX_AM56 AM58
N64 VCCGT_N63 VCCGTX_AM58 AU58
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
N66 VCCGT_N64 VCCGTX_AU58 AU63
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCGT_N66 VCCGTX_AU63
N67 BB57
CC1086

CC1085

CC1080

CC1236

CC1237

CC1092

CC1091

CC1089

CC1122

CC1123

CC1124

CC1125

CC1127

CC1129
CC1093

CC1238

CC1126

CC1128
N69 VCCGT_N67 VCCGTX_BB57 BB66
VCCGT_N69 VCCGTX_BB66
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VCCGT_VCC_SEN J70 AK62 VCCGTX_SENSE 1 TC133 @
59 VCCGT_VCC_SEN VCCGT_VSS_SEN VCCGT_SENSE VCCGTX_SENSE VSSGTX_SENSE
J69 AL61 1 TC134 @
59 VCCGT_VSS_SEN VSSGT_SENSE VSSGTX_SENSE
@ CD@ @ @ @ @ CD@ CD@

SKYLAKE-U_BGA1356 1 OF 20
REV = 1 ?
@

+CPU_CORE +VCC_GT
15x1uF 0201, SIT update to 0402 package Backside Cap 12x1uF 0201, SIT update
1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1095

CC1096

CC1097

CC1100

CC1101

CC1102

CC1104

CC1111
CC1105

CC1108

CC1109

CC1114

CC1118

CC1119

CC1240

CC1241
CC1098

CC1116
CC1099

CC1115
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

@ @

B B

For UMA 2+3e

+VCCOPC_1.0V +VCCEOPIO +VCCOPC_1.0V +VCC_GT Backside Cap 8x10uF 0402

RC1642 1 U23E@ 2 0_0805_5%


VCCOPC_SENSE RC1643 1 U23E@ 2 100_0402_1%

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
10U_0402_6.3V6-M
10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M
1 1 1 1 1 1 1 1

CC1261

CC1263

CC1264

CC1266
CC1262
CC1260

CC1265

CC1267
VSSOPC_SENSE RC1644 1 U23E@ 2 100_0402_1%
2 2 2 2 2 2 2 2
+VCCOPC_1.0V +VCCEOPIO +V1.8S_EDRAM

U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@


1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K
10U_0402_6.3V6-M

10U_0402_6.3V6-M

10U_0402_6.3V6-M

1 1 1 1 1 1 1 1 1 1
CC1270

CC1271
CC1268

CC1273

CC1274

CC1275

CC1277
CC1269

CC1272

CC1276

+VCCEOPIO

2 2 2 2 2 2 2 2 2 2
@
VCCEOPIO_SENSE RC1645 1 U23E@ 2 100_0402_1%
U23E@ U23E@ U23E@ U23E@ U23E@ U23E@ U23E@
U23E@ U23E@
VSSEOPIO_SENSE RC1646 1 U23E@ 2 100_0402_1%

A A

VCCOPC_SENSE RC1647 1 @ 2 0_0402_5% VCCEOPIO_SENSE

VSSOPC_SENSE Security Classification LC Future Center Secret Data Title


RC1648 1 @ 2 0_0402_5% VSSEOPIO_SENSE
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR1)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 12 of 60


5 4 3 2 1
5 4 3 2 1

+VCCIO
3.1A 2x10uF, 4x1uF

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VCCIO 1 1 1 1 1 1 1 1 1 1
+1.2V

CC1152

CC1153

CC1158

CC1159

CC1160

CC1161

CC1218

CC1230

CC1231

CC1232
?
UC1N SKL_ULT

CPU POWER 3 OF 4 2 2 2 2 2 2 2 2 2 2
AU23 AK28
AU28 VDDQ_AU23 VCCIO_AK28 AK30
AU35 VDDQ_AU28 VCCIO_AK30 AL30 @ @ @ @ @
AU42 VDDQ_AU35 VCCIO_AL30 AL42
VDDQ_AU42 VCCIO_AL42
+1.2V 2A , 3x22uF, 6x10uF, 4x1uF, SIT update BB23
VDDQ_BB23 VCCIO_AM28
AM28
BB32 AM30 +VCCSA
BB41 VDDQ_BB32 VCCIO_AM30 AM42
BB47 VDDQ_BB41 VCCIO_AM42
D VDDQ_BB47 D
BB51 AK23 +VCCSA
10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

VDDQ_BB51 VCCSA_AK23 AK25


1 1 1 1 1 1 1 1 1 1 1 1 1 1 VCCSA_AK25 G23 4.5A 10x10uF, 7x1uF, SIT update
CC1256

CC1257

CC1258

CC1168

CC1169

CC1171

CC1222

CC1223

CC1243

CC1244

CC1224

CC1225

CC1226

CC1227
AM40 VCCSA_G23 G25
+VDDQ_CPU_CLK VDDQC VCCSA_G25 G27
2 2 2 2 2 2 2 2 2 2 2 2 2 2 A18 VCCSA_G27 G28
+VCCST_CPU

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VCCST VCCSA_G28 J22
VCCSA_J22 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@ CD@ @ @ CD@ @ CD@ @ A22 J23

CC1133

CC1134

CC1135

CC1136

CC1137

CC1251

CC1252

CC1253

CC1139

CC1140

CC1142

CC1145

CC1141

CC1143

CC1144
+VCCSTG VCCSTG_A22 VCCSA_J23 J27

CC1132
AL23 VCCSA_J27 K23
+VCCSFR_OC VCCPLL_OC VCCSA_K23 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K25
K20 VCCSA_K25 K27
K21 VCCPLL_K20 VCCSA_K27 K28
+VCCPLL_CPU VCCPLL_K21 VCCSA_K28 K30 @ @ @ @ CD@ CD@ CD@
+VCCSTG +VCCST_CPU VCCSA_K30
+VDDQ_CPU_CLK AM23 VCCIO_SENSE 1 TC136 @
VCCIO_SENSE VSSIO_SENSE
120mA VSSIO_SENSE
AM22 1 TC137 @

RC1497 1 @ 2 0_0402_5% RC103 1 @ 2 0_0402_5% H21 VCCSA_VSS_SEN


+1.2V +VCCIO

1U_0402_6.3V6K
VSSSA_SENSE H20 VCCSA_VCC_SEN VCCSA_VSS_SEN 59
1
1U_0201_6.3V6-M

10U_0402_6.3V6M

RC1604 1 @ 2 0_0402_5% VCCSA_SENSE VCCSA_VCC_SEN 59

CC86
1 1 +VCCST_CPU

1U_0402_6.3V6K
CC1229

CC1228

1
SKYLAKE-U_BGA1356 1 OF 20

CC87
2 REV = 1 ?
2 2 Reserved for VCCST/VCCSTG/VCCPLL @
@ power optimized 2 +VCCSA

+VCCSFR_OC
VCCSA_VCC_SEN RC101 1 2 100_0402_1%
+VCCPLL_CPU
RC104 1 @ 2 0_0402_5%
VCCSA_VSS_SEN RC102 1 2 100_0402_1%
1U_0201_6.3V6-M

1 120mA
RC105 1 @ 2 0_0402_5%
CC85

C +VCCST_CPU C

0.1u_0201_10V6K

1U_0402_6.3V6K
2 1 1

CC84
CC1249
2 2

+1.0VALW +VCCST_CPU

RC1605 1 @ 2 0_0402_5%

Reserved for VCCST/VCCSTG/VCCPLL power optimized

+1.0VALW +VCCST_CPU
QC19
AO3402_SOT-23-3
B B

+1.0VALW AON7408L_DFN8-5 +VCCIO 1 3


D S
QC11

10U_0603_6.3V6M

10U_0603_6.3V6M
G

1
1 1
1 RC135

CC79

CC80
0.1u_0201_10V6K

0.1u_0201_10V6K
S1

2
5 2 1 1 470_0603_5%
D S2 3 @ @ @
10U_0603_6.3V6M
22U_0603_6.3V6-M

S3 2 2
1 1
0.1u_0201_10V6K

0.1u_0201_10V6K

22U_0603_6.3V6-M
10U_0603_6.3V6M

2
G

@
CC72
CC71

CC1281

CC1282
1 1 1 1 2 2

1
+5VALW
CC1250

@ @
C1102
4

RC124
2 2 470_0603_5%
CC1279

CC1280

2 2 2 2

1
@ RC1650 1 @ 2 47K_0402_5% D
@ @ V20B+ VCCST_EN# 2 QC14

2
G 2N7002KW_SOT323-3
+5VALW @
RC142 1 2 S

3
+3VALW 100K_0402_5%

0.01U_0201_25V6-K
1
RC1649 1 @ 2 47K_0402_5% D
VCCIO_EN#

2
V20B+ 2 QC13 1

6
G 2N7002KW_SOT323-3 D RC1584

CC81
+3VALW @ RC141 1 2 VCCST_EN# 2 QC16A 120K_0402_5%
RC1621 2 1 100K_0402_5% S 47K_0402_5% G 2N7002KDWH_SOT363-6
3

1
S
0.01U_0201_25V6-K

1
1

1
6

D RC125
CC77

VCCIO_EN#

3
RC128 1 2 2 QC12A 820K_0402_5% D
47K_0402_5% G EC_VCCST_EN 5 QC16B
2N7002KDWH_SOT363-6 44 EC_VCCST_EN
2
2

G 2N7002KDWH_SOT363-6
2

RC1575 S
1

47K_0402_5% S

4
@ +VCCST_CPU switch
1

A A
3

D
RC1577 1 @ 2 0_0402_5% VCCIO_EN 5 QC12B
44 EC_VCCIO_EN G 2N7002KDWH_SOT363-6
DC1 1 2 @
11,44 PM_SLP_S3# S
4

RB751V-40_SOD323-2

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CPU PWR2)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 13 of 60


5 4 3 2 1
5 4 3 2 1

+3VALW_PCH +VCCPGPPG

RC1503 1 @ 2 0_0603_5%
+1.0VALW +VCCAMPHY
RC1622 1 @ 2 0_0402_5%
+1.0VALW RC1504 1 2 BLM18EG221TN1D_2P +VCCAPLL_1P0

D +VCCHDA D

+3VALW_PCH RC1586 1 2 BLM18EG221TN1D_2P

RC1620 1 @ 2 0_0402_5% VCCMPHYON_1P0_L1


+1.0VALW

1U_0402_6.3V6K
1

CC144
2

+3VALW_PCH

0.696A
+1.0VALW
Near AB19

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1

CC141
1 1 1 1 1
22mA 2.574A +VCCPGPPG

CC156

CC164

CC172

CC173

CC174
+1.0VALW +1.0VALW ?

22U_0603_6.3V6-M

1U_0402_6.3V6K
1 1 2 SKL_ULT
UC1O

CC158
@ 2 2 2 2 2

CC153
CPU POWER 4 OF 4
@ @ @ @

1U_0402_6.3V6K
+VCCDSW_1P0 2 2 AB19

1U_0402_6.3V6K
VCCPRIM_1P0_AB19 1
@ AB20 AK15 20mA Near Y15

CC175
1 VCCPRIM_1P0_AB20 VCCPGPPA +3VALW_PCH
P18 AG15 4mA

CC145

1U_0402_6.3V6K
VCCPRIM_1P0_P18 VCCPGPPB Y16
+1.0VALW
1.5A Near AF18 VCCPGPPC
6mA 1
AF18 Y15 8mA 2

CC176
2 AF19 VCCPRIM_CORE_AF18 VCCPGPPD T16 6mA @
VCCPRIM_CORE_AF19 VCCPGPPE +1.8VALW
V20 AF16 161mA
47U_0805_4V6-M

1U_0201_6.3V6-M

C C

1U_0402_6.3V6K
VCCPRIM_CORE_V20 VCCPGPPF +1.8VALW 2
1 1 PCH Internal VRM V21 AD15 61mA 1
VCCPRIM_CORE_V21 VCCPGPPG @

CC142
CC148

CC147

+3VALW_PCH
Near N15 AL1 V19

0.1u_0201_10V6K

1U_0402_6.3V6K
DCPDSW_1P0 VCCPRIM_3P3_V19
2 2 2 1 1
K17 T1

CC149

CC143
VCCMPHYON_1P0_L1 VCCMPHYAON_1P0_K17 VCCPRIM_1P0_T1 +1.0VALW
+VCCAMPHY
88mA L1
@ VCCMPHYAON_1P0_L1 AA1 6mA
22U_0603_6.3V6-M

1U_0402_6.3V6K

N15 VCCATS_1P8 2 2
1 1 VCCMPHYGT_1P0_N15
N16 AK17 1mA
C1096

CC151

N17 VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3


P15 VCCMPHYGT_1P0_N17 AK19 1mA
2 2 VCCMPHYGT_1P0_P15 VCCRTC_AK19 VCCRTC
Near K15 P16 BB14

0.1u_0201_10V6K

1U_0402_6.3V6K
@ VCCMPHYGT_1P0_P16 VCCRTC_BB14
1 1
K15 BB10 VCCRTCEXT

CC146

CC1242
L15 VCCAMPHYPLL_1P0_K15 DCPRTC
VCCAMPHYPLL_1P0_L15 A14 35mA

0.1u_0201_10V6K
VCCCLK1 +1.0VALW 2 2
22mA V15 1
+VCCAPLL_1P0 VCCAPLL_1P0 K19 29mA RC1587 1 @ 2 0_0603_5%

CC55
0.1u_0201_10V6K

1U_0402_6.3V6K

VCCCLK2 +1.0VALW
AB17

1U_0402_6.3V6K
1 1 +1.0VALW VCCPRIM_1P0_AB17
Y18 L21 24mA
C1097

CC154

22U_0603_6.3V6-M
VCCPRIM_1P0_Y18 VCCCLK3 +1.0VALW 1 1 2

CC56

C1098
+VCCHDA
0.118A AD17 N20 33mA
0.1u_0201_10V6K

2 2 +3VALW VCCDSW_3P3_AD17 VCCCLK4 +VCCCLK4


1 AD18
AJ17 VCCDSW_3P3_AD18 L19 4mA 2 2
CC165

VCCDSW_3P3_AJ17 VCCCLK5 +VCCCLK5


@
68mA AJ19 A10 10mA
+1.0VALW
2 VCCHDA VCCCLK6

1U_0402_6.3V6K
+3VALW_PCH
11mA AJ16 AN11 1
VCCSPI GPP_B0/CORE_VID0 AN13

CC57
0.642A AF20 GPP_B1/CORE_VID1
+1.0VALW VCCSRAM_1P0_AF20
AF21
1U_0402_6.3V6K

T19 VCCSRAM_1P0_AF21 2
1 Near AF20 VCCSRAM_1P0_T19
T20
CC159

VCCSRAM_1P0_T20
75mA AJ21
2 +3VALW_PCH VCCPRIM_3P3_AJ21
1U_0402_6.3V6K

CD@ 1 AK20
+1.0VALW VCCPRIM_1P0_AK20
CC171

33mA N18 RC1588 1 @ 2 0_0603_5%


B +1.0VALW VCCAPLLEBB +VCCCLK4 +1.0VALW B

22U_0603_6.3V6-M
2
1U_0402_6.3V6K

1
SKYLAKE-U_BGA1356 1 OF 20

C1099
1
CD@ REV = 1
CC169

?
@
2
2 @

RC1589 1 @ 2 0_0603_5%
+VCCCLK5 +1.0VALW
Near A18

22U_0603_6.3V6-M
1

C1100
2
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (PCH PWR)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 14 of 60


5 4 3 2 1
5 4 3 2 1

SKL_ULT
UC1Q ?
SKL_ULT
UC1P ?
SKL_ULT ?
GND 2 OF 3 UC1R
GND 1 OF 3
AT63 BA49 GND 3 OF 3
A5 AL65 AT68 VSS_AT63 VSS_BA49 BA53 F8 L18
A67 VSS_A5 VSS_AL65 AL66 AT71 VSS_AT68 VSS_BA53 BA57 G10 VSS_F8 VSS_L18 L2
A70 VSS_A67 VSS_AL66 AM13 AU10 VSS_AT71 VSS_BA57 BA6 G22 VSS_G10 VSS_L2 L20
D AA2 VSS_A70 VSS_AM13 AM21 AU15 VSS_AU10 VSS_BA6 BA62 G43 VSS_G22 VSS_L20 L4 D
AA4 VSS_AA2 VSS_AM21 AM25 AU20 VSS_AU15 VSS_BA62 BA66 G45 VSS_G43 VSS_L4 L8
AA65 VSS_AA4 VSS_AM25 AM27 AU32 VSS_AU20 VSS_BA66 BA71 G48 VSS_G45 VSS_L8 N10
AA68 VSS_AA65 VSS_AM27 AM43 AU38 VSS_AU32 VSS_BA71 BB18 G5 VSS_G48 VSS_N10 N13
AB15 VSS_AA68 VSS_AM43 AM45 AV1 VSS_AU38 VSS_BB18 BB26 G52 VSS_G5 VSS_N13 N19
AB16 VSS_AB15 VSS_AM45 AM46 AV68 VSS_AV1 VSS_BB26 BB30 G55 VSS_G52 VSS_N19 N21
AB18 VSS_AB16 VSS_AM46 AM55 AV69 VSS_AV68 VSS_BB30 BB34 G58 VSS_G55 VSS_N21 N6
AB21 VSS_AB18 VSS_AM55 AM60 AV70 VSS_AV69 VSS_BB34 BB38 G6 VSS_G58 VSS_N6 N65
AB8 VSS_AB21 VSS_AM60 AM61 AV71 VSS_AV70 VSS_BB38 BB43 G60 VSS_G6 VSS_N65 N68
AD13 VSS_AB8 VSS_AM61 AM68 AW10 VSS_AV71 VSS_BB43 BB55 G63 VSS_G60 VSS_N68 P17
AD16 VSS_AD13 VSS_AM68 AM71 AW12 VSS_AW10 VSS_BB55 BB6 G66 VSS_G63 VSS_P17 P19
AD19 VSS_AD16 VSS_AM71 AM8 AW14 VSS_AW12 VSS_BB6 BB60 H15 VSS_G66 VSS_P19 P20
AD20 VSS_AD19 VSS_AM8 AN20 AW16 VSS_AW14 VSS_BB60 BB64 H18 VSS_H15 VSS_P20 P21
AD21 VSS_AD20 VSS_AN20 AN23 AW18 VSS_AW16 VSS_BB64 BB67 H71 VSS_H18 VSS_P21 R13
AD62 VSS_AD21 VSS_AN23 AN28 AW21 VSS_AW18 VSS_BB67 BB70 J11 VSS_H71 VSS_R13 R6
AD8 VSS_AD62 VSS_AN28 AN30 AW23 VSS_AW21 VSS_BB70 C1 J13 VSS_J11 VSS_R6 T15
AE64 VSS_AD8 VSS_AN30 AN32 AW26 VSS_AW23 VSS_C1 C25 J25 VSS_J13 VSS_T15 T17
AE65 VSS_AE64 VSS_AN32 AN33 AW28 VSS_AW26 VSS_C25 C5 J28 VSS_J25 VSS_T17 T18
AE66 VSS_AE65 VSS_AN33 AN35 AW30 VSS_AW28 VSS_C5 D10 J32 VSS_J28 VSS_T18 T2
AE67 VSS_AE66 VSS_AN35 AN37 AW32 VSS_AW30 VSS_D10 D11 J35 VSS_J32 VSS_T2 T21
AE68 VSS_AE67 VSS_AN37 AN38 AW34 VSS_AW32 VSS_D11 D14 J38 VSS_J35 VSS_T21 T4
AE69 VSS_AE68 VSS_AN38 AN40 AW36 VSS_AW34 VSS_D14 D18 J42 VSS_J38 VSS_T4 U10
AF1 VSS_AE69 VSS_AN40 AN42 AW38 VSS_AW36 VSS_D18 D22 J8 VSS_J42 VSS_U10 U63
AF10 VSS_AF1 VSS_AN42 AN58 AW41 VSS_AW38 VSS_D22 D25 K16 VSS_J8 VSS_U63 U64
AF15 VSS_AF10 VSS_AN58 AN63 AW43 VSS_AW41 VSS_D25 D26 K18 VSS_K16 VSS_U64 U66
AF17 VSS_AF15 VSS_AN63 AP10 AW45 VSS_AW43 VSS_D26 D30 K22 VSS_K18 VSS_U66 U67
AF2 VSS_AF17 VSS_AP10 AP18 AW47 VSS_AW45 VSS_D30 D34 K61 VSS_K22 VSS_U67 U69
AF4 VSS_AF2 VSS_AP18 AP20 AW49 VSS_AW47 VSS_D34 D39 K63 VSS_K61 VSS_U69 U70
AF63 VSS_AF4 VSS_AP20 AP23 AW51 VSS_AW49 VSS_D39 D44 K64 VSS_K63 VSS_U70 V16
AG16 VSS_AF63 VSS_AP23 AP28 AW53 VSS_AW51 VSS_D44 D45 K65 VSS_K64 VSS_V16 V17
AG17 VSS_AG16 VSS_AP28 AP32 AW55 VSS_AW53 VSS_D45 D47 K66 VSS_K65 VSS_V17 V18
AG18 VSS_AG17 VSS_AP32 AP35 AW57 VSS_AW55 VSS_D47 D48 K67 VSS_K66 VSS_V18 W13
C AG19 VSS_AG18 VSS_AP35 AP38 AW6 VSS_AW57 VSS_D48 D53 K68 VSS_K67 VSS_W13 W6 C
AG20 VSS_AG19 VSS_AP38 AP42 AW60 VSS_AW6 VSS_D53 D58 K70 VSS_K68 VSS_W6 W9
AG21 VSS_AG20 VSS_AP42 AP58 AW62 VSS_AW60 VSS_D58 D6 K71 VSS_K70 VSS_W9 Y17
AG71 VSS_AG21 VSS_AP58 AP63 AW64 VSS_AW62 VSS_D6 D62 L11 VSS_K71 VSS_Y17 Y19
AH13 VSS_AG71 VSS_AP63 AP68 AW66 VSS_AW64 VSS_D62 D66 L16 VSS_L11 VSS_Y19 Y20
AH6 VSS_AH13 VSS_AP68 AP70 AW8 VSS_AW66 VSS_D66 D69 L17 VSS_L16 VSS_Y20 Y21
AH63 VSS_AH6 VSS_AP70 AR11 AY66 VSS_AW8 VSS_D69 E11 VSS_L17 VSS_Y21
AH64 VSS_AH63 VSS_AR11 AR15 B10 VSS_AY66 VSS_E11 E15
AH67 VSS_AH64 VSS_AR15 AR16 B14 VSS_B10 VSS_E15 E18
AJ15 VSS_AH67 VSS_AR16 AR20 B18 VSS_B14 VSS_E18 E21
AJ18 VSS_AJ15 VSS_AR20 AR23 B22 VSS_B18 VSS_E21 E46 1 OF 20
SKYLAKE-U_BGA1356
AJ20 VSS_AJ18 VSS_AR23 AR28 B30 VSS_B22 VSS_E46 E50 REV = 1
VSS_AJ20 VSS_AR28 VSS_B30 VSS_E50 ?
AJ4 AR35 B34 E53 @
AK11 VSS_AJ4 VSS_AR35 AR42 B39 VSS_B34 VSS_E53 E56
AK16 VSS_AK11 VSS_AR42 AR43 B44 VSS_B39 VSS_E56 E6
AK18 VSS_AK16 VSS_AR43 AR45 B48 VSS_B44 VSS_E6 E65
AK21 VSS_AK18 VSS_AR45 AR46 B53 VSS_B48 VSS_E65 E71
AK22 VSS_AK21 VSS_AR46 AR48 B58 VSS_B53 VSS_E71 F1
AK27 VSS_AK22 VSS_AR48 AR5 B62 VSS_B58 VSS_F1 F13
AK63 VSS_AK27 VSS_AR5 AR50 B66 VSS_B62 VSS_F13 F2
AK68 VSS_AK63 VSS_AR50 AR52 B71 VSS_B66 VSS_F2 F22
AK69 VSS_AK68 VSS_AR52 AR53 BA1 VSS_B71 VSS_F22 F23
AK8 VSS_AK69 VSS_AR53 AR55 BA10 VSS_BA1 VSS_F23 F27
AL2 VSS_AK8 VSS_AR55 AR58 BA14 VSS_BA10 VSS_F27 F28
AL28 VSS_AL2 VSS_AR58 AR63 BA18 VSS_BA14 VSS_F28 F32
AL32 VSS_AL28 VSS_AR63 AR8 BA2 VSS_BA18 VSS_F32 F33
AL35 VSS_AL32 VSS_AR8 AT2 BA23 VSS_BA2 VSS_F33 F35
AL38 VSS_AL35 VSS_AT2 AT20 BA28 VSS_BA23 VSS_F35 F37
AL4 VSS_AL38 VSS_AT20 AT23 BA32 VSS_BA28 VSS_F37 F38
AL45 VSS_AL4 VSS_AT23 AT28 BA36 VSS_BA32 VSS_F38 F4
AL48 VSS_AL45 VSS_AT28 AT35 F68 VSS_BA36 VSS_F4 F40
AL52 VSS_AL48 VSS_AT35 AT4 BA45 VSS_F68 VSS_F40 F42
B AL55 VSS_AL52 VSS_AT4 AT42 VSS_BA45 VSS_F42 BA41 B
AL58 VSS_AL55 VSS_AT42 AT56 VSS_BA41
AL64 VSS_AL58 VSS_AT56 AT58
VSS_AL64 VSS_AT58
1 OF 20
SKYLAKE-U_BGA1356
1 OF 20
SKYLAKE-U_BGA1356 REV = 1 ?
REV = 1 ? @
@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (VSS)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 15 of 60
5 4 3 2 1
5 4 3 2 1

?
SKL_ULT
UC1S

RESERVED SIGNALS-1

CPU_CFG0 E68 BB68 1 TC173 @ PAD


D PAD @ TC142 1 CPU_CFG1 B67 CFG[0] RSVD_TP_BB68 BB69 1 TC174 @ PAD D
PAD @ TC143 1 CPU_CFG2 D65 CFG[1] RSVD_TP_BB69
PAD @ TC144 1 XDP_CPU_CFG3 D67 CFG[2] AK13 1 TC175 @ PAD
CPU_CFG4 CFG[3] RSVD_TP_AK13
2

E70 AK12 1 TC176 @ PAD


RC1618 PAD @ TC146 1 CPU_CFG5 C68 CFG[4] RSVD_TP_AK12 +VCCST_CPU
1K_0402_5% PAD @ TC147 1 CPU_CFG6 D68 CFG[5] BB2 UC1T SKL_ULT ?
@ PAD @ TC148 1 CPU_CFG7 C67 CFG[6] RSVD_BB2 BA3
CPU_CFG8 CFG[7] RSVD_BA3

2
PAD @ TC153 1 F71 SPARE
CFG[8]
1

RC106 PAD @ TC150 1 CPU_CFG9 G69 +1.8VALW


CPU_CFG10 CFG[9]

1
1K_0402_5% PAD @ TC151 1 F70 AU5 AW69 F6
PAD @ TC152 1 CPU_CFG11 G68 CFG[10] TP5 AT5 AW68 RSVD_AW69 RSVD_F6 E3 RC1619
PAD @ TC157 1 CPU_CFG12 H70 CFG[11] TP6 AU56 RSVD_AW68 RSVD_E3 C11 150_0402_5%
CFG[12] RSVD_AU56 RSVD_C11
1

PAD @ TC154 1 CPU_CFG13 G71 AW48 B11 @


PAD @ TC155 1 CPU_CFG14 H69 CFG[13] D5 Cannonlake@ C7 RSVD_AW48 RSVD_B11 A11
CFG[14] RSVD_D5 RSVD_C7 RSVD_A11

2
PAD @ TC156 1 CPU_CFG15 G70 D4 RC1582 2 1 0_0402_5% RSVD_U12 U12 D12
CFG[15] RSVD_D4 B2 1 TC183 @ PAD RC1583 2 1 0_0402_5% RSVD_U11 U11 RSVD_U12 RSVD_D12 C12
PAD @ TC159 1 CPU_CFG16 E63 RSVD_B2 C2 1 TC185 @ PAD Cannonlake@ H11 RSVD_U11 RSVD_C12 F52 RSVD_F52
PAD @ TC158 1 CPU_CFG17 F63 CFG[16] RSVD_C2 RSVD_H11 RSVD_F52
CFG[17] B3 1 TC184 @ PAD
PAD @ TC161 1 CPU_CFG18 E66 RSVD_B3 A3 1 TC181 @ PAD
CPU_CFG19 CFG[18] RSVD_A3 1 OF 20
PAD @ TC160 1 F66 SKYLAKE-U_BGA1356
CFG[19] AW1 REV = 1 ?
C CFG_RCOMP E60 RSVD_AW1 @ C
CFG_RCOMP E1 1 TC187 @ PAD
PAD @ TC166 1 XDP_ITP_PMODE E8 RSVD_E1 E2
ITP_PMODE RSVD_E2
2

RC162 AY2 BA4


AY1 RSVD_AY2 RSVD_BA4 BB4
49.9_0402_1% RSVD_AY1 RSVD_BB4
PAD @ TC186 1 D1 A4 1 TC182 @ PAD
RSVD_D1 RSVD_A4
1

D3 C4
RSVD_D3 RSVD_C4
K46 BB5
K45 RSVD_K46 TP4
RSVD_K45 A69 1 TC188 @ PAD
AL25 RSVD_A69 B69 1 TC193 @ PAD
AL27 RSVD_AL25 RSVD_B69
RSVD_AL27 AY3 RSVD_AY3 need to check with Intel
PAD @ TC189 1 C71 RSVD_AY3
RSVD_C71

2
PAD @ TC191 1 B70 D71 1 TC190 @ PAD
RSVD_B70 RSVD_D71 C70 1 TC192 @ PAD RC107
F60 RSVD_C70
RSVD_F60 0_0402_5%
C54
A52 RSVD_C54 D54
RSVD_A52 RSVD_D54

1
B B
PAD @ TC171 1 BA70 AY4
PAD @ TC172 1 BA68 RSVD_TP_BA70 TP1 BB3
RSVD_TP_BA68 TP2
J71 AY71 VSS_AY71 need to check with Intel
J68 RSVD_J71 VSS_AY71 AR56
RSVD_J68 ZVM# ZVM# 57 For UMA 2+3e

2
PAD @ TC169 1 F65 AW71 1 TC177 @ PAD
PAD @ TC170 1 G65 VSS_F65 RSVD_TP_AW71 AW70 1 TC178 @ PAD RC108
VSS_G65 RSVD_TP_AW70
0_0402_5%
F61 AP56 1 TC168 @ PAD
E61 RSVD_F61 MSM# C64 PROC_SELECT# 1 2
RSVD_E61 PROC_SELECT# +VCCST_CPU

1
100K_0402_5% Cannonlake@ R22

1 OF 20
SKYLAKE-U_BGA1356
REV = 1 ?
@
Default
Pin Name Strap Description Configuration Value

A A
CFG[4] Display Port — 1 = eDP Disabled 1
Presence strap — 0 = eDP Enabled
* Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 MCP (CFG,RESERVED)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 16 of 60


5 4 3 2 1
5 4 3 2 1

DDRA_DQ[0..63]
DDRA_DQ[0..63] 5
DDRA_DQS#[0..7]
UD1 @ UD2 @
DDRA_DQS#[0..7] 5
DDRA_MA0 DDRA_DQ2 DDRA_MA0 DDRA_DQ18 +1.2V DDRA_DQS[0..7]
P3 G2 P3 G2
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ3 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ19 DDRA_DQS[0..7] 5
DDRA_MA2 A1 DQ1 DDRA_DQ7 DDRA_MA2 A1 DQ1 DDRA_DQ16 DDRA_MA[0..13]
R3 H3 R3 H3
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ1 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ21 DDRA_MA[0..13] 5
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ4 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ22
DDRA_MA5 A4 DQ4 DDRA_DQ0 DDRA_MA5 A4 DQ4 DDRA_DQ17 1

1
P8 H8 P8 H8 +0.6VS
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ6 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ23
CD119 RD45
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ5 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ20
0.1u_0201_10V6K 1.8K_0402_1%
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ11 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ30 2 DDRA_CLK0# 1 2
RD49 36_0402_1%
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ8 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ28 DDRA_CLK0 1 2
RD50 36_0402_1%
DDRA_MA10 A9 DQ9 DDRA_DQ14 DDRA_MA10 A9 DQ9 DDRA_DQ26

2
M3 C3 M3 C3
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ13 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ25 DDRA_CS0# 1 2
RD51 34.8_0402_1%
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ15 DDRA_MA12 A11 DQ11 DDRA_DQ31 +VREF_CA_MD DDRA_ODT0
M7 C2 RD46 1 2 RD52 1 2 34.8_0402_1%
DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ12 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ29 5 DDR_SA_VREFCA
2.7_0402_1%
A13 DQ13 D3 DDRA_DQ10 A13 DQ13 D3 DDRA_DQ27 DDRA_CKE0 1 2
1 RD53 34.8_0402_1%
DDRA_MA14_WE# DQ14 DDRA_DQ9 DDRA_MA14_WE# DQ14 DDRA_DQ24

1
D L2 D7 L2 D7 1 D
5 DDRA_MA14_WE# DDRA_MA15_CAS# WE_N/A14 DQ15 DDRA_MA15_CAS# WE_N/A14 DQ15 DDRA_MA0
M8 M8 CD111 RD47 RD54 1 2 34.8_0402_1%
5 DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA1 1 2
0.022U_0201_6.3V6-K 1.8K_0402_1% CD112 RD55 34.8_0402_1%
5 DDRA_MA16_RAS# RAS_N/A16 D1 RAS_N/A16 D1 2 DDRA_MA2 1 2
0.1u_0201_10V6K RD56 34.8_0402_1%
DDRA_CLK0# K8 VDD1 J1 DDRA_CLK0# K8 VDD1 J1 2 DDRA_MA3 1 2
5 DDRA_CLK0# RD57 34.8_0402_1%
DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2

2
1
K7 L1 K7 L1
5 DDRA_CLK0 CK_T VDD3 CK_T VDD3 DDRA_MA4
R1 R1 RD48 RD58 1 2 34.8_0402_1%
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA5 1 2
5 DDRA_CKE0 24.9_0402_1% RD59 34.8_0402_1%
CKE VDD5 G7 CKE VDD5 G7 DDRA_MA6 1 2
RD60 34.8_0402_1%
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#2 F3 VDD6 B9 DDRA_MA7 1 2
RD61 34.8_0402_1%
DDRA_DQS0 LDQS_C VDD7 DDRA_DQS2 LDQS_C VDD7

2
G3 J9 G3 J9
DDRA_DQS#1 A7 LDQS_T VDD8 L9 DDRA_DQS#3 A7 LDQS_T VDD8 L9 DDRA_MA8 1 2
RD62 34.8_0402_1%
+1.2V DDRA_DQS1 B7 UDQS_C VDD9 T9 +1.2V DDRA_DQS3 B7 UDQS_C VDD9 T9 DDRA_MA9 1 2
RD63 34.8_0402_1%
UDQS_T VDD10 UDQS_T VDD10 DDRA_MA10 1 2
RD64 34.8_0402_1%
DDRA_DM1 DDRA_DM3 DDRA_MA11
RD65 1 @ 2 0_0402_5% E2 A1 RD66 1 @ 2 0_0402_5% E2 A1 RD67 1 2 34.8_0402_1%
DDRA_DM0 E7 NF/UDM_N/UDBI_N VDDQ1 DDRA_DM2 NF/UDM_N/UDBI_N VDDQ1
RD68 1 @ 2 0_0402_5% C1 RD69 1 @ 2 0_0402_5% E7 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_MA12 1 2
RD70 34.8_0402_1%
DDRA_BS0# N2 VDDQ3 F2 DDRA_BS0# N2 VDDQ3 F2 DDRA_MA13 1 2
5 DDRA_BS0# RD71 34.8_0402_1%
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_MA14_WE# 1 2
5 DDRA_BS1# RD72 34.8_0402_1%
BA1 VDDQ5 F8 BA1 VDDQ5 F8 DDRA_MA15_CAS# 1 2
RD73 34.8_0402_1%
DDRA_ACT# L3 VDDQ6 J8 DDRA_ACT# L3 VDDQ6 J8
5 DDRA_ACT# DDRA_CS0# ACT_N VDDQ7 DDRA_CS0# ACT_N VDDQ7
L7 A9 L7 A9
5 DDRA_CS0# DDRA_ALERT# P9 CS_N VDDQ8 D9 DDRA_ALERT# P9 CS_N VDDQ8 D9 DDRA_MA16_RAS# 1 2
RD74 34.8_0402_1%
5 DDRA_ALERT# ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 +2.5V_DDR DDRA_BG0 1 2
RD75 34.8_0402_1%
DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10 DDRA_BS0# 1 2
5 DDRA_BG0 RD76 34.8_0402_1%
BG0 B1 BG0 B1 DDRA_BS1# 1 2
RD77 34.8_0402_1%
DDRA_ODT0 K3 VPP1 R9 DDRA_ODT0 K3 VPP1 R9
5 DDRA_ODT0 ODT VPP2 ODT VPP2 DDRA_ACT# 1 2
RD78 34.8_0402_1%
DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR T3 M1 +VREF_CA_MD DDRA_PAR 1 2
RD79 34.8_0402_1%

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
5 DDRA_PAR PAR VREFCA PAR VREFCA
1 1 1 1
RD94 1 2 10K_0402_5% TEN_UD1 N9 E1 RD95 1 2 10K_0402_5% TEN_UD2 N9 E1

0.1u_0201_10V6K

0.1u_0201_10V6K
.047U_0201_6.3V6K

.047U_0201_6.3V6K
TEN VSS1 K1 TEN VSS1 K1
CPU_DRAMRST# VSS2 1 1 CPU_DRAMRST# VSS2 1 1
P1 N1 P1 N1
6,18 CPU_DRAMRST# RESET_N VSS3 T1 2 2 RESET_N VSS3 T1 2 2
@ F1 VSS4 B2 @ F1 VSS4 B2

CD121

CD123

CD124

CD125
0.1u_0201_10V6K

0.1u_0201_10V6K
H1 VSSQ1 VSS5 G8 2 2 H1 VSSQ1 VSS5 G8 2 2
1 VSSQ2 VSS6 1 VSSQ2 VSS6
A2 E9 A2 E9 +1.2V

CD113

CD120

CD114

CD122
D2 VSSQ3 VSS7 K9 D2 VSSQ3 VSS7 K9
E3 VSSQ4 VSS8 M9 E3 VSSQ4 VSS8 M9
2 A8 VSSQ5 VSS9 2 A8 VSSQ5 VSS9 DDRA_ALERT# 1 2 49.9_0402_1%
RD86
CD47

CD48
D8 VSSQ6 T7 D8 VSSQ6 T7
E8 VSSQ7 NC E8 VSSQ7 NC
C9 VSSQ8 C9 VSSQ8
H9 VSSQ9 H9 VSSQ9
VSSQ10 VSSQ10
C F9 F9 C
ZQ ZQ
1

1
RD39 MT40A512M16HA083EA_FBGA96 RD40 MT40A512M16HA083EA_FBGA96
240_0402_1% 240_0402_1%
2

2
+1.2V (1uF_0402_6.3V) *16
Place 4 near each DRAM

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
UD3 @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
UD4 @
DDRA_MA0 P3 G2 DDRA_DQ43
DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ44 DDRA_MA0 P3 G2 DDRA_DQ59
DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ46 DDRA_MA1 P7 A0 DQ0 F7 DDRA_DQ60 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ40 DDRA_MA2 R3 A1 DQ1 H3 DDRA_DQ62

CD130

CD133
CD131

CD132

CD137

CD138

CD139

CD140

CD141
CD126

CD135

CD136
CD127

CD128

CD129

CD134
DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ47 DDRA_MA3 N7 A2 DQ2 H7 DDRA_DQ56
DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ45 DDRA_MA4 N3 A3 DQ3 H2 DDRA_DQ63
CD@ CD@ CD@ CD@
DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ42 DDRA_MA5 P8 A4 DQ4 H8 DDRA_DQ61
DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ41 DDRA_MA6 P2 A5 DQ5 J3 DDRA_DQ58
DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ34 DDRA_MA7 R8 A6 DQ6 J7 DDRA_DQ57
DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ37 DDRA_MA8 R2 A7 DQ7 A3 DDRA_DQ54
DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ39 DDRA_MA9 R7 A8 DQ8 B8 DDRA_DQ52
DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ32 DDRA_MA10 M3 A9 DQ9 C3 DDRA_DQ51
DDRA_MA12 M7 A11 DQ11 C2 DDRA_DQ35 DDRA_MA11 T2 A10/AP DQ10 C7 DDRA_DQ49 +1.2V +1.2V
DDRA_MA13 A12/BC_N DQ12 DDRA_DQ33 DDRA_MA12 A11 DQ11 DDRA_DQ50 (1OuF_0603_6.3V) *5
T8 C8 M7 C2 Place around the DRAMs
A13 DQ13 D3 DDRA_DQ38 DDRA_MA13 T8 A12/BC_N DQ12 C8 DDRA_DQ53
DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ36 A13 DQ13 D3 DDRA_DQ55
DDRA_MA15_CAS# M8 WE_N/A14 DQ15 DDRA_MA14_WE# L2 DQ14 D7 DDRA_DQ48
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQ15
RAS_N/A16 D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
CK_T VDD3 DDRA_CLK0 CK_C VDD2 1 1 1 1 1 1 1
B R1 K7 L1 CD109 CD110 B
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 22P_0402_50V8-J 22P_0402_50V8-J
CKE VDD5 G7 DDRA_CKE0 K2 VDD4 B3 RF@ RF@
DDRA_DQS#5 F3 VDD6 B9 CKE VDD5 G7 2 2 2 2 2 2 2
DDRA_DQS5 G3 LDQS_C VDD7 J9 DDRA_DQS#7 F3 VDD6 B9

CD142

CD143

CD144

CD145

CD146
DDRA_DQS#4 A7 LDQS_T VDD8 L9 DDRA_DQS7 G3 LDQS_C VDD7 J9
+1.2V DDRA_DQS4 B7 UDQS_C VDD9 T9 DDRA_DQS#6 A7 LDQS_T VDD8 L9 CD@
UDQS_T VDD10 +1.2V DDRA_DQS6 B7 UDQS_C VDD9 T9
DDRA_DM4 E2 A1 UDQS_T VDD10
RD87 1 @ 2 0_0402_5%
DDRA_DM5 E7 NF/UDM_N/UDBI_N VDDQ1 C1 DDRA_DM6
RD88 1 @ 2 0_0402_5% RD89 1 @ 2 0_0402_5% E2 A1
NF/LDM_N/LDBI_N VDDQ2 G1 DDRA_DM7 E7 NF/UDM_N/UDBI_N VDDQ1 C1
RD90 1 @ 2 0_0402_5%
DDRA_BS0# N2 VDDQ3 F2 NF/LDM_N/LDBI_N VDDQ2 G1
DDRA_BS1# N8 BA0 VDDQ4 J2 DDRA_BS0# N2 VDDQ3 F2
BA1 VDDQ5 F8 DDRA_BS1# N8 BA0 VDDQ4 J2
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8
DDRA_ALERT# CS_N VDDQ8 DDRA_CS0# ACT_N VDDQ7
(1OuF_0603_6.3V) *3
P9 D9 L7 A9 +2.5V_DDR +2.5V_DDR
ALERT_N VDDQ9 +2.5V_DDR DDRA_ALERT# CS_N VDDQ8 Place around the DRAMs
G9 P9 D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0 B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1 R9 BG0 B1
ODT VPP2 DDRA_ODT0 K3 VPP1 R9

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDRA_PAR T3 M1 +VREF_CA_MD ODT VPP2
1 1 1
1U_0402_6.3V6K

1U_0402_6.3V6K

PAR VREFCA DDRA_PAR +VREF_CA_MD 1 1


T3 M1 CD157 CD148

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1
RD96 1 2 10K_0402_5% TEN_UD3 N9 E1 PAR VREFCA 22P_0402_50V8-J 22P_0402_50V8-J
0.1u_0201_10V6K

1 1
.047U_0201_6.3V6K

TEN VSS1 K1 RD97 1 2 10K_0402_5% TEN_UD4 N9 E1 RF@ RF@

0.1u_0201_10V6K
1 1

.047U_0201_6.3V6K
CPU_DRAMRST# P1 VSS2 N1 TEN VSS1 K1 2 2 2 2 2
RESET_N VSS3 CPU_DRAMRST# VSS2 1 1
T1 2 2 P1 N1

CD152

CD156

CD147
@ F1 VSS4 B2 RESET_N VSS3 T1 2 2
CD150

CD151
0.1u_0201_10V6K

H1 VSSQ1 VSS5 G8 2 2 @ F1 VSS4 B2

CD154

CD155
0.1u_0201_10V6K

1 VSSQ2 VSS6 VSSQ1 VSS5 2 2


A2 E9 CD@ H1 G8
CD115

CD149

VSSQ3 VSS7 1 VSSQ2 VSS6


D2 K9 A2 E9 CD@

CD116

CD153
E3 VSSQ4 VSS8 M9 D2 VSSQ3 VSS7 K9
2 A8 VSSQ5 VSS9 E3 VSSQ4 VSS8 M9
CD107

D8 VSSQ6 T7 2 A8 VSSQ5 VSS9


CD108

E8 VSSQ7 NC D8 VSSQ6 T7
C9 VSSQ8 E8 VSSQ7 NC
H9 VSSQ9 C9 VSSQ8 +0.6VS +0.6VS
VSSQ10 VSSQ9
(1uF_0402_6.3V) *8 (1OuF_0603_6.3V) *2
H9 Place 2 near each DRAM Place around the DRAMs
F9 VSSQ10
ZQ F9
ZQ
1

RD43 MT40A512M16HA083EA_FBGA96

10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
240_0402_1% RD44 MT40A512M16HA083EA_FBGA96 1 1 1 1 1 1 1 1 1 1 1 1
240_0402_1% CD168 CD169
A A
22P_0402_50V8-J 22P_0402_50V8-J
2

RF@ RF@
2

2 2 2 2 2 2 2 2 2 2 2 2

CD159

CD160

CD161

CD162

CD163

CD164

CD165

CD167
CD158

CD166
CD@ CD@ CD@

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 Memory Down
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 17 of 60
5 4 3 2 1
5 4 3 2 1

+1.2V

DDR4 SO-DIMM DDRB_DQ[0..63]


DDRB_DQ[0..63] 6

1
DDRB_DQS#[0..7]
RD91
DDRB_DQS#[0..7] 6
+1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V +1.2V 240_0402_1%
DDRB_DQS[0..7]
JDDR1A JDDR1B @
DDRB_DQS[0..7] 6

2
1 2 DDRB_MA3 131 132 DDRB_MA2
DDRB_DQ12 3 VSS_1 VSS_2 4 DDRB_DQ9 6 DDRB_MA3 DDRB_MA1 133 A3 A2 134 DDRB_EVENT# DDRB_MA2 6
5 DQ5 DQ4 6 6 DDRB_MA1 135 A1 EVENT_n 136
DDRB_DQ13 7 VSS_3 VSS_4 8 DDRB_DQ8 DDRB_CLK0 137 VDD_9 VDD_10 138 DDRB_CLK1
9 DQ1 DQ0 10 6 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t 140 DDRB_CLK1# DDRB_CLK1 6
DDRB_DQS#1 11 VSS_5 VSS_6 12 6 DDRB_CLK0# 141 CK0_c CK1_c 142 DDRB_CLK1# 6
DDRB_DQS1 13 DQS0_C DM0_n/DBIO_n/NC 14 DDRB_PAR 143 VDD_11 VDD_12 144 DDRB_MA0
15 DQS0_t VSS_7 16 DDRB_DQ11 6 DDRB_PAR Parity A0 DDRB_MA0 6
DDRB_DQ10 17 VSS_8 DQ6 18
D 19 DQ7 VSS_9 20 DDRB_DQ15 DDRB_BS1# 145 146 DDRB_MA10 D
DDRB_DQ14 21 VSS_10 DQ2 22 6 DDRB_BS1# 147 BA1 A10/AP 148 DDRB_MA10 6
23 DQ3 VSS_11 24 DDRB_DQ5 DDRB_CS0# 149 VDD_13 VDD_14 150 DDRB_BS0#
DDRB_DQ0 25 VSS_12 DQ12 26 6 DDRB_CS0# DDRB_MA14_WE# 151 CS0_n BA0 152 DDRB_MA16_RAS# DDRB_BS0# 6
27 DQ13 VSS_13 28 DDRB_DQ4 6 DDRB_MA14_WE# 153 WE_n/A14 RAS_n/A16 154 DDRB_MA16_RAS# 6
DDRB_DQ6 29 VSS_14 DQ8 30 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
31 DQ9 VSS_15 32 DDRB_DQS#0 6 DDRB_ODT0 DDRB_CS1# 157 ODT0 CAS_n/A15 158 DDRB_MA13 DDRB_MA15_CAS# 6
33 VSS_16 DQS1_c 34 DDRB_DQS0 6 DDRB_CS1# 159 CS1_n A13 160 DDRB_MA13 6
35 DM1_n/DBl1_n/NC DQS1_t 36 DDRB_ODT1 161 VDD_17 VDD_18 162
DDRB_DQ7 37 VSS_17 VSS_18 38 DDRB_DQ1 6 DDRB_ODT1 163 ODT1 C0/CS2_n/NC 164 +VREF_CA_DIMM
39 DQ15 DQ14 40 165 VDD_19 VREFCA 166 DDRB_SA2
DDRB_DQ3 41 VSS_19 VSS_20 42 DDRB_DQ2 167 C1/CS3_n/NC SA2 168

0.1u_0201_10V6K

2.2U_0402_6.3V6M
@
43 DQ10 DQ11 44 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ36
DDRB_DQ18 VSS_21 VSS_22 DDRB_DQ20 DQ37 DQ36 1 1
45 46 171 172
47 DQ21 DQ20 48 DDRB_DQ33 173 VSS_55 VSS_56 174 DDRB_DQ37
DDRB_DQ16 49 VSS_23 VSS_24 50 DDRB_DQ21 175 DQ33 DQ32 176
51 DQ17 DQ16 52 DDRB_DQS#4 177 VSS_57 VSS_58 178 2 2
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQS4 179 DQS4_c DM4_n/DBl4_n/NC 180

CD1

CD2
DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n/NC 56 181 DQS4_t VSS_59 182 DDRB_DQ34
57 DQS2_t VSS_27 58 DDRB_DQ17 DDRB_DQ39 183 VSS_60 DQ39 184
DDRB_DQ22 59 VSS_28 DQ22 60 185 DQ38 VSS_61 186 DDRB_DQ35
61 DQ23 VSS_29 62 DDRB_DQ19 DDRB_DQ38 187 VSS_62 DQ35 188
DDRB_DQ23 63 VSS_30 DQ18 64 189 DQ34 VSS_63 190 DDRB_DQ45
65 DQ19 VSS_31 66 DDRB_DQ24 DDRB_DQ41 191 VSS_64 DQ45 192
DDRB_DQ27 67 VSS_32 DQ28 68 193 DQ44 VSS_65 194 DDRB_DQ44
69 DQ29 VSS_33 70 DDRB_DQ29 DDRB_DQ40 195 VSS_66 DQ41 196
DDRB_DQ28 71 VSS_34 DQ24 72 197 DQ40 VSS_67 198 DDRB_DQS#5
73 DQ25 VSS_35 74 DDRB_DQS#3 199 VSS_68 DQS5_c 200 DDRB_DQS5
+1.2V 75 VSS_36 DQS3_c 76 DDRB_DQS3 201 DM5_n/DBl5_n/NC DQS5_t 202
77 DM3_n/DBl3_n/NC DQS3_t 78 DDRB_DQ47 203 VSS_69 VSS_70 204 DDRB_DQ46
DDRB_DQ25 79 VSS_37 VSS_38 80 DDRB_DQ26 205 DQ46 DQ47 206
81 DQ30 DQ31 82 DDRB_DQ43 207 VSS_71 VSS_72 208 DDRB_DQ42
DDRB_DQ30 83 VSS_39 VSS_40 84 DDRB_DQ31 209 DQ42 DQ43 210
DQ26 DQ27 DDRB_DQ53 VSS_73 VSS_74 DDRB_DQ52
1

85 86 211 212
RD92 RD93 87 VSS_41 VSS_42 88 213 DQ52 DQ53 214
240_0402_1% 240_0402_1% 89 CB5/NC CB4/NC 90 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ49
91 VSS_43 VSS_44 92 217 DQ49 DQ48 218
93 CB1/NC CB0/NC 94 DDRB_DQS#6 219 VSS_77 VSS_78 220
DDRB_DQS#8 VSS_45 VSS_46 DDRB_DQS6 DQS6_c DM6_n/DBl6_n/NC
2

95 96 221 222
DDRB_DQS8 97 DQS8_c DM8_n/DBI8_n/NC 98 223 DQS6_t VSS_79 224 DDRB_DQ55
99 DQS8_t VSS_47 100 DDRB_DQ54 225 VSS_80 DQ54 226
C
101 VSS_48 CB6/NC 102 227 DQ55 VSS_81 228 DDRB_DQ51 C
103 CB2/NC VSS_49 104 DDRB_DQ50 229 VSS_82 DQ50 230
105 VSS_50 CB7/NC 106 231 DQ51 VSS_83 232 DDRB_DQ56
107 CB3/NC VSS_51 108 CPU_DRAMRST# DDRB_DQ60 233 VSS_84 DQ60 234
DDRB_CKE0 109 VSS_52 RESET_n 110 DDRB_CKE1 CPU_DRAMRST# 6,17 235 DQ61 VSS_85 236 DDRB_DQ61
6 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 6 DDRB_DQ57 237 VSS_86 DQ57 238
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# 1 DQ56 VSS_87 DDRB_DQS#7
113 114 CD3 239 240
6 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 6 241 VSS_88 DQS7_c 242 DDRB_DQS7
0.1u_0201_10V6K
6 DDRB_BG0 117 BG0 ALERT_n 118 DDRB_ALERT# 6 243 DM7_n/DBl7_n/NC DQS7_t 244
@
DDRB_MA12 119 VDD_3 VDD_4 120 DDRB_MA11 2 DDRB_DQ59 245 VSS_89 VSS_90 246 DDRB_DQ62
6 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 6 247 DQ62 DQ63 248
6 DDRB_MA9 123 A9 A7 124 DDRB_MA7 6 DDRB_DQ58 249 VSS_91 VSS_92 250 DDRB_DQ63
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 251 DQ58 DQ59 252
6 DDRB_MA8 DDRB_MA6 127 A8 A5 128 DDRB_MA4 DDRB_MA5 6 SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
6 DDRB_MA6 129 A6 A4 130 DDRB_MA4 6 1 7,40
2 SMB_CLK_S3 +VDD_SPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 7,40
+3VS RD1 @
VDD_7 VDD_8 0_0603_5% 257 VDDSPD SA0 258
VPP_1 Vtt DDRB_SA1 +0.6VS
1 1 259 260
VPP_2 SA1
ARGOS_D4AS0-26001-1P60 CD4 CD5 261 262
2.2U_0402_6.3V6M 0.1u_0201_10V6K GND_1 GND_2
ME@ 2 2 ARGOS_D4AS0-26001-1P60
ME@

RD2 1 @ 2 +VPP
+2.5V_DDR
0_0603_5%

+1.2V

1
CD117 Note:
1

+0.6VS +2.5V_DDR
0.1u_0201_10V6K
2 VREF trace width:20 mils at least Layout Note:
RD3
1K_0402_1% Spacing:20mils to other signal/planes Place near DIMM
Place near DIMM scoket
@
2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
B 1 1 1 1 1 1 1 1 B
RD4 1 2 +VREF_CA_DIMM
5 DDR_SB_VREFCA
2_0402_5%
1
2 2 2 2 2 2 2 2

CD118
1
1

CD13

CD7
CD6

CD11

CD12
CD8

CD10
CD9
0.022U_0201_6.3V6-K RD5 CD14
2 1K_0402_1% 0.1u_0201_10V6K CD@ CD@
2
1

RD6
24.9_0402_1%

+1.2V
2

@
10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M

10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_0402_6.3V6K
1

220U_6.3V_M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CD31

CD32

CD35
CD23

CD24

CD26

CD29

CD30
CD21

CD25
CD22

CD27

CD28
CD20

CD34
CD19

CD33
CD@ CD@ CD@ CD@

+3VS +3VS +3VS

+1.2V
1

1
1

RD7 RD8 RD9


EMC_NS@

EMC_NS@
EMC_NS@

EMC_NS@

0_0402_5% 0_0402_5% 0_0402_5%


RF@

@ @ @
RF@
0.1u_0201_10V6K
4.7U_0402_6.3V6M

33P_0402_50V8J
0.1u_0201_10V6K
4.7U_0402_6.3V6M

33P_0402_50V8J
2

2
2

1 1 1 1 1 1
DDRB_SA0 DDRB_SA1 DDRB_SA2
A A
2 2 2 2 2 2
CD15

CD17

CD37
CD16

CD18

CD36
1

1
1

RD10 RD11 RD12


0_0402_5% 0_0402_5% 0_0402_5%
@ @ @
For EMC
Near JDDRL1
2

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 DDR4 SO-DIMM
SPD Address = 2H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 18 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 19 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 20 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 21 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 22 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 23 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 24 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 25 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 26 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 27 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 28 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 29 of 60


5 4 3 2 1
5 4 3 2 1

UW1

RW2 1 2 6.2K_0402_1% RREF 1 24 VDD18 1U_0402_6.3V6K 2 1 CW1


USB20_N5 RW9 1 @ 2 0_0402_5% USB20_N5_R 2 RREF V18 23
9 USB20_N5 USB20_P5 USB20_P5_R DM XD_D7
RW10 1 @ 2 0_0402_5% 3 22
9 USB20_P5 DP SP14 SD_D2_R
+3VS 4 21
CARD_3V3 5 3V3_IN SP13 20 SD_D3_R
SDREG 6 CARD_3V3 SP12 19
7 SDREG SP11 18 SD_CMD_R
D 1 1 D
CW2 CW3 SD_WP 8 XD_CD# SP10 17
4.7U_0402_6.3V6M 0.1u_0201_10V6K 9 SP1 GPIO0 16
SD_D1_R 10 SP2 SP9 15 SD_CLK_R
2 2 1 SP3 SP8
LW1 CW4 SD_D0_R 11 14
USB20_N5 1 2 USB20_N5_R 1U_0402_6.3V6K 12 SP4 SP7 13 SD_CD#
1 2 SP5 SP6
2 25
USB20_P5 4 3 USB20_P5_R GND
4 3
EXC24CH900U_4P RTS5170-GRT_QFN24_4X4
EMC_NS@
FOR EMI

SD_D0_R RW3 1 @ 2 0_0402_5% SD_D0


C C
CW5 1 2 5.6P_0402_50V8-D
SD / MMC
EMC@
CARD_3V3
SD_D1_R RW4 1 @ 2 0_0402_5% SD_D1 JREAD1
CW6 1 2 5.6P_0402_50V8-D 4
VDD

0.1u_0201_10V6K
4.7U_0402_6.3V6M
EMC@ SD_D0 7
1 1 DAT0
SD_D1 8
CW9 CW17 SD_D2 9 DAT1
SD_D2_R RW5 1 @ 2 0_0402_5% SD_D2 SD_D3 1 DAT2
CW7 1 2 5.6P_0402_50V8-D 2 2 CD/DAT3
SD_CD# 11
SD_WP 10 C/D
EMC@
W/P
SD_CMD 2
SD_D3_R SD_D3
Close to Connector SD_CLK CMD
RW6 1 @ 2 0_0402_5% 5
CW8 1 2 5.6P_0402_50V8-D CLK
3 12
6 VSS1 GND_1 13
EMC@
VSS2 GND_2
DEREN_404232501111RHF_NR
SD_CMD_R RW7 1 @ 2 0_0402_5% SD_CMD ME@
B CW11 1 2 5.6P_0402_50V8-D B

EMC@

SD_CLK_R RW8 1 2 0_0402_5% SD_CLK


Close to Connector
CW12 1 2 5.6P_0402_50V8-D

EMC@
CARD_3V3

AZ5123-01F.R7GR_DFN1006P2X2

1
DW1

1
2
EMC_NS@

2
FOR ESD
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Cardreader


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 30 of 60
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 31 of 60


5 4 3 2 1
5 4 3 2 1

+3VS +3VS_TPM

RTPM1 1 TPM@ 2 0_0603_5% 1A


D D
1 1
1 CTPM3
CTPM4 CTPM1 0.1u_0201_10V6K
0.1u_0201_10V6K 10U_0603_6.3V6M TPM@
TPM@ 2 TPM@ 2
2

TPM
+3VS_TPM
UTPM1 TPM@
1 24
2 NC_1 VDD3 10
C 3 NC_2 VDD1 C
NC_3 Reserve for Nationz TPM
RTPM12 1 TPM@ 2 7 28 RTPM2 1 TPM@ 2 4.7K_0402_5%
0_0402_5% PP LPCPD# 27 SERIRQ_TPM RTPM5 1 TPM@ 2 0_0402_5%
SERIRQ LPC_AD0_TPM SERIRQ 7,44
6 26 RTPM6 1 TPM@ 2 0_0402_5%
9 NC_4 LAD0 23 LPC_AD1_TPM 1 TPM@ 2 0_0402_5% LPC_AD0 7,44
Reserve for Nationz TPM NC_7 LAD1 LPC_FRAME#_TPM
RTPM7
LPC_AD1 7,44
22 RTPM8 1 TPM@ 2 0_0402_5%
LFRAME# LPC_AD2_TPM LPC_FRAME# 7,44
4 20 RTPM9 1 TPM@ 2 0_0402_5%
11 GND_1 LAD2 17 LPC_AD3_TPM 1 TPM@ 2 0_0402_5% LPC_AD2 7,44
RTPM10
+3VALW 18 GND_2 LAD3 LPC_AD3 7,44
GND_3 25 +3VS_TPM
RTPM11 1 TPM@ 2 5 GND_4 21
8 NC_5 LCLK 19 CLK_PCI_TPM 7
0_0603_5%
12 NC_6 VDD2 15 TPM_CLKRUN# RTPM13 1 @ 2
13 NC_8 CLK_RUN# PM_CLKRUN# 7
Add for Nuvoton TPM NC_9
0_0402_5%
14 16
NC_10 LRESET# PLT_RST# 11,37,40,44
Reserve for Nuvoton TPM

1
Z32H320TC-LPC-T28-LT1_TSSOP28 RTPM4
0_0402_5%
TPM@

2
B B

Nationz TPM Nuvoton TPM

RTPM2 Stuff NC

RTPM12 Stuff NC

RTPM11 NC Stuff

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 TPM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 32 of 60


5 4 3 2 1
5 4 3 2 1

LCD POWER CIRCUIT CMOS Camera


+3VS +3VS Need short +3VS_CMOS_R
+LCDVDD +LCDVDD_CON J1 @
1 2
U5 1 2
5 1 R263 1 @ 2 W=60mils W=40 mils JUMP_43X39
IN OUT

RF_NS@
1 2 0_0805_5% +3VS_CMOS
GND

0.1u_0201_10V6K

33P_0402_50V8J
4.7U_0402_6.3V6M
@ LP2301ALT1G_SOT23-3
C1 PCH_ENVDD 4 3
EN OCB 1 1 1 W=40mils
0.1u_0201_10V6K Q7 3 1 @ R3 1 @ 2

D
2 SY6288C20AAC_SOT23-5

0.01U_0201_10V6K
D 0_0603_5% D

@
2 2 2 1 1 1 1
C5 C3 C4

G
U5 EN PIN VIH MIN 1.5V

2
0.1u_0201_10V6K 0.1u_0201_10V6K 10U_0603_6.3V6M

C121

C122

C123
@ CD@ @
2 2 2 2

C6
CMOS_ON# R5 1 @ 2
100K_0402_5%
PCH_ENVDD For RF 1 1
4 PCH_ENVDD
C9 C10

1
0.01U_0201_25V6-K 0.1u_0201_10V6K
R1 EMC_NS@ @
100K_0402_5% 2 2
For EMI
Close to R5
2

R296 1 @ 2 0_0402_5% CMOS_ON# +3VS


8 PCH_CMOS_ON#

+3VS R297 1 @ 2 0_0402_5%


44 EC_CMOS_ON# EMI request

2
R8 R9
DMIC_CLK INVT_PWM
2

100K_0402_1% 100K_0402_1% DISPOFF#


R10
PCH_ENBKL

470P_0201_50V7-K
470P_0201_50V7-K
1 2

100P_0201_25V8J
R11 @ 4.7K_0402_5% @ @

1
0_0402_5% @

EMC_NS@
EMC_NS@
1 1 1

EMC@
1

EDP_AUX
R12 1 @ 2 0_0402_5% DISPOFF# V20B+ +LEDVDD EDP_AUX#
44 BKOFF# 2 2 2

C13
C11

C12
2A 80 mil 2A 80 mil

2
R14 1 @ 2 0_0402_5% ENBKL R17 1 @ 2 0_0805_5%
4 PCH_ENBKL ENBKL 44
R13 R15
C C
1

EMC@
4.7U_0805_25V6-K

0.1U_0201_25V6-K
100K_0402_1% 100K_0402_1%

CD@
R16 1 1
100K_0402_5% @ @

1
2 2
2

JEDP1
1

C14

C15
+LEDVDD 1
2
3 2
+3VS 4 3
CPU_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 5 4
EMI Request 4 CPU_EDP_TX0+ CPU_EDP_TX0- EDP_TX0- 5
C16 1 2 0.1u_0201_10V6K 6
4 CPU_EDP_TX0- 6
2

7
R18 CPU_EDP_TX1+ C17 1 2 0.1u_0201_10V6K EDP_TX1+ 8 7
4 CPU_EDP_TX1+ CPU_EDP_TX1- EDP_TX1- 8
1K_0402_5% C18 1 2 0.1u_0201_10V6K 9
4 CPU_EDP_TX1- 9
@ 10
CPU_EDP_AUX C20 1 2 0.1u_0201_10V6K EDP_AUX 11 10
4 CPU_EDP_AUX 11
1

CPU_EDP_AUX# C21 1 2 0.1u_0201_10V6K EDP_AUX# 12


INVT_PWM 4 CPU_EDP_AUX# 12
R19 1 @ 2 0_0402_5% 13
4 PCH_EDP_PWM 13
DISPOFF# 14
15 14
INVT_PWM 15
1

16
R20 17 16
100K_0402_5% +3VS 18 17
19 18
4 CPU_EDP_HPD 19
R21 1 @ 2 20
20
2

1 0_0402_5% +LCDVDD_CON 21
22 21
EMC_NS@ C22
W=60mils 23 22
+3VS 23
680P_0402_50V7K 43 DMIC_DATA 24
2 25 24
43 DMIC_CLK 25
26
27 26
R182 1 @ 2 0_0402_5% USB20_P4_R 28 27
9 USB20_P4 28
B R183 1 @ 2 0_0402_5% USB20_N4_R 29 B
9 USB20_N4 29
+3VS_CMOS 30
31 30
W=40mils
Touch Screen C24
1 32 G1
G2
.047U_0201_6.3V6K DRAPH_FC5AF301-3181H
EMC_NS@ ME@
2
+5VS +5VS_TS

R26 1 @ 2 0_0402_5% EMI request


JTS1
1
C25 1
0.1u_0201_10V6K 2 1 7
TS@ R28 1 @ 2 0_0402_5% TS_RS 3 2 GND1
2 44 EC_TS_ON 3
4 8
R23 1 @ 2 0_0402_5% USB20_N6_CONN 5 4 GND2
9 USB20_N6 USB20_P6_CONN 5
R24 1 @ 2 0_0402_5% 6
9 USB20_P6 6
CVILU_CI1806M2HR0-NH For EMI
ME@ L12 EMC_NS@
USB20_N4 1 2 USB20_N4_R
1 2
Touch Screen
USB20_P4 4 3 USB20_P4_R
4 3
EXC24CH900U_4P
USB20_P6_CONN

USB20_N6_CONN

+5VS_TS
3

L15
USB20_P6 1 2 USB20_P6_CONN
1 2
A A
1

D2
USB20_N6 4 3 USB20_N6_CONN
1

4 3
EXC24CH900U_4P
EMC_NS@ D1
AZC199-02S.R7G_SOT23-3
2

EMC_NS@
AZ5725-01F.R7GR_DFN1006P2X2
2

EMC_NS@ Title
For EMI Security Classification LC Future Center Secret Data
1

For EMI Issued Date 2015/08/20 Deciphered Date 2016/08/20 eDP/CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 33 of 60
5 4 3 2 1
5 4 3 2 1

L2 EMC@ EMC_NS@
HDMI_CLK-_C 1 2 HDMI_CLK-_CON 1 2
1 2 C26 3.3P_0402_50V8-C
EMC_NS@
HDMI_CLK+_C 4 3 HDMI_CLK+_CON 1 2
4 3 C27 3.3P_0402_50V8-C
EXC24CH900U_4P
+3VS
D L3 EMC@ EMC_NS@ D
HDMI_TX0-_C 1 2 HDMI_TX0-_CON 1 2
1 2 C28 3.3P_0402_50V8-C
EMC_NS@
HDMI_TX0+_C 4 3 HDMI_TX0+_CON 1 2
4 3 C29 3.3P_0402_50V8-C

5
EXC24CH900U_4P

G
Q1B D3
HDMI_DET 1 1 HDMI_DET
L4 EMC@ EMC_NS@ 10 9
HDMI_TX1-_C 1 2 HDMI_TX1-_CON 1 2
1 2 4 3 HDMICLK_R HDMIDAT_R 2 2 HDMIDAT_R
C30 3.3P_0402_50V8-C 9 8

S
4 DDPB_CLK

D
EMC_NS@
HDMI_TX1+_C 4 3 HDMI_TX1+_CON 1 2 2N7002KDWH_SOT363-6 HDMICLK_R 4 4 7 7 HDMICLK_R
4 3

2
C31 3.3P_0402_50V8-C

G
EXC24CH900U_4P Q1A +5VS_HDMI 5 5 6 6 +5VS_HDMI

L5 EMC@ EMC_NS@ 3 3
HDMI_TX2-_C 1 2 HDMI_TX2-_CON 1 2 1 6 HDMIDAT_R

S
1 2 4 DDPB_DATA

D
C32 3.3P_0402_50V8-C 8
EMC_NS@ 2N7002KDWH_SOT363-6
HDMI_TX2+_C 4 3 HDMI_TX2+_CON 1 2
4 3 C33 3.3P_0402_50V8-C AZ1045-04F_DFN2510P10E-10-9
EXC24CH900U_4P EMC_NS@

For EMC
For EMC

C C
HDMI_CLK-_C R29 1 2 470_0402_5% +5VS +5VS_HDMI_F +5VS_HDMI
D5
HDMI_CLK+_C R30 1 2 470_0402_5% +5VS 2 F1
+3VS 1 1 2
HDMI_TX0-_C R31 1 2 470_0402_5% 3

2
D4 RB491D_SOT23-3 0.5A_6V_1206L050YRHF
HDMI_TX0+_C R32 1 2 470_0402_5% @
HDMI_TX1-_C R33 1 2 470_0402_5% @ LP2301ALT1G_SOT23-3

2
HDMI_TX1+_C R34 1 2 470_0402_5% BAT54S-7-F_SOT23-3 1 3 Q22

S
R35 1

1
2
Q12 D4 C34

G
HDMI_TX2-_C 1M_0402_5%
R37 1 2 470_0402_5% 0.1u_0201_10V6K

G
1

2
HDMI_TX2+_C R38 1 2 470_0402_5% 2

2
3 1
4 HDMI_HPD 46 SUSP

D
R39 R40
1

D Q13 2N7002KW_SOT323-3 2.2K_0402_5% 2.2K_0402_5%

2
2
+3VS G 2N7002KW_SOT323-3 R41

1
20K_0402_5%
S JHDMI1
3

HDMI_DET 19
HP_DET

1
R42 1 @ 2 18
17 +5V
100K_0402_5% HDMIDAT_R 16 DDC/CEC_GND
HDMICLK_R 15 SDA
14 SCL
13 Reserved
HDMI_CLK- C35 2 1 0.1u_0201_10V6K HDMI_CLK-_C R43 2 @ 1 0_0402_5% HDMI_CLK-_CON 12 CEC 20
4 HDMI_CLK- CK- GND1
11 21
B HDMI_CLK+ C36 2 1 0.1u_0201_10V6K HDMI_CLK+_C R44 2 @ 1 0_0402_5% HDMI_CLK+_CON 10 CK_shield GND2 22 B
4 HDMI_CLK+ HDMI_TX0- HDMI_TX0-_C R45 2 HDMI_TX0-_CON CK+ GND3
C37 2 1 0.1u_0201_10V6K @ 1 0_0402_5% 9 23
4 HDMI_TX0- D0- GND4
8
HDMI_TX0+ C38 2 1 0.1u_0201_10V6K HDMI_TX0+_C R46 2 @ 1 0_0402_5% HDMI_TX0+_CON 7 D0_shield
4 HDMI_TX0+ HDMI_TX1- HDMI_TX1-_C R47 2 HDMI_TX1-_CON D0+
C39 2 1 0.1u_0201_10V6K @ 1 0_0402_5% 6
4 HDMI_TX1- D1-
5
HDMI_TX1+ C40 2 1 0.1u_0201_10V6K HDMI_TX1+_C R48 2 @ 1 0_0402_5% HDMI_TX1+_CON 4 D1_shield
4 HDMI_TX1+ HDMI_TX2- HDMI_TX2-_C R49 2 HDMI_TX2-_CON D1+
C41 2 1 0.1u_0201_10V6K @ 1 0_0402_5% 3
4 HDMI_TX2- D2-
2
HDMI_TX2+ C42 2 1 0.1u_0201_10V6K HDMI_TX2+_C R50 2 @ 1 0_0402_5% HDMI_TX2+_CON 1 D2_shield
4 HDMI_TX2+ D2+
SINGA_2HE3Y37-000111F
ME@

Close to JHDMI1
D6 D7
HDMI_CLK+_CON 1 1 10 9 HDMI_CLK+_CON HDMI_TX1-_CON 1 1 HDMI_TX1-_CON
10 9
HDMI_CLK-_CON 2 2 9 8 HDMI_CLK-_CON HDMI_TX1+_CON 2 2 9 8 HDMI_TX1+_CON

HDMI_TX0+_CON 4 4 7 7 HDMI_TX0+_CON HDMI_TX2-_CON 4 4 7 7 HDMI_TX2-_CON

HDMI_TX0-_CON 5 5 6 6 HDMI_TX0-_CON HDMI_TX2+_CON 5 5 6 6 HDMI_TX2+_CON


A A
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 For EMC AZ1045-04F_DFN2510P10E-10-9


EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data Title
Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDMI_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 34 of 60
5 4 3 2 1
5 4 3 2 1

+3VS +DP_3V3 +AVCC33

+5VS +5VS_HV
RVG1 1 @ 2 RVG2 1 @ 2 0_0402_5%
0_0603_5% +VDD_DAC_33
+CRT_VCC_CON RVG3 1 @ 2
0_0603_5%
RVG4 1 @ 2 0_0402_5%
RVG5 1 @ 2 0_0603_5%
+5VS_HV
D 1 D
CVG1
10U_0603_6.3V6M
@

0.1u_0201_10V6K

4.7U_0603_10V6-K
2
1 1
06/21 P/N from SA00007QZ00 change to SA00007QZ10
For FW Update
2 2

CVG2

CVG3
+AVCC33
UVG1

1 17
AVCC_33 HVSYNC_PWR
CVG4 1 2 0.1u_0201_10V6K AUXP 2 18 VGA_VS
4 VGA_AUX AUX_P VSYNC VGA_VS 36
CVG5 1 2 0.1u_0201_10V6K AUXN 3 19 VGA_HS
4 VGA_AUX# AUX_N HSYNC VGA_HS 36
CVG6 1 2 0.1u_0201_10V6K +VCCK_12 4 20 +VDD_DAC_33 CVG7 1 2 0.1u_0201_10V6K
AVCC_12 VDD_DAC_33
CVG8 1 2 0.1u_0201_10V6K DRX0P 5 21 CRT_B
4 VGA_TX0+ LANE0_P BLUE_P CRT_B 36
CVG9 1 2 0.1u_0201_10V6K DRX0N 6 22 CRT_G
4 VGA_TX0- LANE0_N GREEN_P CRT_G 36
CVG10 1 2 0.1u_0201_10V6K DRX1P 7 23 CRT_R
4 VGA_TX1+ LANE1_P RED_P CRT_R 36
CVG11 1 2 0.1u_0201_10V6K DRX1N 8 24
4 VGA_TX1- LANE1_N GND
C C
RVG6 1 2 4.7K_0402_5% POL2 9 25 +VCCK_12
+DP_3V3 POL2 VCCK_12
RVG7 1 2 4.7K_0402_5% POL1 10 26 +DP_3V3 CVG12 1 2 0.1u_0201_10V6K
+DP_3V3 POL1/SPI_CEB PVCC_33
DP_GP11 DP_LDO_RST# 1 1
11 27 RVG20 1 @ 2 4.7K_0402_5%
GPI1/SPI_CLK LDO_RSTB +DP_3V3
CVG13 CVG14
DP_GP12 12 28 DP_EXT_CLKIN 1 TVG2 @ 0.1u_0201_10V6K 2.2U_0402_6.3V6M
GPI2/SPI_SI EXT_CLK_IN 2 2
@ TVG3 1 DP_GP13 13 29 DP_SMB_SDA 1 TVG4 @
GPI3/SPI_SO SMB_SDA
1

RVG8 RVG9 14 30 DP_SMB_SCL 1 TVG5 @


+DP_3V3 VCC_33 SMB_SCL
4.7K_0402_5% 4.7K_0402_5%
@ @ CRT_DDC_CLK 15 31 DP_EXT1.2V_EN 1 TVG6 @
36 CRT_DDC_CLK VGA_SCL EXT1.2V_CTRL
2

CRT_DDC_DAT 16 32 DP_VGA_HPD
DP_GP11 36 CRT_DDC_DAT VGA_SDA HPD DP_VGA_HPD 4
33
DP_GP12 EPAD
CRT_R

RTD2166-CG_QFN32_4X4
CRT_G
1

RVG10 RVG11
4.7K_0402_5% 4.7K_0402_5%
@ @ CRT_B
2

B B

1
RVG12 RVG13 RVG14
75_0402_1% 75_0402_1% 75_0402_1%

2
CLOSE TO UVG1

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 P35-DP to VGA (RTD2166)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 35 of 60


5 4 3 2 1
5 4 3 2 1

+CRT_VCC_CON
CRT Connector

2
1
+CRT_VCC_CON +5VS_HDMI
RPVG1
+5VS @
2.2K_0404_4P2R_5% +CRT_VCC RVG15 1 2 0_0603_5%
DVG1

3
4
@ 2 FVG1
CRT_DDC_DAT RVG16 1 @ 2 0_0402_5% CRT_DDC_DAT_R 1 1 2 @ +CRT_VCC_CON
35 CRT_DDC_DAT 3
D CRT_DDC_CLK CRT_DDC_CLK_R 1 D
RVG17 1 @ 2 0_0402_5% RB491D_SOT23-3 0.5A_6V_1206L050YRHF CVG15
35 CRT_DDC_CLK

1
0.1u_0201_10V6K
CD@ DVG2
1 1 W=40mils

1
CVG16 CVG17 2 AZ5725-01F.R7GR_DFN1006P2X2
100P_0201_25V8J 68P_0201_50V8-J EMC_NS@
@ @
2 2

2
2
0229: Need update symbols in SIT phase JCRT1
6
11
LVG1 1 2 EMC@ CRT_R_CON 1
35 CRT_R 7
BLM18BB220SN1D_2P
CRT_DDC_DAT_R
For EMC
12
LVG2 1 2 EMC@ CRT_G_CON 2
35 CRT_G 8
BLM18BB220SN1D_2P
HSYNC_CON 13
LVG3 1 2 EMC@ CRT_B_CON 3
35 CRT_B 9
BLM18BB220SN1D_2P
VSYNC_CON 14

CVG18

CVG19

CVG20

CVG21

CVG22

CVG23
2.2P_0402_50V8-C

2.2P_0402_50V8-C

2.2P_0402_50V8-C

2.2P_0402_50V8-C

2.2P_0402_50V8-C

2.2P_0402_50V8-C
1 1 1 1 1 1 4
10 G 16
CRT_DDC_CLK_R 15 17
G
5
2 2 2 2 2 2

EMC@

EMC@

EMC@

EMC@

EMC@

EMC@
1
CVG24 SUYIN_070546HR015M25KZR
100P_0201_25V8J ME@
@
2

C C

0714: SVT For VGA 20m cable test issue change to 100ohm

VGA_HS RVG18 1 2 100_0402_5% HSYNC_CON


35 VGA_HS

1
CVG25
2.2P_0402_50V8-C
@
2

VGA_VS RVG19 1 2 100_0402_5% VSYNC_CON


35 VGA_VS
1
CVG26
2.2P_0402_50V8-C
@
2

B B

DVG3 DVG4
CRT_B_CON 1 1 CRT_B_CON VSYNC_CON VSYNC_CON
10 9 1 1 10 9
CRT_G_CON 2 2 9 8 CRT_G_CON HSYNC_CON 2 2 9 8 HSYNC_CON

CRT_R_CON 4 4 7 7 CRT_R_CON CRT_DDC_CLK_R 4 4 7 7 CRT_DDC_CLK_R

5 5 6 6 CRT_DDC_DAT_R 5 6 6 CRT_DDC_DAT_R
5
3 3 3 3

8 8

AZ1045-04F_DFN2510P10E-10-9 AZ1045-04F_DFN2510P10E-10-9
A
EMC_NS@ EMC_NS@ A
For EMC

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 CRT_CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 36 of 60
5 4 3 2 1
5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising t i me ( 10 %~90 %):
+3VALW +3VALW_LAN
s pec< 10 0m s
0.5ms < +3VALW_LAN +LAN_VDDREG
Need short
RL1 @
JL1 1 2 @ width : 40 mils 1 2
1 2
JUMP_43X79 0_0603_5%
D D
1 1
+3VALW LP2301ALT1G_SOT23-3 CL4 CL5 CL1 CL2

0.1u_0201_10V6K

0.1u_0201_10V6K
4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
1 1 CL6 1 CL7 1 4.7U_0402_6.3V6M 0.1u_0201_10V6K
Q14 3 1 @

0.01U_0201_10V6K
2 2
1

0.1u_0201_10V6K
RL2 1 CL8 CL9 1
100K_0402_5% 2 2 2 2

G
2
@
@ @
2

2 2
RL3 1 @ 2 @ @
44 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32
+3VALW_LAN +3VS

+3VALW_LAN

2
@

2
RL4

G
2
RL5 manual change the Codec PN to RTL8111GUL-CG 10K_0402_5% QL1

10K_0402_5% UL1

1
@ LAN_CLKREQ#_R 1 3 @
LAN_CLKREQ# 10

S
1
2N7002KW_SOT323-3
RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R
11,40,44 PCIE_WAKE#
40,44 LAN_WAKE# RL6 1 @ 2 0_0402_5%
33 RL18 1 @ 2 0_0402_5%
C 32 +3VALW_LAN GND 16 CLK_PCIE_LAN# C
1 2 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN CLK_PCIE_LAN# 10
RL8 RSET
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N5 CLK_PCIE_LAN 10
2.49K_0402_1% 30 14
29 LAN_XTALO AVDD10 HSIN 13 PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_N5 9
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P5 9
28 12
+3VS TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# @ LAN_DISABLE# LED0 AVDD33_1 LAN_MDI3-
RL121 2 26 10
LED1/GPIO MDIN3 LAN_MDI3+ LAN_MDI3- 38
0_0402_5% TL4 @ 1 25 9
+LAN_REGOUT LED2 MDIP3 +LAN_VDD10 LAN_MDI3+ 38
1

24 8
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 38
1K_0402_1% 22 6
PCIE_WAKE#_R 21 DVDD10 MDIP2 5 LAN_MDI1- LAN_MDI2+ 38
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- 38
ISOLATE# 20 4
ISOLATEB MDIP1 LAN_MDI1+ 38
2

PLT_RST# 19 3 +LAN_VDD10
11,32,40,44 PLT_RST# PERSTB AVDD10_1
CL10 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_N5 18 2 LAN_MDI0-
LAN_PWR_ON# 9 PCIE_PRX_DTX_N5 HSON MDIN0 LAN_MDI0- 38
ISOLATE# RL10 1 @ 2 CL11 1 2 0.1u_0201_10V6K PCIE_PRX_C_DTX_P5 17 1 LAN_MDI0+
9 PCIE_PRX_DTX_P5 HSOP MDIP0 LAN_MDI0+ 38
0_0402_5% CL10 close to Pin18
1

RL11 CL11 close to Pin17


15K_0402_5%
@
2

RTL8111GUL-CG QFN 32P


8111GUL@

B B

LAN_XTALI
For RTL8111GUL(SWR mode, reserved)
LAN_XTALO_R 1 2 LAN_XTALO For RTL8111H (LDO mode)
RL21 1K_0402_5% +LAN_VDD10
YL1 LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
1 4
OSC1 GND2 +LAN_REGOUT RL20 1 2 8111H@
2 3 0_0805_5%
GND1 OSC2
1 1 1 1 1 1 1 1
1 1
CL12 25MHZ_10PF_7V25000014 CL13 CL15 CL16 CL17 CL18 CL19 CL20 CL21 CL22
12P_0402_50V8-J 15P_0402_50V8J 4.7U_0402_6.3V6M 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 0.1u_0201_10V6K 1U_0402_6.3V6K 0.1u_0201_10V6K
2 2 2 2 2 2 2 2
2 2

Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)


Layout Note: LL1 must be
within 200mil to Pin24,
CL15,CL16 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_RTL8111H_CG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 37 of 60


5 4 3 2 1
5 4 3 2 1

DL1/DL2
1'S PN:SC300003M00
TL1
24 1 MCT
D MCT1 TCT1 D
LAN_MDI0+ 23 2 LAN_MDO0+
37 LAN_MDI0+ MX1+ TD1+
DL1
LAN_MDI2+ 1 10 LAN_MDI2+ LAN_MDI0- 22 3 LAN_MDO0-
LINE1IN LINE1OUT 37 LAN_MDI0- MX1- TD1-

1
EMC@
LAN_MDI2- 2 9 LAN_MDI2- 21 4 MCT RL17
LINE2IN LINE2OUT MCT2 TCT2 20_0603_5%
LAN_MDI1+ LAN_MDO1+

1
3 8 20 5
GND1 GND2 37 LAN_MDI1+ MX2+ TD2+ DL3

1
2
LAN_MDI3+ 4 7 LAN_MDI3+ LAN_MDI1- 19 6 LAN_MDO1- PDT5061_DO-214AA
LINE3IN LINE3OUT 37 LAN_MDI1- MX2- TD2- EMC@
LAN_MDI3- 5 6 LAN_MDI3- 18 7 MCT

2
LINE4IN LINE4OUT MCT3 TCT3 EMC

2
11 13 LAN_MDI2+ 17 8 LAN_MDO2+
GND3 GND5 37 LAN_MDI2+ MX3+ TD3+
12 LAN_MDI2- 16 9 LAN_MDO2-
GND4 37 LAN_MDI2- MX3- TD3-
AZ3133-08F.R7G_DFN3020P10E10 15 10 MCT
EMC_NS@ MCT4 TCT4
1 1
LAN_MDI3+ 14 11 LAN_MDO3+ CL32 CL25
37 LAN_MDI3+ MX4+ TD4+ 0.022U_0603_50V7K 1000P_1206_2KV7-K
LAN_MDI3- 13 12 LAN_MDO3- EMC@ EMC@
37 LAN_MDI3- MX4- TD4- 2 2
1 EMC
C
DL2 CL24 C
LAN_MDI1- 1 10 LAN_MDI1- 0.01U_0201_25V6-K BOTH_GST5009 LF
LINE1IN LINE1OUT EMC@
LAN_MDI1+ 2 9 LAN_MDI1+ 2
LINE2IN LINE2OUT
3 8 EMC
GND1 GND2
LAN_MDI0- 4 7 LAN_MDI0- CHASSIS1_GND
LINE3IN LINE3OUT
LAN_MDI0+ 5 6 LAN_MDI0+
LINE4IN LINE4OUT
11 13
GND3 GND5
12
GND4
AZ3133-08F.R7G_DFN3020P10E10
EMC_NS@
JRJ1 ME@
12
GND_4
Place Close to TL1
11
GND_3
EMC
10
LAN_MDO0+ 1 GND_2
PR1+ 9
B B
LAN_MDO0- 2 GND_1
PR1-
LAN_MDO1+ 3
PR2+ CHASSIS1_GND
LAN_MDO2+ 4
PR3+
LAN_MDO2- 5
@ PR3-
RL14 1 2 0_0603_5% LAN_MDO1- 6
@ PR2-
RL15 1 2 0_0603_5% LAN_MDO3+ 7
@ PR4+
RL16 1 2 0_0603_5% LAN_MDO3- 8
PR4-
EMC
SANTA_130460-3

CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 LAN_Transformer
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 38 of 60


5 4 3 2 1
5 4 3 2 1

R175 1 @ 2 0_0402_5% REMOTE1+

Close to U1 REMOTE+_R R176 1 @ 2 0_0402_5% REMOTE2+ REMOTE1+


Near GPU&VRAM REMOTE2+
Near CPU core
1
REMOTE+_R

1
1 C46 C

1
1 C45 C 100P_0201_25V8J 2 Q16
C44 REMOTE-_R R177 1 @ 2 0_0402_5% REMOTE2- 100P_0201_25V8J 2 Q15 @ B MMBT3904WH_SOT323-3
2200P_0201_25V7-K @ B MMBT3904WH_SOT323-3 2 E @

3
@ 2 E @ REMOTE2-

3
2 REMOTE-_R R178 1 @ 2 0_0402_5% REMOTE1- REMOTE1-

+3VALW
D REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: +3VALW D

Trace width/space:10/10 mil Near CPU


Trace length:<8"

1
R36
13.7K_0402_1% R25
13.7K_0402_1%

2
NTC_V1

2
NTC_V2
SMSC thermal sensor

1
R287
placed near DIMM 100K_0402_1%_NCP15WF104F03RC
OPT@
R288
100K_0402_1%_NCP15WF104F03RC
+3VS

2
U1 @

2
1 8 EC_SMB_CK2
VDD SCL EC_SMB_CK2 7,44

2
REMOTE+_R 2 7 EC_SMB_DA2 R184 R185
1 D+ SDA EC_SMB_DA2 7,44
C47 0_0402_5% 0_0402_5%
0.1u_0201_10V6K REMOTE-_R 3 6 OPT@ @
@ D- ALERT#

1
2 R51 2 @ 1 4 5
+3VS T_CRIT# GND
10K_0402_5%
NCT7718W_MSOP8
EC_AGND
Address 1001_101xb for layout optimized, change the EC_AGND to GND

C C

+5VLP +5VLP
+5VLP

HW thermal sensor
2

2
1 R252 R253
C7 21.5K_0402_1% 21.5K_0402_1%
0.1u_0201_10V6K @ @
@
1

1
2
U4 @
1 8 TMSNS1 R196 1 @ 2 0_0402_5% NTC_V1
VCC TMSNS1 NTC_V1 44
2 7 PHYST1 R6 1 @ 2 10K_0402_5%
GND RHYST1
3 6 TMSNS2 R197 1 @ 2 0_0402_5% NTC_V2
44,54,55 EC_ON OT1 TMSNS2 NTC_V2 44
4 5 PHYST2 R7 1 @ 2 10K_0402_5%
OT2 RHYST2
G718TM1U_SOT23-8

B over temperature threshold: B

RSET=3*RTMH
92+/-30C
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

FAN Conn
+5VS

JFAN1
R52 1 @ 2 0_0603_5% +5VS_FAN 1
2 1
44 EC_FAN_SPEED 2
@ 3

0.1u_0201_10V6K
4 3
1 1 44 EC_FAN_ANTI 4
C49 44 EC_FAN_PWM 5
10U_0805_10V6K 6 5
7 GND1
2 2 GND2

C50
ACES_50273-0050N-001
ME@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 Thermal sensor/FAN CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 39 of 60
5 4 3 2 1
A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VS
+3VS_WLAN

+3VS +3VS_WLAN
Need short
J2 @ JWLAN1
1 1

1
1 2 1 2
1 2 3 GND1 3.3VAUX1 4 R258 R259
9 USB20_P7 USB_D+ 3.3VAUX2
JUMP_43X79 1 5 6 1 @ T2 49.9K_0402_1% 49.9K_0402_1%
9 USB20_N7 USB_D- LED#1
C53 7 8
0.1u_0201_10V6K 9 GND2 PCM_CLK 10
SDIO_CLK PCM_SYNC

2
@ 11 12
2 13 SDIO_CMD PCM_IN 14
15 SDIO_DAT0 PCM_OUT 16 1 @ T3
17 SDIO_DAT1 LED#2 18
19 SDIO_DAT2 GND11 20
21 SDIO_DAT3 UART_WAKE 22 UART_RX_DEBUG_R R256 1 @ 2 0_0402_5%
SDIO_WAKE UART_RX UART_RX_DEBUG 8
23
SDIO_RESET

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 UART_TX_DEBUG_R R257 1 @ 2 0_0402_5%


GND3 UART_TX UART_TX_DEBUG 8
35 34
9 PCIE_PTX_C_DRX_P6 PETP0 UART_CTS
37 36
9 PCIE_PTX_C_DRX_N6 PETN0 UART_RTS EC_TX_RSVD
39 38 R62 1 @ 2 0_0402_5%
41 GND4 RSRVD10 40 EC_RX_RSVD R63 1 @ 2 0_0402_5%
9 PCIE_PRX_DTX_P6 PERP0 RSRVD11
43 42
9 PCIE_PRX_DTX_N6 PERN0 RSRVD9
45 44 R88 1 @ 2 0_0402_5%
GND5 COEX3 EC_RX 44
47 46
10 CLK_PCIE_WLAN REFCLKP0 COEX2
49 48
10 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
2 51 50 R55 1 @ 2 0_0402_5% 2
WLAN_CLKREQ_Q# GND6 SUSCLK PLT_RST# SUSCLK 10
10 WLAN_CLKREQ# R61 1 @ 2 0_0402_5% 53 52
PCIE_WAKE#_WLAN CLKEQ0# PERSTO# BT_OFF# PLT_RST# 11,20,32,37,44
R262 1 @ 2 0_0402_5% 55 54 R53 1 2 1K_0402_5%
11,37,44 PCIE_WAKE# PEWAKE0# RSRVD/W_DISABLE#2 WLAN_OFF# PCH_BT_OFF# 8
57 56 R56 1 @ 2 0_0402_5%
GND7 W_DISABLE#1 PCH_WLAN_OFF# 8
R57 1 @ 2 0_0402_5%
37,44 LAN_WAKE#
59 58 WLAN_SMB_DATA R58 1 @ 2 0_0402_5%
RSRVD/PETP1 I2C_DATA WLAN_SMB_CLK SMB_DATA_S3 7,18
61 60 R59 1 @ 2 0_0402_5%
RSRVD/PETN1 I2C_CLK SMB_CLK_S3 7,18
63 62
65 GND8 ALERT 64 EC_TX_R R89 1 @ 2 0_0402_5%
RSRVD/PERP1 RSRVD6 EC_TX 44
67 66
69 RERVD/PERN1 RSRVD7 68 +3VS_WLAN
GND9 RSRVD8

1
71 70
73 RSRVD1 RSRVD12 72 R186
75 RSRVD2 3.3VAUX3 74 100K_0402_5%
GND10 3.3VAUX4
77 76
GND15 GND14

2
LCN_DAN05-67406-0102
ME@

3 3

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 NGFF WLAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 40 of 60
A B C D E
A B C D E

+USB_VCCA

C55 1 2

+
220U_6.3V_M

C1111 1 2
@ 47U_0805_6.3V6-M

C125 1 2
@ 1U_0402_10V6K
1 LEFT SIDE USB3.0 PORT x1 C127
@
1 2
1U_0402_10V6K
1

JUSB1 ME@
USB30_TX_P1 C126 1 2 0.1u_0201_10V6K USB30_TX_C_P1 R95 1 @ 2 0_0402_5% USB30_TX_R_P1 9
9 USB30_TX_P1 1 StdA_SSTX+
+5VALW +USB_VCCA USB30_TX_N1 C124 1 2 0.1u_0201_10V6K USB30_TX_C_N1 R96 1 @ 2 0_0402_5% USB30_TX_R_N1 8 VBUS
9 USB30_TX_N1 USB20_P1 1 2 0_0402_5% USB20_P1_R 3 StdA_SSTX-
U2 R97 @
5 1 9 USB20_P1 7 D+
IN OUT USB20_N1 R93 1 @ 2 0_0402_5% USB20_N1_R 2 GND_DRAIN 10
1 9 USB20_N1 USB30_RX_P1 USB30_RX_R_P1 D- GND_1
C128 2 R94 1 @ 2 0_0402_5% 6 11
1U_0402_6.3V6K GND 9 USB30_RX_P1 4 StdA_SSRX+ GND_2 12
4 3 USB_OC1# USB30_RX_N1 R98 1 @ 2 0_0402_5% USB30_RX_R_N1 5 GND_5 GND_3 13
2 44,45 USB_ON# ENB OCB USB_OC1# 9 9 USB30_RX_N1 StdA_SSRX- GND_4
SY6288D20AAC_SOT23-5 1 SUYIN_020053GR009M2736L
C140
1000P_0201_50V7-K
Low Active 2A 2
EMC_NS@

2 2

L13 EMC@
USB30_RX_P1 1 2 USB30_RX_R_P1
1 2

USB30_RX_N1 4 3 USB30_RX_R_N1
4 3
EXC24CH900U_4P
+USB_VCCA D12 EMC_NS@ USB20_P1_R
USB30_RX_R_N1 9 USB30_RX_R_N1
L16 EMC@ 10 1 1

AZ5725-01F.R7GR_DFN1006P2X2
USB30_TX_C_P1 1 2 USB30_TX_R_P1 USB20_N1_R
1 2 USB30_RX_R_P1 8 2 USB30_RX_R_P1
9 2

1
D11
USB30_TX_C_N1 USB30_TX_R_N1 USB30_TX_R_N1 7 4USB30_TX_R_N1

2
4 3 7 4

1
4 3 D13
USB30_TX_R_P1 6 5 USB30_TX_R_P1
EXC24CH900U_4P 6 5 AZC199-02S.R7G_SOT23-3
EMC_NS@
L8 EMC@ 3 3
USB20_P1 1 2 USB20_P1_R

2
1 2 EMC_NS@ 8

2
USB20_N1 4 3 USB20_N1_R AZ1045-04F_DFN2510P10E-10-9
3 4 3 3
EXC24CH900U_4P

1
EMC EMC

4 4

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 USB3.0 PORT (LEFT)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 41 of 60
A B C D E
A B C D E F G H

SATA HDD Conn.


FOR 14"
JHDD1

10
SATA ODD Conn.
SATA_PTX_DRX_P0 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 9 10
9 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 9
9 SATA_PTX_DRX_N0 C67 1 2 0.01U_0201_10V6K 8
7 8 12
1 SATA_PRX_DTX_N0 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 6 7 GND2 1
9 SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 5 6 JODD1
9 SATA_PRX_DTX_P0 4 5 1
3 4 11 SATA_PTX_DRX_P1 14@ C70 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_14 2 GND_1
3 GND1 9 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 SATA_PTX_C_DRX_N1_14 RX+
2 9 SATA_PTX_DRX_N1 14@ C71 1 2 0.01U_0201_10V6K 3
1 2 4 RX-
+5VS +5VS_HDD 1 SATA_PRX_DTX_N1 14@ C72 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_14 5 GND_2
Need short ELCO_006809610010846 9 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 14@ C73 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_14 6 TX-
9 SATA_PRX_DTX_P1 7 TX+
ME@ GND_3
J3 1 2 @
1 2 8
JUMP_43X79 9 DP
+5V_ODD 10 +5V_1
11 +5V_2 14
12 MD GND1 15
13 GND_4 GND2
GND_5
+5VS_HDD SUYIN_127382FB013S255ZL
ME@

1 1 1 1 1
C74 C76 C75 C77 C78
33P_0201_50V8-J 33P_0201_50V8-J 0.1u_0201_10V6K 10U_0805_10V6K 10U_0805_10V6K
@ @ @
2 2 2 2 2

FOR 15"
2 2

For EMC SATA ODD FFC Conn

JODD2
1
SATA_PTX_DRX_P1 15@ C79 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P1_15 2 1
SATA_PTX_DRX_N1 15@ C80 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N1_15 3 2
4 3
SATA_PRX_DTX_N1 15@ C81 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N1_15 5 4
SATA_PRX_DTX_P1 15@ C82 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P1_15 6 5
7 6 9
+5V_ODD 8 7 GND1 10
8 GND2
HIGHS_FC1AF081-1151H
ME@

+5VS +5V_ODD
3
Need Short 3
J4 @
1 2
1 2
JUMP_43X79
10U_0805_10V6K

1 1 0.1u_0201_10V6K

2 2
C85

C86

CD@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 HDD/ODD CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 42 of 60
A B C D E F G H
5 4 3 2 1

+3VS

+3VS +3VALW_PCH RA3 1 @ 2 0_0603_5%


+3VALW +5VA AVDD_HP
RA2 1 @ 2 0_0603_5% +3.3VD RA44 1 @ 2 0_0402_5%

0.1u_0201_10V6K

0.1u_0201_10V6K
+3VS RA5 1 @ 2 0_0603_5% AVDD_HP
2 2
+3VL
RA11 1 @ 2 0_0402_5% DVDD_IO
RA43 1 @ 2 0_0603_5%
+5VS 1 1

CA11

CA12
0.1u_0201_10V6K
CA1 2
RA7 1 @ 2 0_0603_5% +5VA

RA10 1 @ 2 0_0603_5% +5VD 1 Close to Pin28 Close to Pin24


D Close to Pin3 D

Close to Pin7
DA1
2
44 BEEP#
0.1u_0201_10V6K CA16 close to Pin18

0.1u_0201_10V6K

4.7U_0402_6.3V6M
1 PC_BEEP1 CA2 1 2 PC_BEEP
2 1 CA17 close to Pin2
Close to Pin27

1
3
8 PCH_BEEP
RA14
BAT54CW_SOT323-3 10K_0402_5% 1 2
change the Codec PN to CX11802-33Z,, symbol check ok

CD@
0.1u_0201_10V6K

1U_0402_6.3V6K
CA3

CA4
2 1
UA1

0.1u_0201_10V6K

2.2U_0402_6.3V6M
2

HDA_RST_AUDIO# FILT_1.8V 2 1
9 3
8 HDA_RST_AUDIO# RESET# FILT_1.8V 7 DVDD_IO 1 2
VDD_IO 2

CA7

CA8
HDA_BITCLK_AUDIO 5 VDDO_3.3 18 +3.3VD 1 2

CA5

CA6
8 HDA_BITCLK_AUDIO BIT_CLK DVDD_3.3
HDA_SYNC_AUDIO 8 27 AVDD_3.3
8 HDA_SYNC_AUDIO SYNC AVDD_3.3 29 VREF_1.65V
33_0402_5% 1 RA16 2 SDATA_IN 6 VREF_1.65V 28 +5VA
8 HDA_SDIN0 HDA_SDOUT_AUDIO 4 SDATA_IN AVDD_5V

0.1u_0201_10V6K

1U_0402_6.3V6K
8 HDA_SDOUT_AUDIO SDATA_OUT
CX20751-11Z MICBIASB 2 1
+3.3VD

PC_BEEP 10 12 SPK_L+
SPKR_MUTE# 39 PC_BEEP LEFT+ 14 SPK_L-
SPKR_MUTE# LEFT- DA2

4LINE_B_R
SPK_R+ 1 2

3LINE_B_L
JSENSE 38 17 BAT54AW_SOT323-3

CA9

CA10
JSENSE RIGHT+ SPK_R-

1
2

37 15 @
GPIO1/PORTC_R_MIC RIGHT-

1
RA15
5.11K_0402_1% 36 35 RA42 RA41
33_0402_5% 1 RA18 2 DMIC_CLK_R 40 MUSIC_REQ/GPIO0/PORTC_L_MIC MICBIASC 34
31,33 DMIC_CLK DMIC_DATA_R DMIC_CLK/MUSIC_REQ/GPIO0 MICBIASB
MICBIASB 0_0402_5% 0_0402_5% Close to Pin29
0_0402_5% 1 @ 2 1 @ @ RPA2
31,33 DMIC_DATA DMIC_DAT/GPIO1
1

RA19 33 LINE_B_R
PORTB_R_LINE 100_0404_4P2R_1%

2
PLUG_IN RA17 1 2 JSENSE 0.1u_0201_10V6K 32 LINE_B_L
39.2K_0402_1% +5VD 1 2 11 PORTB_L_LINE
CLASS-D_REF

1
2
CA13 30 PORTD_A_MIC
C PORTD_A_MIC C
RA36 1 2 13 31 PORTD_B_MIC
20K_0402_1% 16 LPWR_5.0 PORTD_B_MIC
RPWR_5.0 RING2_CONN

1
1
25

3K_0402_1%
3K_0402_1%
HGNDA RING3_CONN 1 1
CA14 1 2 1U_0402_6.3V6K 19 26

RA38
RA37
20 FLY_P HGNDB CA35 CA36
FLY_N 24 AVDD_HP 4.7U_0603_10V6-K 4.7U_0603_10V6-K
CA17 1 2 2.2U_0402_6.3V6M 21 AVDD_HP 2 2 RPA3
AVEE

2
HPOUT_R

2
23 1 4 HP_OUTR
41 PORTA_R 22 HPOUT_L 2 3 HP_OUTL
GND PORTA_L
82.5_0404_4P2R_1%

+5VD CX11802-33Z QFN LOW POWER CODEC


RPA1
CD@

CD@

PORTD_A_MIC 2 3 CA39 1 2 2.2U_0402_6.3V6M RING3_CONN


PORTD_B_MIC 1 4 CA40 1 2 2.2U_0402_6.3V6M RING2_CONN
0.1u_0201_10V6K
0.1u_0201_10V6K
4.7U_0603_10V6-K

4.7U_0603_10V6-K

1 1 2 2 RA1 1 @ 2 0_0402_5%
100_0404_4P2R_1%
RA4 1 EMC@ 2 0_0402_5%
2 2 1 1 RA6 1 @ 2 0_0402_5%
CA15

CA16

CA19
CA18

RA9 1 EMC@ 2 0_0402_5%


JSPK1
RA12 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA25 SPK_R+ RA26 EMC@1 2 PBY160808T-221Y-N_2P SPK_R+_CONN 1
15_0402_5% 1 CD@ 2 RA29 SPK_R- RA31 EMC@1 2 PBY160808T-221Y-N_2P SPK_R-_CONN 2 1
RA13 1 @ 2 0_0402_5% 15_0402_5% 1 CD@ 2 RA32 SPK_L+ RA30 EMC@1 2 PBY160808T-221Y-N_2P SPK_L+_CONN 3 2
1 2 SPK_L- RA34 EMC@1 2 PBY160808T-221Y-N_2P SPK_L-_CONN 4 3
Close to Pin11,13,16 15_0402_5% CD@ RA33
4
5
6 GND1

EMC@

EMC@

EMC@
EMC@
GND GNDA

CD@

CD@

CD@

CD@
GND2

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

220P_0201_25V7-K

470P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K
470P_0201_50V7-K
+3.3VD

Use 250mils wide trace bridging 2 2 2 2 1 1 1 1 ACES_88231-04001


AGND and DGND at codec ME@

RA24 1 @ 2 1 1 1 1 2 2 2 2

CA31

CA32

CA34
CA33
B B
1

0_0402_5%

CA27

CA28

CA29

CA30
RA28
47K_0402_5%
RB751V-40_SOD323-2 @
HDA_RST_AUDIO# DA3 1 2 @
2

SPKR_MUTE#
RB751V-40_SOD323-2
EC_MUTE# DA4 1 2 @
44 EC_MUTE#

Audio Jack HP_OUTR


HP_OUTL
RA45 1
RA46 1
@
@
2 0_0402_5%
2 0_0402_5%
HP_OUTR_R
HP_OUTL_R
RA35 1 @ 2
0_0402_5% RING3_CONN

RING2_CONN JHP1
RING2_CONN 3
HP_OUTL_R G/M
RA47 1 @ 2 @ 1 2 CA41 HP_OUTL_R 1
HP_OUTR_R 0_0402_5% L/R
470P_0201_50V7-K PLUG_IN 5
PLUG_IN 6 5
6
RA48 1 @ 2 @ 1 2 CA42 HP_OUTR_R 2
AZ5725-01F.R7GR_DFN1006P2X2
AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2
AZ5123-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2
0_0402_5% R/L
470P_0201_50V7-K
RING3_CONN
1
1

1
1

1
DA5 DA6 DA7 DA8 DA9 4
DMIC_CLK HDA_RST_AUDIO# M/G
1
1
1

1
1

1
CA43 7

100P_0201_25V8J
100P_0201_25V8J
HDA_SYNC_AUDIO 1000P_0402_50V7K MS
DMIC_DATA 1 1
EMC@ SINGA_2SJ3095-091111F
HDA_SDOUT_AUDIO 2 ME@
EMC_NS@
EMC_NS@

2
2
2

RA27 1 EMC@ 2 HDA_BITCLK_AUDIO 2 2

CA44
CA45
100P_0201_25V8J
100P_0201_25V8J

2
2
2

1 1 27_0402_5%
HDA_SDIN0
A A
EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
EMC_NS@

EMC_NS@
EMC_NS@

2 2
FOR ESD Close to Connector
EMC@

EMC@
CA38
CA37

22P_0201_25V8
22P_0201_25V8
68P_0402_50V8J

33P_0201_50V8-J

33P_0201_50V8-J

1 1 1 1 1

2 2 2 2 2
For EMI
CA22

CA24

CA25

CA26
CA23

Security Classification LC Future Center Secret Data Title


For EMI Issued Date 2015/08/20 Deciphered Date 2016/08/20 Codec_CX11802 & Audio jack
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 43 of 60


5 4 3 2 1
5 4 3 2 1

For EMI RE1 1 @ 2 0_0603_5%


For ESD +3VL V20B+
PLT_RST# CLK_PCI_EC RE2 1 2 10_0402_5%
EMC@

1
1 1 RE3 1 @ 2 0_0603_5%
CE1 CE2 Close EC +3VALW
RE261
220P_0201_25V7-K 10P_0201_50V8F 470K_0402_5%
+3VL_EC +3VL_EC +3VL_EC_R
EMC@ EMC@ @
2 2 CE3 1 2 VCOREVCC

2
LE1 1 @ 2 0_0603_5% B+_Track
0.1u_0201_10V6K +3VL_EC All capacitors close to EC

1
CD@
1 1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 @1 1 @ 1 CE4 CE5 +3VL_EC R260
0.1u_0201_10V6K 1000P_0201_50V7-K 47K_0402_5%
+3VS +3VL_EC_R @
2 2

2
D 2 2 2 2 2 2 EC_AGND D

1
Change RE6 to 0ohm jump LE2 1 @ 2 0_0603_5%

CE10

CE11
RE5

CE6

CE7

CE8

CE9
RE6 1 @ 2 0_0402_5% 10K_0402_5%
EC_AGND

2
LAN_WAKE#
minimum trace width 12 mil LAN_WAKE# 37,40

114
121
127
12

11

26
50
92

74
3
UE1
+3VS

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VBAT

VSTBY(PLL)
VCORE
EC_FAN_SPEED RE10 1 2 10K_0402_5%
EC_FAN_PWM RE11 1 @ 2 10K_0402_5%
RE56 2 @ 1 0_0402_5% 4 24 PWR_LED#
7 KBRST# 2 1 0_0402_5% 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED# 45 LPC_FRAME# 1 2 10K_0402_5%
RE59 @ RE7 @
+3VL_EC 7,32 SERIRQ LPC_FRAME#_EC 6 SERIRQ/GPM6 PWM1/GPA1 BATT_CHG_LED# 45
RE60 1 @ 2 0_0402_5% 28
7,32 LPC_FRAME# 1 2 0_0402_5% LPC_AD3_EC 7 LFRAME#/GPM5 PWM2/GPA2 29 EC_VCCST_PWRGD BATT_LOW_LED# 45 1 2 100K_0402_5%
RE61 @ ENBKL RE9 @
7,32 LPC_AD3 LPC_AD2_EC LAD3/GPM3 PWM3/GPA3 EC_VCCST_PWRGD 11
DE1 1 2 @ RE62 1 @ 2 0_0402_5% 8 PWM 30
7,32 LPC_AD2 LPC_AD1_EC LAD2/GPM2 PWM4/GPA4 EC_FAN_PWM SYS_PWROK 11 CPU_VR_READY
RE63 1 @ 2 0_0402_5% 9 31 RE270 1 2 10K_0402_5%
7,32 LPC_AD1 1 2 0_0402_5% LPC_AD0_EC 10 LAD1/GPM1 PWM5/GPA5 32 EC_FAN_PWM 39
RB751V-40_SOD323-2 RE64 @
7,32 LPC_AD0 CLK_PCI_EC LAD0/GPM0 PWM6/SSCK/GPA6 EC_VCCST_EN_R BEEP# 43 EC_VCCST_EN EC_CMOS_ON#
7 CLK_PCI_EC
13
LPCCLK/GPM4 LPC PWM7/RIG1#/GPA7
34
LAN_WAKE#
RE54 1 @ 2
EC_VCCST_EN 13
RE275 1 @ 2 10K_0402_5%
1 2 WRST# 14 120 0_0402_5%
RE8 15 WRST# TMRI0/GPC4 124 SUSP#
1 9 EC_SMI# EC_RX ECSMI#/GPD4 TMRI1/GPC6 SUSP# 46
100K_0402_5% 16
CE12 40 EC_RX EC_TX 17 PWUREQ#/BBO/SMCLK2ALT/GPC7 66 +5VS +3VS
1U_0402_6.3V6K 40 EC_TX PLT_RST# LPCPD#/GPE6 ADC0/GPI0 NTC_V1 39
22 67 NTC_V2 39
2 11,32,37,40 PLT_RST# 23 LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
4 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 BATT_TEMP 52,53

1
2
126 ADC 69
GA20/GPB5 ADC3/GPI3 PM_SLP_SUS# 11
70
IT8586E/AX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72 B+_Track
CPU_VR_READY
ADP_I 53
59
+3VL_EC
RE52
0_0402_5%
@
@
RE51
0_0402_5%

LQFP-128L ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 1 TE1 @

2
1
KSI[0..7] KSI0 58
45 KSI[0..7] KSI0/STB#

1
KSI1 59 78
KSO[0..17] KSI1/AFD# DAC2/TACH0B/GPJ2 SUSWARN# 11 TP_CLK
KSI2 60 79 RE65 RE12 2 1 4.7K_0402_5%
45 KSO[0..17] KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC SUSACK# 11
C KSI3 61
KSI3/SLIN# DAC DAC4/DCD0#/GPJ4
80 100K_0402_5%
TP_DATA
C
KSI4 62 81 RE13 2 1 4.7K_0402_5%
KSI4 DAC5/RIG0#/GPJ5 ENBKL 33
KSI5 63
KSI5

2
+3VL_EC KSI6 64 85 EC_ON_GPIO 0_0402_5% 1 @ 2 RE57
65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 EC_ON 39,54,55
KSI7 +5VALW
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK3 PBTN_OUT# 11
KSO0 36 87
EC_SMB_CK1 1 37 KSO0/PD0 GPF2 88 EC_SMB_DA3 EC_SMB_CK3 55
RPE2
EC_SMB_DA1 EC_SMB_DA1
PAD @
IT1
KSO1
KSO1/PD1 Int. K/B PS2 GPF3 TP_CLK EC_SMB_DA3 55 USB_ON#
2 3 PAD 1 @ KSO2 38 Matrix 89 RE15 1 2 100K_0402_5%
EC_SMB_CK1 IT2 KSO2/PD2 PS2CLK2/GPF4 TP_DATA TP_CLK 45 +3VALW +3VL_EC
1 4 PAD 1 @ KSO3 39 90 For PMIC
1 IT3 40 KSO3/PD3 PS2DAT2/GPF5 TP_DATA 45
PAD @ KSO4
IT4 KSO4/PD4
2.2K_0404_4P2R_5% PAD 1 @ KSO5 41 EXTERNAL SERIAL FLASH 96 +3VL_EC
IT5 KSO5/PD5 GPH3/ID3 CAPS_LED# 45

1
KSO6 42 97
KSO6/PD6 GPH4/ID4 PCH_PWR_EN 46,55
KSO7 43 98 RE273 RE274
KSO7/PD7 GPH5/ID5 EC_BKL_EN 45
KSO8 44 99 0_0402_5% @ 0_0402_5%
+3VS KSO8/ACK# GPH6/ID6 PCH_PWROK 11
KSI7 PAD 1 @ KSO9 45 @ SUSP# RE18 1 @ 2 100K_0402_5%
IT6 KSO9/BUSY EC_SPI_CS0#
KSI6 PAD 1 @ KSO10 46 101
IT7 KSO10/PE NC1

2
RPE3 WRST# PAD 1 @ KSO11 51 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
EC_SMB_CK2 IT8 KSO11/ERR# NC2 EC_SPI_SO
1 4
EC_SMB_DA2
KSO12 52
KSO12/SLCT SPI Flash ROM NC3
103
EC_SPI_CLK EC_SMB_DA3
RPE4
SYSON_R
2 3 KSO13 53 105 1 4 RE21 1 2 100K_0402_5%
KSO13 NC4 EC_SMB_CK3
For factory EC flash KSO14 54
KSO14
2 3
EC_VCCST_EN
2.2K_0404_4P2R_5% KSO15 55 RE269 1 @ 2 100K_0402_5%
KSO16 56 KSO15 108 ACIN# 2.2K_0404_4P2R_5%
57 KSO16/SMOSI/GPC3 AC_IN# 109 LID_SW# EC_VCCIO_EN RE268 1 2 100K_0402_5%
KSO17
KSO17/SMISO/GPC5 UART LID_SW# LID_SW# 45
@

ON/OFF 110 82 EC_FAN_ANTI_R RE53 1 @ 2 0_0402_5%


EC_ON 45 ON/OFF PWRSW# EGAD/GPE1 EC_FAN_ANTI 39
RE58 2 @ 1 0_0402_5% 111 SM Bus 83 VDDQ_PGOOD 55
EC_SMB_CK1 115 XLP_OUT EGCS#/GPE2 84 EC_VPP_PWREN Add to fix Reset&PWRGD test fail issue
52,53 EC_SMB_CK1 EC_SMB_DA1 116 SMCLK1/GPC1 EGCLK/GPE3 EC_VPP_PWREN 55
52,53 EC_SMB_DA1 PECI_EC SMDAT1/GPC2 VDDQ_PGOOD CE51 1
4 H_PECI RE24 1 2 43_0402_5% 117 GPIO 77 2 0.01U_0201_10V6K
118 SMCLK2/PECI/GPF6 GPJ1 100 EC_CMOS_ON# 33
GPG2
37 LAN_PWR_ON# EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 106
7,39 EC_SMB_CK2 EC_SMB_DA2 95 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 EC_MUTE# 43 PM_SLP_S4#
104 CE50 1 2 EMC_NS@ 1000P_0201_50V7-K
+3VL 7,39 EC_SMB_DA2 CTX1/SOUT1/GPH2/SMDAT3/ID2 DSR0#/GPG6 107 SYSON_R ME_FLASH 8
RE271 1 @ 2 0_0402_5% SYSON
DTR1#/SBUSY/GPG1/ID7 119 SYSON 55
BKOFF#
CRX0/GPC0 123 BKOFF# 33 EC_VCCIO_EN PM_SLP_S3#
RE55 2 @ 1 0_0402_5% CE21 1 2 EMC_NS@ 1000P_0201_50V7-K
1 2 0_0402_5% 112 CTX0/TMA0/GPB2 18 EC_VCCIO_EN 13
RE27 @
125 VSTBY0 RI1#/GPD0 PM_SLP_S3# 11,13
RE272 1 @ 2 0_0402_5% 21 PM_SLP_S4# 11
B 57,59 EC_VR_ON GPE4 RI2#/GPD1 76 B
WAKE UP NOVO# 45 SYSON CE13 1 2 EMC_NS@ 1000P_0201_50V7-K
PM_SLP_S3# DE2 1 2 TACH2/GPJ0 48
TACH1A/TMA1/GPD7 47 EC_FAN_SPEED EC_TS_ON 33
@ RB751V-40_SOD323-2 EC_FAN_SPEED 39
USB_ON# 33 TACH0A/GPD6 19 1 TE3 @
41,45 USB_ON# GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 EMC Request

2
35 GPIO 20
11 DPWROK_EC 93 RTS1#/GPE5 L80LLAT/GPE7 NUM_LED# 45
11 EC_RSMRST# CLKRUN#/GPH0/ID0

PCIE_WAKE# 2 DE3
11,37,40 PCIE_WAKE# CK32KE/GPJ7

1
128 Clock RB751V-40_SOD323-2
+3VL 11 AC_PRESENT CK32K/GPJ6 @
PM_SLP_S4#

RE34 1 @ 2 H_PROCHOT# 4,55


RE35 1 @ 2 10K_0402_5% ON/OFF 53,59 VR_HOT# 0_0402_5%
AVSS
VSS3
VSS4
VSS5
VSS6
VSS1

VSS2

EC_RTC_RST# 10

1
RE36 1 @ 2 10K_0402_5% BKOFF# 1
IT8586E-AX_LQFP128_14X14 RE267 CE14
49
91
113
122

75
1

27

RE38 2 1 100K_0402_5% LID_SW# 100_0402_5% 47P_0201_25V8-J


EMC_NS@
2

1
QE3 D

1 2
EC_RTCRST#_ON 2
RE40 1 2 10K_0402_5% BKOFF# QE1 D G
EC_AGND H_PROCHOT#_EC 2 +3VL
G @ S 2N7002KW_SOT323-3

3
1
2N7002KW_SOT323-3 S RE50
for EC version update to EX, manual modify PN to FX

2
100K_0402_5%
RE42 @
100K_0402_5%

2
1
+3VL +3VS ACIN# RE262 1 @ 2 0_0402_5%
PECI_EC 11 ACIN#
EMC_NS@ CE15 1 2 47P_0201_25V8-J
+3VL_EC
BATT_TEMP

1
EMC_NS@ CE16 1 2 100P_0201_25V8J 1 D QE2
A GPG2 RE43 2 @ 1 10K_0402_5% CE19 2 A
ACIN 53
ACIN# EMC_NS@ CE17 1 2 100P_0201_25V8J 0.1u_0201_10V6K G
GPG2 RE44 2 1 10K_0402_5% EC_SPI_CS0# RE45 2 @ 1 0_0402_5% SPI_CS0#
SPI_CS0# 7 NOVO# ON/OFF @ CE18 1 2 1U_0402_6.3V6K 2 S 2N7002KW_SOT323-3

3
GPG2 RE46 2 @ 1 10K_0402_5% @
EC_SPI_SI RE47 2 @ 1 0_0402_5% SPI_SI
SPI_SI 7
when mirror, GPG2 pull high
EC_SPI_SO SPI_SO
when no mirror, GPG2 pull low RE48 2 @ 1 0_0402_5%
SPI_SO 7 1
CE48
0.01U_0201_10V6K Title
EC_SPI_CLK RE49 2 @ 1 0_0402_5% SPI_CLK EMC_NS@
Security Classification LC Future Center Secret Data
SPI_CLK 7 2
Issued Date 2015/08/20 Deciphered Date 2016/08/20 EC ITE8586LQFP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 44 of 60


5 4 3 2 1
5 4 3 2 1

ON/OFF switch Novo button

+3VL +3VALW NOVO_BTN#

ON/OFFBTN#

1
R82 R83

AZ5123-01F.R7GR_DFN1006P2X2
1

3
100K_0402_5% 100K_0402_5% SW2 D24

1
1
@ D25 AZ5123-01F.R7GR_DFN1006P2X2
R261 1 @ 2 EVQP7L01K SPST EMC@

1
1

1
0_0402_5% SW1
SKRBAAE010_4P

4
14@

2
2
NOVO# D15 2

2
44 NOVO#

4
EMC_14@
NOVO_BTN#

2
1

ON/OFF R85 1 @ 2 0_0402_5% 3 @


D D
BAT54CW_SOT323-3

+3VALW +3VL
LID switch
ON/OFFBTN#

AZ5123-01F.R7GR_DFN1006P2X2
1

3
R111 R114

1
100K_0402_5% 100K_0402_5% D26
@ 1

1
SW3 C1104
1

1
SKRBAAE010_4P U14 100P_0201_25V8J
ON/OFFBTN# R119 1 @ 2 0_0402_5% ON/OFF 15@ 1
ON/OFF 44 GND 2
1 LID_SW#
3

2
C1105
OUTPUT LID_SW# 44

4
J5 1 2 @ EMC_15@ 0.01U_0201_10V6K

2
SHORT PADS R264 1 @ 2 2 +VCC_LID 2
+3VL VCC
0_0402_5%
J6 1 2 @ AH9247-W-7_SC59-3

SHORT PADS

K/B Connector KSI[0..7]


KSI[0..7] 44
JKB1
KB Backlight Connector
KSO[0..17]
KSO[0..17] 44 KB_P32 32 33
KB_P31 32 GND1 +5VS
31 34
R279 1 15@ 2 0_0402_5% NUM_LED#_R 30 31 GND2
44 NUM_LED# PWR_NUM_LED 30 +5VALW
EMC_NS@ +3VS R90 1 15@ 2 300_0402_5% 29 +VCC_KB_LED
PWR_CAPS_LED KSO17 R281 1 15@ 2 0_0402_5% KSO17_R 28 29
C133 1 2 100P_0201_25V8J KSO16_R 28 Q31
KSO16 R280 1 15@ 2 0_0402_5% 27

1
27 R265 LP2301ALT1G_SOT23-3
PWR_NUM_LED C134 1 2 100P_0201_25V8J KSI1 26 10K_0402_5%
26 KBL@
KSI7 25 KBL@ 3 1

D
KSI6 24 25
EMC_NS@ 24
KSO9 23
KSI4 22 23 1 1

2
22 R266 C1106 C1107

G
KSI5 21

2
21 1 2 10U_0603_6.3V6M 0.1u_0201_10V6K
R291 1 14@ 2 0_0402_5% KB_P32 KSO0 20
KSO12 20 KBL@ KBL@
KSI2 19 2 2
EMC@ 19 100K_0402_5% 1
CAPS_LED# 1 2 100P_0201_25V8J KSI3 18
C117 KSO14 R292 1 15@ 2 0_0402_5% 18 KBL@ C1108
KSO5 17 0.01U_0201_10V6K
NUM_LED#_R KSO1 16 17
C C118 1 2 100P_0201_25V8J 16 KBL@ C
KSI0 15 2
KSO2 14 15
EMC_15@ 14
KB_P31 KSO4 13
KSI2 R289 1 14@ 2 0_0402_5% 13
KSO7 12
KSO8 11 12

1
KSI5 R290 1 15@ 2 0_0402_5% 11 D
KSO6 10 EC_BKL_EN 2
10 Q32
CAPS_LED# NUM_LED#_R KSO3 9 44 EC_BKL_EN
9 G 2N7002KW_SOT323-3
KSO12 8
8 KBL@
KSO13 7 S
KSO14 6 7 1

3
6 C1109
KSO11 5 0.1u_0201_10V6K
KSO10 4 5
1

4 KBL@
KSO15 3 2
D22 D23 CAPS_LED# 3 JKBL1
1

2 +VCC_KB_LED 1
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 44 CAPS_LED# PWR_CAPS_LED 2
R84 1 2 1 2 1
EMC@ EMC_15@ +3VS 1
300_0402_5% 3 2
CVILU_CF32321D0RONH 4 3
ME@ 4
2

1
C1110 5
GND1
2

0.1u_0201_10V6K 6
@ GND2
2
For EMC HIGHS_FC1AF040-1201H
ME@

+USB_VCCB JUSB3
USB DB Connector TP/B Connector
12
11 12 14
10 11 GND2 +5VS TP_PWR
Right Side USB2.0 Port X 2 (USB/B) R67 1 @ 2 0_0402_5% USB20_P2_CONN
9
8
10
9 GND1
13
R160 1 @ 2
9 USB20_P2 1 2 0_0402_5% USB20_N2_CONN 7 8 +3VS
R66 @ 0_0402_5%
+5VALW +USB_VCCB 9 USB20_N2 6 7 JTP1
U3 R254 1 @ 2 0_0402_5% USB20_P3_CONN 5 6 R141 1 @ 2 0_0402_5% 1
5 1 9 USB20_P3 2 0_0402_5% USB20_N3_CONN 4 5 TP_CLK 1
R255 1 @ 2
IN OUT 9 USB20_N3 3 4 44 TP_CLK TP_DATA 3 2
1 PWR_LED# 3 44 TP_DATA 3

0.1u_0201_10V6K
C141 2 2 1 4
GND 44 PWR_LED# 2 4

100P_0201_25V8J
100P_0201_25V8J
1U_0402_6.3V6K 1 1 1

EMC_NS@
EMC_NS@
USB_OC2# +5VALW 1
4 3 5
2 41,44 USB_ON# ENB OCB USB_OC2# 9 GND1
ACES_50506-01201-AT1 6
SY6288D20AAC_SOT23-5 ME@ TP_CLK 2 GND2

C114
1 TP_DATA 2 2
C142 HIGHS_FC1AF040-1201H

C116
C115
Low Active 2A 1000P_0201_50V7-K ME@

2
EMC_NS@
B 2 B
DT1

EMC_NS@

L14 EMC_NS@ JUSB4


USB20_P2 1 2 USB20_P2_CONN 22
1 2 21 GND2
R284 1 @ 2 0_0402_5% USB30_RX_R_P2 20 GND1
USB20_N2 4 3 USB20_N2_CONN 9 USB30_RX_P2 2 0_0402_5% USB30_RX_R_N2 20
R283 1 @ 19
4 3 9 USB30_RX_N2 18 19 AZC199-02S.R7G_SOT23-3
2 0_0402_5% USB30_TX_R_P2 18

1
EXC24CH900U_4P R285 1 @ 17 For EMC
9 USB30_TX_P2 2 0_0402_5% USB30_TX_R_N2 17
R286 1 @ 16
9 USB30_TX_N2 15 16
+3VS_DB 15
L17 EMC_NS@ 14
USB20_P3 USB20_P3_CONN +USB_VCCB 14
1 2 13
1 2 12 13
11 12
USB20_N3 4 3 USB20_N3_CONN 10 11
4 3 9 10
EXC24CH900U_4P USB20_P2_CONN 8 9
USB20_N2_CONN 7 8
6 7
L18 EMC_NS@ USB20_P3_CONN 5 6
USB30_RX_P2 1 2 USB30_RX_R_P2 USB20_N3_CONN 4 5
1 2 3 4
PWR_LED# 2 3
USB30_RX_N2 4 3 USB30_RX_R_N2 1 2
4 3 +5VALW 1
EXC24CH900U_4P HIGHS_FC5AF201-1151H
ME@

L19 EMC_NS@ +3VS +3VS_DB


USB30_TX_N2 1 2 USB30_TX_R_N2
1 2 +3VALW R295 1 @ 2 0_0402_5%
USB30_TX_P2 4 3 USB30_TX_R_P2
4 3 R298 1 510Z@ 2 0_0402_5%
EXC24CH900U_4P

BATT_LOW_LED# LED2 1 2 R143 1 2 470_0402_5%


44 BATT_LOW_LED# +3VALW
L-C192JFCT-LCFC_SUPER_AMBER
1

D18
1

A AZ5123-01F.R7GR_DFN1006P2X2 A
EMC_NS@
2
2

BATT_CHG_LED# LED3 1 2 R144 1 2 1.5K_0402_5%


44 BATT_CHG_LED# +5VALW
L-C192WDT-LCFC_WHITE
1

D19
1

AZ5725-01F.R7GR_DFN1006P2X2
EMC_NS@ Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 KBD/PWR/IO/LED/TP Conn.
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
2

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 45 of 60
5 4 3 2 1
A B C D E

Load Switch
+5VALW To +5VS +3VS, C173 --> 2.74ms
+3VALW To +3VS +5VS, C176 --> 2.03ms
VIN 5V and 3.3V (VBIAS=5V), IMAX(per channel)=6A, Rds=16mohm Need Short
R64 1 @ 2 0_0402_5% 3VSON
+5VALW U13 +5VS
1 14 J12 @
2 IN1_1 OUT1_2 13 +5VS_LS 1 2
1 IN1_2 OUT1_1 1 2 1

1 5VSON 3 12 C176 1 2 1000P_0201_50V7-K JUMP_43X118 1


SUSP# R27 1 @ 2 0_0402_5% 5VSON EN1 CT1 C174
C177 4 11 0.1u_0201_10V6K
+5VALW VBIAS GND
1U_0402_6.3V6K @
+3VALW 2 3VSON 5 10 C173 1 2 2200P_0402_25V7-K 2 +3VS
1 1 EN2 CT2 J11 @
C180 C179 6 9 +3VS_LS 1 2
1U_0402_6.3V6K 1U_0402_6.3V6K 7 IN2_1 OUT2_2 8 1 2
2 2 IN2_2 OUT2_1 JUMP_43X118
1 1
15 C175
GPAD 0.1u_0201_10V6K
C178 Need Short
1U_0402_6.3V6K G5016KD1U_TDFN14_2X3 @
2 @ 2
Change the main source to SA000067600 (GMT) 7/16

2 2
+3VALW Need short +3VALW_PCH
+5VALW
J7 @
1 2
1 2
1

JUMP_43X79
R155 1
100K_0402_5% C1103
@ 22U_0603_6.3V6-M LP2301ALT1G_SOT23-3 Id=3.2A
2

@
PCH_PWR_EN#_R R158 1 @ 2 100K_0402_5% PCH_PWR_EN# 2 Q29 3 1 @

D
1
1

Q30 D C130

G
2
PCH_PWR_EN 2 0.01U_0201_10V6K
44,55 PCH_PWR_EN G @
2
@ S 2N7002KW_SOT323-3
3

PCH_PWR_EN#_R
1

R162 1
100K_0402_5% C131
@ 0.1u_0201_10V6K
2

@
2
1

R87
100K_0402_5%
@
2

3 3

+5VLP +5VALW
For DisCharge
1

R156 R157 +0.6VS +2.5V_DDR


100K_0402_5% 100K_0402_5%
@

1
1
2

R159 R278
SUSP 47_0603_5% 200_0402_5%
34 SUSP
@ @

2
2
1

1
1

Q10 D D Q11 D Q33


2 2 SUSP 2 SUSP
44 SUSP# G G G

S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3 S 2N7002KW_SOT323-3


3

3
3

@ @

4 4
08/29: Need double check enable signal and the resistance

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 46 of 60
A B C D E
5 4 3 2 1

B2 A2
D
+3VLP PCH_PWR_EN# 2 D

Q25,+3V_PCH

V
V
AC A1
MODE VIN
A2 A4 B5

V V
3 +3V_PCH
PU301 PU904

V
B+
+3VALW
BATT BATT V 1
DPWROK_EC
V
MODE

V V V
B1
4
PCH_RSMRST#
EC 14
PM_DRAM_PWRGD
5 PBTN_OUT#

V
EC_ON PM_SLP_S3# PCH 15
A3 B4
PM_SLP_S4# H_CPUPWRGD CPU

V V
PM_SLP_S5#
PM_SLP_SUS# 6
CPU_PLTRST# 16

V
12
PCH_PWROK

V V
C C

B3 13
SYS_PWROK

V
ON/OFF V
NOVO

NVDD_PWR_EN
(DIS)
Vb
+VGA_CORE
+1.35V

V
11 VR_REDY SYSON 7 PU801
PU501

V
DGPU_PWROK
DGPU_PWR_EN
10 Va (DIS)
+1.5VS_VGA

V
PU901 VR_ON Q31

V
PU601
V

+CPU_CORE

V
+5VS

B B
Q32 +1.05VSP_VGA

V
SUSP#,SUSP +3VS PU702
9 VGA

V
PU602

V
+1.5VS +3VS_VGA

V
Q27
PU502

V
+0.675V
8
SUS_VCCP PU701
V
+1.05VS

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 Power sequence block
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 47 of 60
5 4 3 2 1
5 4 3 2 1

ZZZ1 @ ZZZ1 @ ZZZ1 @ ZZZ1 @ ZZZ1 @ ZZZ1 @ UC1 80710@ UC1 80310@ UC1 80410@

PCB PN PCB PN PCB PN PCB PN PCB PN PCB PN KBL-U CPU KBL-U CPU KBL-U CPU
DAZ11500100 DAZ11600100 DAZ11500200 DAZ11600200 DAZ11300100 DAZ11300200 SA000080710 SA000080310 SA000080410
PCB_MB CPU

UL1 8111H@ UV1 N16SGTR@ UV1 N16VGMR1@ ZZZ3 S4GX4@ ZZZ3 H4GX4@ ZZZ3 M4GX4@ ZZZ3 S4GX8@ ZZZ3 H4GX8@ ZZZ3 M4GX8@

D D

RTL8111H-CG N16S-GTR GPU N16V-GMR1 GPU Samsung Hynix Micron Samsung Hynix Micron
SA000074W00 SA00007QA10 SA00007QX00 X7612912001 X7612712003 X7612712002 X7612712001 X7612712008 X7612712007
LAN Chip GPU
VRAM X76 BOM

ZZZ2 @ ZZZ2 @ UV5 S4G_SR@ UV6 S4G_SR@ UV7 S4G_SR@ UV8 S4G_SR@ RV159 S4G_SR@

Samsung Micron K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A 10K_0402_1%


X76XXXXXXXX X76XXXXXXXX SA000063F20 SA000063F20 SA000063F20 SA000063F20 SD03410028J

2133MT/s DRAM X76 BOM VRAM_Samsung 4GX4

UD1 @ UD2 @ UD3 @ UD4 @ RC1634 @ RC1635 @ RC1640 @ UV5 H4G_SR@ UV6 H4G_SR@ UV7 H4G_SR@ UV8 H4G_SR@ RV159 H4G_SR@

K4A8G165WB-BCPB K4A8G165WB-BCPB K4A8G165WB-BCPB K4A8G165WB-BCPB 10K_0402_5% 10K_0402_5% 10K_0402_5% H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C 15K_0402_1%
SA00007DA10 SA00007DA10 SA00007DA10 SA00007DA10 SD02810028J SD02810028J SD02810028J SA00007DU10 SA00007DU10 SA00007DU10 SA00007DU10 SD03415028J

2133MT/s DRAM_Samsung 4G VRAM_Hynix 4GX4

UV5 M4G_SR@ UV6 M4G_SR@ UV7 M4G_SR@ UV8 M4G_SR@ RV159 M4G_SR@

C C

MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N 34.8K_0402_1%


SA00007QJ00 SA00007QJ00 SA00007QJ00 SA00007QJ00 SD03434828J

2133MT/s DRAM_Hynix 4G VRAM_Micron 4GX4

UD1 @ UD2 @ UD3 @ UD4 @ RC1631 @ RC1635 @ RC1640 @ UV5 S4G_DR@ UV6 S4G_DR@ UV7 S4G_DR@ UV8 S4G_DR@ RV156 S4G_DR@

MT40A512M16HA-083E:A MT40A512M16HA-083E:A MT40A512M16HA-083E:A MT40A512M16HA-083E:A 10K_0402_5% 10K_0402_5% 10K_0402_5% K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A 45.3K_0402_1%
SA000079F10 SA000079F10 SA000079F10 SA000079F10 SD02810028J SD02810028J SD02810028J SA000063F20 SA000063F20 SA000063F20 SA000063F20 SD03445328J

2133MT/s DRAM_Micron 4G

UV9 S4G_DR@ UV10 S4G_DR@ UV11 S4G_DR@ UV12 S4G_DR@

K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A K4W4G1646E-BC1A


ZZZ2 DRAM_S4G@ ZZZ2 DRAM_M4G@ SA000063F20 SA000063F20 SA000063F20 SA000063F20

VRAM_Samsung 4GX8

Samsung Micron
X7612912002 X7612912003

2400MT/s DRAM X76 BOM UV5 H4G_DR@ UV6 H4G_DR@ UV7 H4G_DR@ UV8 H4G_DR@ RV156 H4G_DR@

B B
UD1 MD_S8Gb@ UD2 MD_S8Gb@ UD3 MD_S8Gb@ UD4 MD_S8Gb@ RC1634 MD_S8Gb@ RC1635 MD_S8Gb@ RC1639 MD_S8Gb@ H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C 34.8K_0402_1%
SA00007DU10 SA00007DU10 SA00007DU10 SA00007DU10 SD03434828J

K4A8G165WB-BCRC K4A8G165WB-BCRC K4A8G165WB-BCRC K4A8G165WB-BCRC 10K_0402_5% 10K_0402_5% 10K_0402_5% UV9 H4G_DR@ UV10 H4G_DR@ UV11 H4G_DR@ UV12 H4G_DR@
SA00007TQ00 SA00007TQ00 SA00007TQ00 SA00007TQ00 SD02810028J SD02810028J SD02810028J

2400MT/s DRAM_Samsung 4G

H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C H5TC4G63CFR-N0C


SA00007DU10 SA00007DU10 SA00007DU10 SA00007DU10

VRAM_Hynix 4GX8

UV5 M4G_DR@ UV6 M4G_DR@ UV7 M4G_DR@ UV8 M4G_DR@ RV156 M4G_DR@

2400MT/s DRAM_Hynix 4G

MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N 15K_0402_1%


SA00007QJ00 SA00007QJ00 SA00007QJ00 SA00007QJ00 SD03415028J
UD1 MD_M8Gb@ UD2 MD_M8Gb@ UD3 MD_M8Gb@ UD4 MD_M8Gb@ RC1631 MD_M8Gb@ RC1635 MD_M8Gb@ RC1639 MD_M8Gb@

UV9 M4G_DR@ UV10 M4G_DR@ UV11 M4G_DR@ UV12 M4G_DR@

MT40A512M16JY-083E:B MT40A512M16JY-083E:B MT40A512M16JY-083E:B MT40A512M16JY-083E:B 10K_0402_5% 10K_0402_5% 10K_0402_5%


SA00007TS00 SA00007TS00 SA00007TS00 SA00007TS00 SD02810028J SD02810028J SD02810028J

2400MT/s DRAM_Micron 4G
MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N MT41J256M16LY-091G:N
SA00007QJ00 SA00007QJ00 SA00007QJ00 SA00007QJ00

A A
VRAM_Micron 4GX8

ZZZ4 HDMI@

HDMI PN
RO00000040J
HDMI Royalty Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 Virtual symbol
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 48 of 60
5 4 3 2 1
5 4 3 2 1

PCB Fedical Mark PAD


FD1 FD2 FD3 FD4 FD5 FD6
NH1 NH2 NH3
HOLEA HOLEA HOLEA

1
D D
1

1
PAD_O2P6X2P5D2P6X2P5N PAD_O2P5X3P0D2P5X3P0N PAD_O2P5X2P9D2P5X2P9N

H1 H3 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
CHASSIS1_GND
PAD_D3P4 PAD_CT7P0B9P0D3P0 PAD_C8P0 PAD_C5P0 PAD_C7P0D3P0

H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
C C
1

1
PAD_CT7P0B9P0D3P0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 pad_ct6p0b7p0d4p0 PAD_ShapeT9P0X8P0CB9P0D3P0 PAD_ShapeT7P5X8P0D3P4 PAD_CT7P0B6P0D3P3 PAD_C3P0D3P0N PAD_C7P0 PAD_C6P0D2P5

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 Hole
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 49 of 60


5 4 3 2 1
5 4 3 2 1

Silergy
PMIC-LV5075AGQV +1.0VALW/6A
D D
Converter
SUSP# EN FOR PCH PGOOD

B+
+5VLP/ 100mA
Silergy
SY8288CRAC +5VALW/6A
Adaptor Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
PAGE 39

ANPEC
+3VLP/ 100mA
Silergy PMIC-LV5075AGQV +1.8VALW/1A
SY8286BRAC
QFN20_3X3 +3VALW/ 5A EN PGOOD
Converter
EC_ON EN FOR SYSTEM PGOOD ALW_PWRGD
C PAGE 39 C

Richtek +1.2V/7A

PMIC-LV5075AGQV
SYSON S5
TI SUSP# S3 Switch Mode +0.6VS/2A

BQ24780SRUYR FOR DDR PGOOD

Battery Charger
Switch Mode
PAGE 46 ANPEC
Richtek PMIC-LV5075AGQV +2.5V/1A
+1.35V/8A
NB685GQ-Z
EN PGOOD
SYSON S5 QFN16_3X3
SMBus
SUSP# S3
B
Switch Mode B
FOR DDR PGOOD

Battery Onsemi CPU Core/23A

polymer NCP81206MNR2G VCCGT/25A


2S1P QFN60_7X7
Switch Mode VCCSA/7A
VR_ON
EN FOR CPU Core PGOOD VGATE
PGOOD_NB

RichTek
A NB681GD-Z VCC_OPC/4.5A A

VIDs
Switch Mode
EC_VR_ON EN FOR GPU VDDC PGOOD

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-Power Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 50 of 60


5 4 3 2 1
5 4 3 2 1

VIN
7A_24VDC_429007.WRML EMC@
HCB2012KF-121T50_0805
JDCIN1 PF101 PL101
1 ADPIN 1 2 APDIN_F 1 2
1 2
GND1 3 EMC@
GND2 4

EMC@
HCB2012KF-121T50_0805
GND3 5

1000P_0201_50V7-K

470P_0201_50V7-K

470P_0201_50V7-K

1000P_0201_50V7-K
PC101

PC102

PC103
PL102
GND4 6 1 2
GND5

2
D 7 D
GND6

PC104
EMC@
1

1
HIGHS_PJSS0026-8B01H
ME@

EMC@ EMC@

+3VL

1
PR1015
1.5K_0402_1%

2
C VCCRTC C

1
PR1016
45.3K_0402_1%
PD101
RTC_VCC

2
2

1 RTC_VCC 20MIL
JRTC1 +3VL 20MIL
3 2 PR101 1 1
2 1 VCCRTC 20MIL
3 2
1K_0603_5%
G1 No charge RTC
2

@ BAT54CW_SOT323-3 4
PC105 G2
1U_0402_6.3V6K ACES_50273-0020N-001
1

ME@

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-DCIN / RTC charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 51 of 60
5 4 3 2 1
5 4 3 2 1

VBAT_F
SUYIN_125022HB008M202ZL VBAT
PF201 EMC@
D JBATT1 D
12A_24V_F1206HB12V024T/M HCB2012KF-121T50_0805
1
BATT+ 2S1P BAT +6V
PL201
1 2 1 2 1 2
2 EC_SMCA
9
10 GND1 3
3
4 EC_SMDA
PR202 1
1
2 100_0402_1%
2
EC_SMB_CK1 44,53
1 2
~ 8.4 V
GND2 4 EC_SMB_DA1 44,53
5 PR201 100_0402_1%
5 6 PL202
6 7 HCB2012KF-121T50_0805
7

2
8
8 EMC@

1
ME@ PC201 PC202
1000P_0201_50V7-K 0.01U_0201_25V6-K

2
Reverse PD201 PD202 EMC@ EMC@

For EMI request


PD201

EMC_NS@

AZC199-02S.R7G_SOT23-3

1 PR209
1 2
+3VALW
100K_0402_1%

PR213
C BATT_TEMP_IN 1 2 C
10K_0402_5%
BATT_TEMP 44,53 A/D
1

PD202
1

EMC_NS@
AZ5215-01F_DFN1006P2E2
2
2

VBAT
SUYIN_125022HB008M202ZL
JBATT2
1
1 2
9 2 3 EC_SMCA
B 10 GND1 3 4 EC_SMDA B
GND2 4 5 BATT_TEMP_IN
5 6
6 7
7 8
8
ME@

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-BATTERY CONN/OTP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 52 of 60
5 4 3 2 1
5 4 3 2 1

AON6414AL_DFN8-5
PQ311 PQ312
AON7408L_DFN8-5 N2
VIN N1 @ PR301
1 1 PJ301 0.01_1206_1%
2 2 JUMP_43X118
5 3 3 5 1 2 1 4
1 2 V20B+

0.1U_0201_25V6-K
2 3

1000P_0201_50V7-K
D D

10U_0603_25V6-M

10U_0603_25V6-M
470P_0201_50V7-K

0.022U_0402_25V7K
4

2
PC312

PC331
1

2
PC301

PC303

PC304
EMC_NS@

EMC_NS@
1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K

1000P_0201_50V7-K
1

1
PC329

PC330

PC317

PC332

PC302

1
PR302

1
4.7_0603_5% EMC_NS@
2

5
0.1U_0201_25V6-K
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

2
EMC_NS@
PC305
1 2
BQ24780_BATDRV 4

2
PC306 AON6764_DFN8-5
PC307 0.1U_0201_25V6-K PQ314

1
1U_0603_25V6K

3
2
1
2
PR303
499K_0402_1% PC308
0.01U_0201_25V6-K

1
VIN BATT+

2
432K and 64.9k change
to 43k and 6.49k.0.1u

BAT54CW_SOT323-3
change to 0.01u

PD302
2

3
decrease ACDET V20B+
deassert time

2200P_0201_25V7-K
VIN

10U_0805_25V6K

10U_0805_25V6K
1
1
1

2
PC310

PC313
4.02K_0603_1%
4.02K_0603_1%

ACN
ACP
PR311
PR310

PC314
1

1
2
1

5
PR314 BQ24780_VDD
2
2

1
C PR313 10_1206_5% C
7.15K_0402_1% 1U_0603_25V6K

ACN
ACP
1 2 43K_0402_1% PC315 EMC@

1
PR315 2 1 780_VCC 28 24 1 2 PQ316
VCC REGN

2
2.2U_0603_10V6-K PC316 4
2 1 ACDET 6 AON7408L_DFN8-5
PC309 ACDET PR316 PC318
25 BST_CHG1 2 2 1
0.01U_0201_25V6-K BTST 2.2_0603_5% PR317

3
2
1
3
BQ24780SRUYR_QFN24_4X4
26 DH_CHG
0.047U_0603_16V7K 4.7UH_PCMB063T-4R7MS_5.5A_20%
PL302
0.01_1206_1%
0.5C charge
CMSRC HIDRV 1 2 CHG 1 4 BATT+
@ 2 PR339 1 20K_0402_1% 4
ACDRV 2 3
LX_CHG

1
100K_0402_1% 2 PR324 1 @ 27
BQ24780_VDD PHASE PR321

10U_0805_25V6K

10U_0805_25V6K
ACIN_R

2
0_0402_5% 1 2 PR325 @ 5 4.7_0603_5%

PC319
44 ACIN ACOK EMC@

PC320
0_0402_5% 1 2 PR320 @ EC_SMB_DA1_R 11
SDA DL_CHG

1
44,52 EC_SMB_DA1 PU301 23 PQ317 4
LODRV
2 PR322 @ EC_SMB_CK1_R

1
0_0402_5% 1 12 22 AON7408L_DFN8-5
44,52 EC_SMB_CK1 SCL GND PC321
2200P_0201_25V7-K
ADP_I_R

2
3
2
1
0_0402_5% 1 2 PR323 @ 7 29 EMC@
44 ADP_I IADP PAD

0.1U_0201_25V6-K

0.1U_0201_25V6-K
BQ24780_BATDRV

2
IDCHG 8 18

PC322

PC323
IDCHG BATDRV
9 PR338 10_0603_5%
PMON

1
59 Psys 17 2 1
BATSRC
100P_0201_25V8J
100P_0201_25V8J

SRP_R
2
2

20 2 1 SRP
SRP

0.1U_0201_25V6-K
10 PR328 10_0603_5%
44,59 VR_HOT# PROCHOT#

2
PC325
PC324

PC327
100P_0201_25V8J
1

13
CMPIN

1
BATPRES#
14

TB_STAT#
PC1108

CMPOUT
1

19 SRN_R 2 1 SRN
B
ILIM 21 SRN PR329 10_0603_5% B
ILIM
2

@
0_0402_5%

16

15
PR330
1

1 2 ILIM_R 1 2 TB_STAT#
+3VALW BATT_TEMP 44,52
PR331 14.7K_0402_1%
316K_0402_1% PR332
0.1U_0201_25V6-K
1
2

PR333
PC328

100K_0402_1%
need config special
1

appliction

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-CHARGER


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 53 of 60


5 4 3 2 1
5 4 3 2 1

+3VALW

2
PR407
100K_0402_5%
@
V20B+ @

1
2
PJ401
1
1.5A +3V_VIN
PU401
5 9 +3V_PWRGD TDC-5A OCP-12A OVP-120%
2 1 4 IN1 PG 1 +3VBS 1 2

10U_0805_25V6K

10U_0805_25V6K
3 IN2 BS

0.01U_0201_25V6-K
1

1
PC403
2 IN3 +3VALW

SY8286BRAC_QFN20_3X3
JUMP_43X79 0.1U_0603_25V7-M

PC401

PC402

PC452
IN4 6 @
LX1

2
7 19 PL401 PJ402
8 GND1 LX2 20 +3VLX 1 2 +3VALW_P 2 1
18 GND2 LX3 2.2UH_PCME063T-2R2MS_8A_20% 2 1

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
D
21 GND3 D
GND4

1
PR414 @ PR415 @ JUMP_43X79
1 2 EMC@ EC_ON_R 1 2 +3VALW_EN 12 14 +3VALW_P PR403

PC434

PC432

PC431

PC435
39,44,55 EC_ON +3V_VIN 11 EN1 OUT 2.2_0805_5%
EN2 +3VALW_FB

2
0_0402_5% 0_0402_5% 13 EMC_NS@
10 FF
NC1

2
15
NC2 100mA +3VLP

1
16 17

1M_0402_5%
NC3 LDO

0.1U_0201_25V6-K

1
PR401
1
PC410

PC408

4.7U_0603_6.3V6K
1
@ 1200P_0201_25V7-K

2
EMC_NS@

PC409
2

2
PC411
PR405
1 2 1 2

1K_0402_1%
+3VL 1000P_0201_25V7K
+3VLP @
PJ404
2 1
2 1

JUMP_43X39

+3VALW

2
C C
PR406
100K_0402_5%

V20B+

1
@
PU402 @ TDC-6A OCP-14A OVP-120%
2
PJ405
1
2.5A +5V_VIN 5 9 ALW_PWRGD PC415
2 1 IN1 PG ALW_PWRGD 55
4 1 +5VBS 1 2
+5VALW

10U_0805_25V6K

10U_0805_25V6K
IN2 BS

0.1U_0201_25V6-K
1

1
3

PC413

PC414
JUMP_43X79 PC412 2 IN3 0.1U_0603_25V7-M PL402 PJ406
IN4 6 +5VLX 1 2 +5VALW_P 2 1
LX1 2 1
2

2
7 19 2.2UH_PCME063T-2R2MS_8A_20%

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
8 GND1 LX2 20
GND2 LX3

1
18 JUMP_43X79
21 GND3 PR410 @ PR411

PC417

PC418

PC419

PC420
PR409 @ GND4 14 +5VALW_OUT 1 2 +5VALW_P 2.2_0805_5% @
EMC@
EC_ON_R +5VALW_EN OUT

2
1 2 12 EMC_NS@
+5V_VIN 11 EN1 13 0_0402_5%
EN2 FF

2
0_0402_5%
15
LDO +5VLP

1
10
NC1
16 17 2
+5VVCC 1
100mA PC423
1M_0402_5%

NC2 VCC
0.1U_0201_25V6-K

4.7U_0603_6.3V6K
1

1
PC416 1200P_0201_25V7-K

2
1

EMC_NS@
PC421

PR412

PC422
@ SY8288CRAC_QFN20_3X3 1U_0603_25V6M

2
2

PC424
PR413
+5VFB 1 2 1 2

1K_0402_1%
1000P_0201_25V7K

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_3VALW/5VALW


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
6800pf soft start 2ms AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
47nf soft start 7ms DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 54 of 60


5 4 3 2 1
5 4 3 2 1

PR500 @
0_0402_5%
1 2 PMIC_VCC

PMIC_VCC PR521 @ 1 2 0_0402_5%


EC_ON 39,44,54

PR522
0_0402_5%
D 1 2 D
ALW_PWRGD 54
+5VALW @

+5VLP 1
PR502 @
2
PR523
0_0402_5%
1 2 PCH_PWR_EN
10_0603_5%
1 2 0_0402_5% VDDQ_EN
PR501 @ PR520 @
44 SYSON 1 2

PMIC_EN
10_0603_5%
1 2 0_0402_5% VTT_EN
PR503 @ PC500
5 CPU_DRAMPG_CNTL 1 2
PR505
1 2 0_0402_5% +1.8VALW_L_EN VDDQ_P 1 2
PR504 @ 2.2U_0603_6.3V6K

2
10_0402_5%

VSYS_PMIC
1 2 0_0402_5% +1.0VALW_EN
PR506 @ PC502
44,46 PCH_PWR_EN 0.1u_0201_10V6K

1
+1.8VALW_B_EN
PR507 2 1
1M_0402_5%

28

27

41
EC_VPP_PWREN +2.5V_DDR_EN PU500

9
PR508 @ 1 2
44 EC_VPP_PWREN

VCC

PMIC_EN

GND
VSYS
0_0402_5%
+2.5V_DDR_EN PMIC_SMB_DAT1

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
29 25 PR510 @ 1 2 0_0402_5%
EN_LDO1 SDA EC_SMB_DA3 44

2
PC504

PC506

PC507

PC503

PC508
+1.8VALW_L_EN 1 26 PMIC_SMB_CLK1 1 2 0_0402_5%
PR511 @ EC_SMB_CK3 44
EN_LDO2 SCL
+1.0VALW_EN PMIC_ALERT#

1
11 24 PR512 2 1 @ 0_0402_5%
EN_V1P0A T_ALERT_B H_PROCHOT# 4,44
@ @ @ @ @
+1.8VALW_B_EN 16 22 +1.0VALW_PG 1 PAD @ PTC501
EN_V1P8A POK_V1P0A
VDDQ_EN 31 21 +1.8VALW_B_PG 1 PAD @ PTC502
EN_VDDQ POK_V1P8A
+3VALW
2A VTT_EN 36 23 VDDQ_PGOOD
EN_VTT POK_VDDQ
+5VALW TDC-6A OCP-10A OVP-135%
PJ500 @ 12 0.47UH_PCME063T-R47MS_18A_20% PJ501 @
+1.0VALW_B_VIN LX_V1P0A_12 LX_1P0 +1.0VALW_FB

22U_0603_6.3V6-M
2 1 7 13 1 2 2 1
2 1 VIN_V1P0A_7 LX_V1P0A_13 2 1
+1.0VALW

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
LV5075AGQV_VQFN40_5X5
8 14 PL500
VIN_V1P0A_8 LX_V1P0A_14

1
1

1
15 JUMP_43X79

100K_0402_5%
JUMP_43X39 PC510 LX_V1P0A_15

PC512

PC516
PC509

PC513
PC511

PC514

PC515
+1.0VALW_FB

1
0.1u_0201_10V6K 10

PR513
R_0402
VO_V1P0A

2
2

2
EMC_NS@
@ @
17
LX_V1P8A_17

LX_1P0
19 18
VIN_V1P8A_19 LX_V1P8A_18

2
20
VO_V1P8A_20
C C
UG_VDDQ

1
33
38 UGATE_VDDQ PR1031 PC518 PR1029
+1.2V_P VIN_VTT 32 BST_VDDQ 2 1
PC517 1 2 10U_0603_10V6K 1 2 4.7_0603_5%
PJ508 @ BOOT_VDDQ EMC@
2 1 39 0_0603_5% 0.1U_0603_25V7-M
+0.6VS 2 1 VTT LX_VDDQ

2
34
VDDQ_PGOOD 44 PHASE_VDDQ

22U_0603_6.3V6-M
1
2A JUMP_43X39 LG_VDDQ

1
40 35

PC519
VSNS_VTT LGATE_VDDQ PC1109
+1.2V_P

2
PR515 @ 37 2200P_0201_25V7-K
VSNS_VDDQ

2
1 2 30 EMC@
CS_VDDQ

1A
33K_0402_1%
600mA
PJ502 @ PJ503 @
2 1 +2.5V_DDR_VIN 5 6 +2.5V_P 2 1
+3VALW 2 1 VIN_LDO1 LDO1 2 1 +2.5V_DDR
JUMP_43X39
PC521
2 1
1 2
JUMP_43X39 6mA
PC520 22U_0603_6.3V6-M

600mA PJ504 @
10U_0603_10V6K
+1.8VALW_L_VIN LDO2
3 +1.8VALW_L_P 2
PJ505
2 1
@
1
+1.8VALW
2 1 4
+3VALW 2 1 VIN_LDO2 2
FB_LDO2 JUMP_43X39

22U_0603_6.3V6-M
2
105K_0402_1%
JUMP_43X39

1
PR516
PC523

PC522
10U_0603_10V6K

+1.8VALW_L_FB
2

2
1
VDDQ_P
2A PJ506
2 1
2 1 V20B+

0.1U_0201_25V6-K
5
JUMP_43X39

10U_0805_25V6K
10U_0805_25V6K
EMC@ PC524
@

1
1

PC526
PC525
PQ500
UG_VDDQ

2
2
2
4
PR517 AON7408L_DFN8-5
75K_0402_1% TDC-6A OCP-10A OVP-120%

3
2
1
0.68UH_PCMB063T-R68MS_16A_+-20%
PJ507
PL501
LX_VDDQ 1 2 +1.2V_P 2 1
2 1
+1.2V

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X79

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
5

2
AON7506_DFN @ @

0.1U_0402_25V6
1

1
1
4.7_0805_5% @

1
B PR518 B

PC527

PC528

PC529

PC530

PC531

PC532
PC1113
PQ501 EMC_NS@

2
LG_VDDQ

2
4

1
PC533
68P_0402_50V8J EMC_NS@
EMC_NS@

3
2
1

2
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-DDR4/1.0ALW/1.8ALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413 1.0

Date: Thursday, July 14, 2016 Sheet 55 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

Security Classification LC Future Center Secret Data Title


A A
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. CG413
Date: Thursday, July 14, 2016 Sheet 56 of 60
5 4 3 2 1
5 4 3 2 1

D D

ZVM# 16

1
U23E@ U23E@

100K_0402_1%
PR710 PR734 PC737

PR732

U23E@
0_0402_5% 2.2_0603_1% 0.1U_0603_25V7-M
U23E@ 1 2 2 1

2
1A

9
V20B+
4.5A

LP#

BST
MODE
PJ705
2 1 +VCCOPC_VIN 1 U23E@ +VCCOPC_L +VCCOPC_1.0V
2 1 VIN 0.56UH_PH041H-R56MS_5.4A_20%
JUMP_43X79 PL701 PJ706
8+VCCOPC_LX

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1

1
@ 1 2 2 1

PC722

PC720

PC750
U23E@

U23E@

U23E@
PU703 SW 2 1
NB681GD-Z_QFN13_2X3 JUMP_43X79

2
12 1 2 @
+VCCOPC_EN 5 VOUT 2.2_0603_1%
EN

1
PR736

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
PR721

U23E@
U23E@
1 2 3 PR717

@
PC716

PC721

PC717

U23E@
44,59 EC_VR_ON C1 2.2_0805_5%
C C

2
0_0402_5% EMC_NS@

2
2

U23E@ 4 2
47K_0402_5%

C0 PGND
1
PR719

1200P_0402_50V7-K
1
3V3
PC719 11

PG

EMC_NS@
.1U_0402_10V6-K AGND

PC718
2
1

13

10

2
@ @ U23E@ PR722

U23E@
PR701 1 2
VCCOPC_SENSE 12
U23E@ 5.1_0402_1% 0_0402_5%
+3VS 2 PR718 1 2 1 U23E@
+3VALW
0_0402_5%
PR708 100K_0402_5% 1 2
VSSOPC_SENSE 12

1U_0402_6.3V6K
1
1 2
PR723

PC732

U23E@
0_0402_5%

U23E@

2
VCCOPC_GND U23E@
PJ701
1 2 1 2

JUMPER 0_0402_5% VCCOPC_GND


@ PR709
U23E@

VCCOPC_GND

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-+VCCOPC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 57 of 60


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR-VGA_CORE_AMD
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 58 of 60


5 4 3 2 1
5 4 3 2 1

+VCCST_CPU
+5VS +5VS
V20B+

2
2.2_0603_5% 2.2_0603_5%

1
PR922 PR926
+VCCST_CPU

1
PC918

1K_0402_1%

75_0402_1%

100_0402_1%
45.3_0402_1%
1U_0402_6.3V6K

PR923

PR933

PR943

PR932
1

2
@

2.2U_0603_10V7K

2.2U_0603_10V7K
D D

2
53 Psys

2
PC912

PC916

VR_VCC
1

VR_VRMP

1
VR_PVCC
PC920

1
@ 0.01U_0402_25V7K

1K_0402_1%

1K_0402_1%

2
PR944 PR936

PR945

PR946
54.9_0402_1% @ @ 10_0402_1%
VR_SVID_DAT_1 2 1

18

13

12
VR_SVID_DAT 12
20K_0402_1% PU901 NCP81206MNTXG_QFN52_6X6 PR937
VR_SVID_DAT_1

2
1 PR940 2 50 36 0_0402_5%

PVCC

VCC

VRMP
PSYS SDIO 38 VR_SVID_CLK_1 VR_SVID_ALRT#_1 2 1
SCLK 37 VR_SVID_ALRT#_1 VR_SVID_ALRT# 12
PR916 @ PR938
1 2 VR_EN 41 ALERT# 49.9_0402_1%
44,57 EC_VR_ON EN VR_SVID_CLK_1 2 1
39 VR_SVID_CLK 12
0_0402_5%
DRON DRON 60
42
44 CPU_VR_READY VR_RDY
35
44,53 VR_HOT# VRHOT# PR919 PC910
26 Vcore_BST 1 2 1 2
BST3 23.2K_0402_1%
2.7K_0402_1% 1500P_0402_50V6-K
VCORE PORTION 2.2_0603_5% 0.22U_0603_16V7K 1 PR947 2
Vcore_COMP Vcore_PH 59,60
1 PR903 2 2 1 PC902 30 25
COMP_1a HG3 Vcore_HG 60
18K_0402_1%
1 2 2 PR901 1Vcore_ILIM 31 22K_0402_1% PH905
PC901 15P_0402_50V8J 1 2 ILIM_1a 24 1 PR948 2 1 2
SW3 Vcore_PH 59,60 +CPU_CORE 12,60
1.58K_0402_1% 1000P_0402_50V7K PC909
1 PR913 2 Vcore_VSP 28 100K_0402_1%_NCP15WF104F03RC
12 VCORE_VCC_SEN VSP_1a
1 2 1 2 23
LG3/ICCMAX_1b Vcore_LG 60
2

PC913 PR910 PC904 1000P_0402_50V7K 1K_0402_1% 11K_0402_1% 1 2


1.58K_0402_1% 1 PR911 2 Vcore_VSN 29 1 PR941 2 PC942 3300P_0402_50V7-K
1000P_0402_50V7K VSN_1a
470P_0402_50V7K
1

1 2 2 1 Vcore_IOUT 34 33 Vcore_CSP 1 2
12 VCORE_VSS_SEN IOUT_1a CSP_1a
330P_0402_50V7K PC906 PC911 PC922 2200P_0402_50V7K
2 1 27 32
PR917 TSENSE_1ph CSN_1a
C C
40.2K_0402_1%
Vcore_TSENSE
VCCGT PORTION 180K_0402_1%
GT_CSSUM
1

7 1 PR949 2
CSSUM_2ph GT_PH1 59,60
PR942 U23E@
MOSFET

0_0402_5% 6 GT_CSCOMP PR950 1 2 180K_0402_1% 1 2 PR904 1 2


CSCOMP_2ph GT_PH2 59,60
470P_0402_50V7K 110K_0402_1% PR1018
2 1 PC930 1 2 180K_0402_1%
100K_0402_1%_NCP15WF104F03RC

PH901 1 2 PC925 U23E@


1 2 GT_IOUT 1 U23E@ 220K_0402_5%_ERTJ0EV224J 220P_0402_50V7K
IOUT_2ph GT_ILIM
1

5 2 1 2 1
8.25K_0402_1%

ILIM_2ph
.1U_0402_10V6-K
1
Place close to

26.1K_0402_1% PR959 PR902 U23E@ PR951 16.9K_0402_1% PC914 330P_0402_50V7K 10_0402_1%


PH902

PR931

PC924

1 2 8 GT_CSREF 1 PR924 2
CSREF_2ph +VCC_GT 12,60
154K_0402_1%

0.22U_0603_16V7K
2

GT_DIFFOUT 2 14 GT_BST1 1 2 PR988


DIFFOUT_2ph/ICCMAX_2ph BST1

0.01U_0402_25V7K
2

470P_0402_50V7K PR934 2200P_0402_50V7K PR925 2.2_0603_5% 10_0402_1%

PC915
1 PR914 2 1 2 1 2 1 2 GT_COMP 4 1 2

PC917
COMP_2ph

1
2
49.9_0402_1% PC907 7.5K_0402_1% PC908 15
1 2 1 2 HG1 GT_HG1 60
U23E@

1
PR918 PC932 10P_0402_50V8J 0.047U_0402_16V7K

2
GT_FB

1
1K_0402_1% 3 16 PC926
FB_2ph SW1 GT_PH1 59,60

1
2
PC988
17 0.047U_0402_16V7K
LG1/ROSC GT_LG1 60

2
U23E@
PR954
2 1
51 14K_0402_1%
12 VCCGT_VCC_SEN VSP_2ph 10 GT_CSP1 1 2
CSP1_2ph GT_PH1 59,60
2

1.5K_0402_1% PR953
PC931 1 PR964 2 GT_VSN 52 1.8K_0402_1%
1000P_0402_50V7K VSN_2ph 9 GT_CSP2 1 2
CSP2_2ph GT_PH2 59,60
1

1 2 PR952
12 VCCGT_VSS_SEN 1 2
PC933 3300P_0402_50V7-K 1.8K_0402_1%

2
22.1K_0402_1% U23E@
PR927 PR1019
GT_TSENSE 11 40
B TSENSE_2ph PWM/ADDR_VBOOT GT_PWM 60 2K_0402_1% B
U22@

1
1.5K_0402_1% 0.015U_0402_25V7-K

0.22U_0603_16V7K
1 PR965 2 2 1 PC936 SA_COMP 47 22 SA_BST 1 2
COMP_1b BST2
+5VS
1

PR989 2.2_0603_5% 13K_0402_1%

PC989
PR960 1 2 PR912 30.9K_0402_1% 1 PR956 2
2 SA_ILIM 46
VCCSA PORTION SA_PH 59,60

2
0_0402_5% PC935 15P_0402_50V8J 1 21
ILIM_1b HG2 SA_HG 60
PR966 PR957
1 2 PH904
100K_0402_1%_NCP15WF104F03RC

1
1 2 1000P_0402_50V7K PC940 20 1 2 1 2
SW2 SA_PH 59,60 +VCCSA 13,60
30K_0402_1%
SA_VSP 49
1

3.16K_0402_1% 19 1 PR955 2 100K_0402_1%_NCP15WF104F03RC


8.25K_0402_1%

13 VCCSA_VCC_SEN PR907
.1U_0402_10V6-K

VSP_1b LG2/ICCMAX_1a 22K_0402_1%


1
PH903

PR963

PC934

1 2 1 2 1K_0402_1% PC941 2 15600P_0402_25V7-K


SA_VSN 48 SA_LG 60
PC937 PC938 1000P_0402_50V7K 1 PR970 2
VSN_1b SA_CSP
2

IOUT_1b

1000P_0402_50V7K 44 1 2
3.16K_0402_1% CSP_1b
2

1
2

1 2
EPAD

13 VCCSA_VSS_SEN 45
220P_0402_50V7K PC939 PC927 6800P_0402_25V7-K
CSN_1b
43

53

SA_Iout
1

1
470P_0402_50V7K PR958
PC929 121K_0402_1%
2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE1


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 59 of 60


5 4 3 2 1
5 4 3 2 1

+CPU_CORE
PJ1001
CPU_VIN 2 1
2 1 1 1
V20B+

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
1

1
JUMP_43X79 + PC1004 + PC1107

PC1002

PC1003
5
@ 68U_25V_M 68U_25V_M

PC1001

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
2

2
2 2

1
@

PC1005

PC1006

PC1007

PC1008

PC1009

PC1013

PC1010

PC1011

PC1014

PC1012
2

2
4
59 Vcore_HG
EMC@
AON6372_DFN8-5
PQ1001 +CPU_CORE @ @ @ @
0.15UH_PCMB063T-R15MS_30A_20%

3
2
1
1 2
59,60 Vcore_PH
PL1001
D D

1
PR1002 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
220U_D2_2VM_R6M
2.2_0805_5%

0.1U_0201_25V6-K
1

1
EMC_NS@ +

PC1015

EMC_NS@
PC1114

PC1078

PC1022

PC1016

PC1023

PC1017

PC1025

PC1018

PC1024

PC1019

PC1020

PC1021
2
4 2200P_0201_25V7-K
59 Vcore_LG

2
2 3
+CPU_CORE 12,59

1
AON6764_DFN8-5 EMC_NS@
PQ1002 PC1026
1000P_0201_50V7-K
3
2
1

2
Vcore_PH 59,60
EMC_NS@

@
PJ1002
GT_VIN 2 1
2 1 V20B+
JUMP_43X79

10U_0805_25V6K

10U_0805_25V6K
PC1030

0.1U_0201_25V6-K
1

1
5
1 2 1 2

U23E@

PC1083

PC1085
PR1013

U23E@

U23E@
PC1082
2.2_0603_5% 0.22U_0603_16V7K AON6372_DFN8-5

GT_BST2

2
U23E@ U23E@ PQ1007
U23E@ U23E@ U23E@
2.2_0603_5% PU902 4
PR1014 NCP81151MNTBG_DFN8_2X2 +VCC_GT
1 2 GT_VCC 4 1
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0_0402_5%
1 PR1004 2 GT_PWM_D 2 8 GT_HG2 U23E@
1U_0402_10V6K PWM DRVH

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59 GT_PWM U23E@ 0.15UH_PCMB063T-R15MS_30A_20%
1 1 2 GT_EN 3 7 GT_PH2 1 2
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PC1034

59 DRON EN SW
C 10_0402_5% PL1004 C
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PC1086
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1
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PC1084
1200P_0201_25V7-K

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GT_PH2 59

CPU_VIN
5

+VCC_GT

10U_0805_25V6K

10U_0805_25V6K
0.1U_0201_25V6-K
1

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PC1033

PC1031
PC1032

2
4
59 GT_HG1

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AON6372_DFN8-5

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PC1058
PC1052

PC1053

PC1055

PC1056

PC1059

PC1060

PC1061
PC1054

PC1057

PC1062

PC1063

PC1064
3
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2
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PC1066

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EMC_NS@
EMC_NS@

PC1081

PC1080

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22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

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PC1068

PC1071

PC1072

PC1074
PC1069

PC1075

PC1076

PC1077
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PC1073
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0.1U_0201_25V6-K

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22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
22U_0603_6.3V6-M

22U_0603_6.3V6-M
5

47U_0603_4V6-M

47U_0603_4V6-M

1
1
1

1
1
D

1
1

PR1006
PC1037

PC1040

PC1042
PC1036

PC1039
PC1115

PC1116

PC1038

PC1041

2.2_0805_5%
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2
2
2

2
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PC1046 Title
Security Classification LC Future Center Secret Data
3
2
1

1200P_0201_25V7-K
SA_PH 59,60
2

EMC_NS@
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR_CPU_CORE2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
CG413 1.0

Date: Thursday, July 14, 2016 Sheet 60 of 60


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