6/8/2021 Final-exam report

SUBJECT: INS3135

Group members:
Nguyễn Tất Bảo Ngọc – 17071391
Nguyễn Thái Học – 17071384
Nguyễn Minh Tuấn – 18071539
Bùi Quang Hiệp - 17071380

TOPIC 2
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Contents
List of figures .............................................................................................................................. 2

Project Brief ............................................................................................................................... 3

1. Circuit Specification ............................................................................................................... 4

2. Mathematical Design ............................................................................................................. 5

2.1 State Diagram................................................................................................................... 5

2.2 Truth and state tables ...................................................................................................... 6

2.2.1 Truth table for 4-bit Subtractor ................................................................................ 6

2.2.2 State table for counter circuit ................................................................................... 7

2.2.3 Truth table of converter circuit................................................................................. 8

2.3 Equation Minimization ..................................................................................................... 8

2.3.1 Equation Minimization for counter circuit ............................................................... 8

2.3.2 Equation Minimization for converter circuit .......................................................... 10

2.3.3 Equation Minimization for 4-bit subtractor:........................................................... 11

2.4 Logical circuit drawing ................................................................................................... 12

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List of figures
Figure 1.Counter state diagram ................................................................................................. 6
Figure 2. Converter State Diagram ............................................................................................ 7
Figure 3. A Full subtractor truth table ....................................................................................... 7
Figure 4. Counter state table (X: don’t care condidtion) ........................................................... 8
Figure 5. Excitation table of T flip-flop....................................................................................... 8
Figure 6. Converter truth table (X:don’t care condition) ........................................................... 8
Figure 7: 1-bit full- subtractor K-map ..................................................................................... 12
Figure 8. Counter circuit ........................................................................................................ 134
Figure 9. Converter & counter circuit ...................................................................................... 13
Figure 10. Digital system that contains a 4-bit subtractor, a counter and a converter. ....... 145
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Project Brief

Design a digital system that contains a 4-bit subtractor, a counter and a converter:

(1) The 4-bit subtractor that adds two numbers, one from the input and another from the
converter circuit,

(2) The counter that counts in the sequence 1, 4, 5, 9, 13, 14 and repeat,

(3) The converter that converts the counted sequence to 1, 3, 5, 7, 9, 11 to feed back into
subtractor.

Demonstrate in full detail the mathematical model of the design including: the state
diagram (for SC*), the truth (for CC*) and state (for SC) tables, the minimization of
equations, the logical circuit drawing, the explanations for all choices, the simulation using
HDL in active-HDL software, and evaluate the circuit when considering the propagation
delay time is 2ns for each basic gate and 10ns for each flip-flop.

*Sequential circuit: SC

**Combination circuit: CC
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1. Circuit Specification
This digital system includes 4-bit adder, a counter and a converter.

 The full subtractor circuit is basically two half subtractors connected together, the
truth table for the full subtractor r includes an additional column to take into
account the Carry-in, CIN input as well as the summed output, S and the Carry-out,
Cout bit . The single 1-bit binary subtractor can be constructed from basic logic
gates. If we wanted to add together two 4-bit numbers, then 4 number of 1-bit full
subtractor need to be connected or “cascaded” together to subtract two parallel 4-
bit numbers from each other. So by using an 4-bit adder and 4 number of inverters
(NOT Gates), the process of subtraction becomes an addition as we can use two’s
complement notation on all the bits in the subtrahend and setting the carry input of
the least significant bit to a logic “1”. Because the 4-bit subtractor that adds two
numbers, one from the input and the another from the converter circuit. So, we
have first number is B3, B2, B1, B0 and the second number is A3, A2, A1, A0 and A0 =
0.
 The counter that counts in the sequence 1, 4, 5, 9, 13, 14 and repeat. The counter uses
4 T Flip Flops and has 4 inputs T4,T3,T2,T1 , the present state includes Q4,Q3 ,Q2 ,Q1
; the next state includes Q4(t+1) , Q3(t+1) , Q2(t+1), Q1(t+1). The way the counter
works is that if we want to count a sequence of numbers, the 4 bits present sate
(Q4,Q3 ,Q2 ,Q1) will represent the initial number, the 4 bits next state ( Q4(t+1) ,
Q3(t+1) , Q2(t+1), Q1(t+1)) will represent the next number of the sequence. And then
continue like that until the last number of the sequence, the last number of the
sequence will be represented in the initial 4 bits present sate (Q4,Q3 ,Q2 ,Q1) , the
4 bits next state ( Q4(t+1) , Q3(t+1) , Q2(t+1), Q1(t+1)) will represent the original
number of the sequence, that means this counter counts a repeated sequence.
 The converter that converts the counted sequence to 1, 3, 5, 7, 9, 11 to feed back into
the adder. The converter has 4 bits input are ( Q4(t+1) , Q3(t+1) , Q2(t+1), Q1(t+1) –
the next sate of Counter and 4 bits output are A3, A2 ,A1 ,A0 and A0 = 0 ; 4 bits input
( Q4(t+1) , Q3(t+1) , Q2(t+1), Q1(t+1) represent the sequence 1, 4, 5, 9, 13, 14. This
converter will convert the numbered sequences into a new sequence represented by
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the output 4 bits A3, A2 ,A1 ,A0 and also because the conversion sequence is even, in
the 4 bits output A3, A2 ,A1 ,A0 , so the value of A0 is 0.

2. Mathematical Design
2.1 State Diagram
The state diagram for the counter that counts in the sequence 1, 4, 5, 9, 13, 14 and
repeat is shown as below.

Figure 1.Counter state diagram

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The state diagram for the converter that converts the counted sequence to 1, 3, 5, 7,
9, 11 to feed back into the adder:

Figure 2. Converter State Diagram

2.2 Truth and state tables

2.2.1 Truth table for 4-bit Subtractor

Figure 3. A Full subtractor truth table

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2.2.2 State table for counter circuit

State Table
Present State Next State
Q4 Q3 Q2 Q1 Q4(t+1) Q3(t+1) Q2(t+1) Q1(t+1) T4 T3 T2 T1
0 0 0 0 X X X X X X X X
0 0 0 1 0 1 0 0 0 1 0 1
0 0 1 0 X X X X X X X X
0 0 1 1 X X X X X X X X
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 1 0 0 1 1 1 0 0
0 1 1 0 X X X X X X X X
0 1 1 1 X X X X X X X X
1 0 0 0 X X X X X X X X
1 0 0 1 1 1 0 1 0 1 0 0
1 0 1 0 X X X X X X X X
1 0 1 1 X X X X X X X X
1 1 0 0 X X X X X X X X
1 1 0 1 1 1 1 0 0 0 1 1
1 1 1 0 0 0 0 1 1 1 1 1
1 1 1 1 X X X X X X X X
Figure 4. Counter state table (X: don’t care condition)

T flip-flop – If value of Q changes either from 0 to 1 or from 1 to 0 then input for T flip-flop is
1 else input value is 0.

Excitation Table
Q(t) Q(t+1) T
0 0 0
0 1 1
1 0 1
1 1 0

Figure 5. Excitation table of T flip-flop

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2.2.3 Truth table of converter circuit

Decimal Q4(t+1) Q3(t+1) Q2(t+1) Q1(t+1) A3 A2 A1 A0
0 X X X X X X X X
1 0 0 0 1 0 0 0 1
2 X X X X X X X X
3 X X X X X X X X
4 0 1 0 0 0 0 1 1
5 0 1 0 1 0 1 0 1
6 X X X X X X X X
7 X X X X X X X X
8 X X X X X X X X
9 1 0 0 1 0 1 1 1
10 X X X X X X X X
11 X X X X X X X X
12 X X X X X X X X
13 1 1 0 1 1 0 0 1
14 1 1 1 0 1 0 1 1
15 X X X X X X X X

Figure 6. Converter truth table (Don’t care condition)

2.3 Equation Minimization

2.3.1 Equation Minimization for counter circuit
Determine the input table of all T flip-flops by using the excitation table of T flip-flop.
Usually, T flip-flop is toggle in nature. Here, Q4 as Most significant bit and Q1 as least
significant bit.

Find value of T4, T3, T2, and T1 in terms of Q4, Q3, Q2, and Q1 using K-Map:
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Q4Q3\Q2Q1 00 01 11 10
00 X 0 X X
01 0 1 X X
11 X 0 X 1
10 X 0 X X

Therefore, T4= Q2 + Q4’Q3Q1

Therefore, T3= Q4’Q1 + Q2 + Q3’

Q4Q3\Q2Q1 00 01 11 10
00 X 0 X X
01 0 0 X X
11 X 1 X 1
10 X 0 X X

Therefore, T2= Q4Q3

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Therefore, T1= Q1’ + Q4 XNOR Q3

2.3.2 Equation Minimization for converter circuit

The converter that converts the sequence 1, 4, 5, 9, 13, 14 to 1, 3, 5, 7, 9, 11 to feed back
into the subtractor.

To find the corresponding digital circuit, we will use the K-Map technique for each of the
bits as output with all of the binary bits as input.

Here, Q output of counter is Q(t+1) next state

Find value of A3, A2, A1, A0 using K-Map (Karnaugh Map):

Q4Q3\Q2Q1 00 01 11 10
00 X 0 X X
01 0 0 X X
11 X 1 X 1
10 X 0 X X

Therefore, A3= A3= Q4Q3

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Q4Q3\Q2Q1 00 01 11 10
00 X 0 X X
01 0 1 X X
11 X 0 X 0
10 X 1 X X

Therefore, A2 = Q4Q3’+Q1Q4’Q3

Q4Q3\Q2Q1 00 01 11 10
00 X 0 X X
01 1 0 X X
11 X 0 X 1
10 X 1 X X

Therefore, A1= A1= Q1’ + Q4Q3’

Q4Q3\Q2Q1 00 01 11 10

00 X 1 X X

01 1 X X X

11 X 1 X 1

10 X 1 X X

Therefore, A0 =0

2.3.3 Equation Minimization for 4-bit subtractor:

The Boolean expression for a full subtractor is as follows:

For the DIFFERENCE (D) bit:

D = (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN)

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Which can be simplified too:

D = (X XOR Y) XOR BIN = (X ⊕ Y) ⊕ BIN

For the BORROW OUT (BOUT) bit:

BOUT = (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN) + (X.Y.BIN)

Which will also simplify too:

BOUT = X AND Y OR (X XOR Y)BIN = X.Y + (X ⊕ Y)BIN

Figure 7: 1-bit full-subtractor K-map

2.4 Logical circuit drawing

From the expressions of K-maps:
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Figure 8. Counter circuit

Figure 9. Converter & counter circuit

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Figure 10. Digital system that contains a 4-bit adder, a counter and a converter.