Digital Electronics.

CHAPTER TWENTY THREE

CMOS Inverter

1
 Introduction
© Dr. Anas

Complementary MOS (CMOS) uses a P-channel MOS as a pull-

up load device with an N-channel MOS as a pull-down device.

Ch. 23
CMOS is widely used in digital circuit technology because it
possesses the lowest power dissipation (wrist watches, hand-held
calculators, and recently note book computers) and has the
highest packing density.

All modern microprocessors are manufactured using CMOS

technology including Intel’s 80286, 80386, 80486, 8086, 8088
and Motorola’s 68010,68020,68030, 68040

In this chapter, we will describe the operation of CMOS as an

inverter device, and then analyze its VTC, power-dissipation, and
fan-out.

2
 Operation of CMOS Inverter
© Dr. Anas

The drain terminal of the NMOS is VDD

connected with the drain terminal of the
PMOS
Ch. 23 S
VIN  VGS , N  VDD  VSG, P
PO
D
The output is taken at the common drain G I DP  I DN
terminal
VOUT  VDS , N  VDD  VSD, P VIN
D  VOUT
NO

Note: either MOS can be considered as a VGS , N
load for the other, therefore the operations S
 
of NO and PO complement each other.

3
 VTC of CMOS Inverter
© Dr. Anas

VDD
VOH
When VIN=0, i.e. VIN=VGS,N<VTN: NO is
Ch. 23 cut-off
S

I D, N  I D, P  0

ID
PO
VX
PO VSG, P  VDD  VIN  VDD D
G I D, P  I D, N
VGS , P  VDD  VTP VGS
VIN
 Channel is created between the source and D  VOUT
the drain of PO MOS Linear
NO

|IDS|

VGS , N
In active mode: VGS  VTP 
VGS < VTP
S
VSG > -VTP  
Zero drain current |VDS|
Slide 3 of chapter 17
 PO is active (linear) mode 4
 VTC of CMOS Inverter
© Dr. Anas

VDD
VOH
When VIN=0, i.e. VIN=VGS,N<VTN: NO is
Ch. 23 cut-off
S

I D, N  I D, P  0 PO
 PO is active (linear) mode D
G I D, P  I D, N
I SD, P LIN  
Kp
2  V
SG, P 
 VTP VSD, P  V SD2 ,P  0 VIN
2 D  VOUT

VSD, P 2  VSG, P  VTP   VSD, P   0 

NO
VGS , N
VSD, P  0 
S

VSD, P  2  VSG, P  VTP   VSG, P  VTP
Invalid since VSD has to be
VOH  VDS , N  VDD  VSD, P  VDD
less than (VSG+VTP) 5
 VTC of CMOS Inverter
© Dr. Anas

VDD
VOL
For VIN=VOH=VDD.(VGS,P=0 >V(-)T,P)
Ch. 23 S
 PO is cut-off

Active mode: VGS  VTN  Zero drain current PO

 NO is active, linear D
G I D, P  I D, N
I DS , N LIN  
Kn
2
 
2  VGS , N  VTN VDS , N  V DS2 ,N  0 VIN
D  VOUT

VDS , N 2  VGS , N  VTN   VDS , N   0 

NO
VGS , N
VDS , N  0 
S

VDS , N  2  VGS , N  VTN   VGS , N  VTN
Invalid since VDS has to be
VOL  VDS , N  0 less than (VGS-VTN) 6
 VTC of CMOS Inverter
© Dr. Anas

NO is cut-off &
VDD
PO is active, linear
NO is sat & PO is sat
VOUT
Ch. 23 VOH  VDD S
  1   1
PO
VM D
G I D, P  I D, N

  1 VIN
D  VOUT
VOL  0 VIN
VIL VM VIH V  V  VDD NO
VT , N
DD TP

for VO  VOH VI  VIL  NO is cut-off & PO is linear
VGS , N
S
for VI  VIL NO is sat & PO is linear  
for VI  VO  VM NO is sat & PO is sat
for VI  VIH NO is linear & PO is sat
for VO  VOL NO is linear & PO is cut-off 7
 Power Dissipation CMOS Inverter
© Dr. Anas

IDD(OL)  PO is cut-off

IDD(OH)  NO is cut-off VDD

Ch. 23
S
Static Power Dissipation PDD(avg)

 I OL  I DD OH  
PO
PDD avg   VDD  DD 0 D
 2  G I D, P  I D, N

VIN
D  VOUT
NO

VGS , N
S
 

8
 Power Dissipation CMOS Inverter
© Dr. Anas

Dynamic Power Dissipation PDD(dyn)

PDD dyn   CL VDD 

2

Ch. 23 CL is the total load capacitance at the output of the gate

 is the switching frequency of the gate
PDD CMOS   PDD dyn  See example 23.1

PDD max 
PDD  VDD I DD
I DD max 
I DD

VIN
VTN VM VDD  VTP 9
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VOH
for VO  VOH VI  VIL 
Ch. 23 S
NO is cut-off & PO is linear
I D, N  I D, P  0 PO
D
VOH  VDD VDS , N  VDD G I D, P  I D, N

VIN
VOL D  VOUT

for VO  VOL NO is linear & PO is cut-off NO


I D, N  I D, P  0 VGS , N
S
 
VOL  0 VDS , N  0

10
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VIL for VI  VIL NO is sat & PO is linear

Ch. 23 VGS  VIL VSG, P  VDD  VIL S

VDS , N  VOut VSD, P  VDD  VOut
PO
I D, N 
Kn
VGS  VTN 2 I D , N  n VIN  VTN 
K 2 D
2 2 G I D, P  I D, N
I D, p 
Kp
2

2  VSG  VTP VSD  V SD2  VIN
D  VOUT

I D, p 
Kp
2
2  V DD  VIN  VTP VDD  VOUT   VDD  VOUT 
2
 
NO
VGS , N
S
I D , N I D , P  
I D, N  I D, P or 
VIN VIN
11
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VIL for VI  VIL NO is sat & PO is linear

Ch. 23 VGS  VIL VSG, P  VDD  VIL S

VDS , N  VOut VSD, P  VDD  VOut
PO
dVOUT D
 1 G I D, P  I D, N
dVIN VIN VIL
VIN
D  VOUT
2 K pVOUT  K p VDD  VTP   K nVTN
VIL  NO
Kn  K p 
VGS , N
S
 

12
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VIH for VI  VIH NO is linear & PO is sat

Ch. 23 VGS  VIH VSG, P  VDD  VIH S

VDS , N  VOut VSD, P  VDD  VOut
PO

 
D
 n 2  VIN  VTN VOUT  VOUT
K
I D ,n 2
G I D, P  I D, N
2
VIN
Kp D  VOUT
I D, p  VDD  VIN  VTP  2

2 NO

VGS , N
S
I D , N I D , P  
I D, N  I D, P or 
VIN VIN
13
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VIH for VI  VIH NO is linear & PO is sat

Ch. 23 VGS  VIH VSG, P  VDD  VIH S

VDS , N  VOut VSD, P  VDD  VOut
PO
dVOUT D
 1 G I D, P  I D, N
dVIN VIN VIH
VIN
D  VOUT
2 K nVOUT  K p VDD  VTP   K nVTN
VIH  NO
Kn  K p 
VGS , N
S
 

14
 VTC of CMOS Inverter
© Dr. Anas

Analytical determination of VTC :

VDD
VM Mid point

for VI  VO  VM
Ch. 23 S
NO is sat & PO is sat
PO
D
Kp I D, P  I D, N
Kn
VM  VTN   VDD  VM   VTP 2
2 G
2 2
VIN
D  VOUT
Then solve for VM
NO

VGS , N
S
See example on page 342  

15
 The Symmetric CMOS Inverter
© Dr. Anas

 The VTC of symmetric CMOS inverter is easily obtainable:

VDD
 One reason of designing a symmetric CMOS inverter is
to obtain a symmetric transient response:
Ch. 23 S
 Remember the VTC of CMOS inverter
PO
VOUT D
VOH  VDD G I D, P  I D, N
VOH  VOL VDD
VM   VIN
2 2 D  VOUT
VM
VIH  VIL VTN  VDD  VTP NO
VM   
2 2
VGS , N
VIN  S 
VOL  0
VTN  VTP
VT , N VIL VM VIH V  V  VDD
DD TP
16
 Design of Symmetric CMOS Inverter
© Dr. Anas

1. The threshold voltages of N-MOS and P-MOS are made

equal in magnitude VDD

2. The requirements for Kn=Kp must be considered

Ch. 23 Wp
S
Wn Kp   p Cox
Kn   nCox
Ln Lp
PO
3. Usually the gate oxide layers of the N-MOS and P- D
MOS devices are grown simultaneously, and hence G I D, P  I D, N
have the same thickness t ox
VIN
Wn W D  VOUT
n  p  p
Ln Lp
NO

VGS , N
4. Typically µn(Si)=580 cm2/V.s and µp(Si)=230 cm2/V.s S
 
Wp Wn
 2.5
Lp Ln
17
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution
For symmetry, the width of the channel of P-MOS is determined from

Wp Wn
 2.5 Wp  2.5  4  10m
Lp Ln
Wn K n  2  40  80A / V 2
Kn   nCox
Ln Equal values
Wp
Kp   p Cox K p  5 16  80A / V 2
Lp 18
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution
Kp 2 Slide 15 of this
Kn
VM  VTN   VDD  VM   VTP 
2
chapter
2 2
VM 12  5  VM  12
VDD
2VM  5  VM  2.5V VM 
2

19
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution Slide 12 of this

chapter
2 K pVOUT  K p VDD  VTP   K nVTN
VIL  160VOUT  805  1  80
Kn  K p VIL   VOUT  2.5
160

I D, N 
Kn
2
2 Kp
2

VIN  VTN   I D, p  2  VSG  VTP VSD  VSD2 
Kn
2
K

VIL  VTN 2  p 2  VDD  VIL   VTP VDD  VOUT   VDD  VOUT 2
2

 
VIL 12  2  5  VIL  15  VIL  2.5  5  VIL  2.52 20
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution
VIL 12  2  5  VIL  15  VIL  2.5  5  VIL  2.52 
 
12.75
VIL 1 2
 2  4  VIL 2.5  VIL   2.5  VIL 
2 VIL 
6
 2.125V

21
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution :similarly Slide 14 of this

chapter
2 K nVOUT  K p VDD  VTP   K nVTN 160VOUT  805  1  80
VIH  VIH   VOUT  2.5
Kn  K p 160

I D, N 
Kn
2
2 Kp
2

VIN  VTN   I D, p  2  VSG  VTP VSD  VSD2 
Kn
2
K

VIH  VTN 2  p 2  VDD  VIH   VTP VDD  VOUT   VDD  VOUT 2
2

 
VIH 12  2  5  VIH  15  VIH  2.5  5  VIH  2.52 VIH  2.875V
22
 Design of Symmetric CMOS Inverter
© Dr. Anas

 Example
Design a symmetrical CMOS inverter assuming:
VDD=5V, VTN=1 V, VTP=-1 V, µnCox=40 μA/V2 , µpCox=16 μA/V2 ,
Ch. 23 Wn=4 µm, Ln=Lp=2 µm
And verify that the midpoint voltage is half of VDD, and VIL and VIH
are symmetric about VM.

 Solution
VIL  2.125V VIH  VIL 2.875  2.125
  2.5V  VM
VIH  2.875V 2 2
VIL and VIH are symmetric about VM.

23
 Family Characteristics Example
© Dr. Anas

TTL Standard transistor/transistor logic 7400

L Low power TTL 74L00

H High speed TTL 74H00

S Schottky TTL - high speed 74S00

Ch. 23 LS Low power Schottky TTL 74LS00

AS Advanced Schottky 74AS00

ALS Advanced Low power Schottky 74ALS00

F Fast Schottky 74F00

HC High speed CMOS 74HC00

High speed CMOS, TTL-voltage

HCT 74HCT00
compatible

AC Advanced CMOS 74AC00

Advanced CMOS, TTL-output

ACT 74ACT00
compatible

24
© Dr. Anas

 HW #12:Solve Problems: 23.1-3, 23.22

Ch. 23

25