Digital Logic Design

Lab report 11

Submitted by
Adeel Sahto
Registration No:
FA20-BEE-019
Submitted to
Ma’am Faiza Rajab

Dated: 06/20/2021
 Lab# 11 Implementation of a BCD Counter with
Control Inputs on FPGA
Verilog Code:
module Lab_11(clk, reset, bcd_counter

);

input reset;

input clk;

output reg [6:0] bcd_counter;

reg [3:0] counter_state,next_state;

always@(posedge clk, posedge reset)

begin

if(reset == 1)

counter_state <= 4'b0000;

else

counter_state <= next_state;

end

always@(counter_state)begin

case(counter_state)

4'b0000:begin

next_state <= 4'b0001;

end

4'b0001:begin

next_state <= 4'b0010;

end

4'b0010:begin

next_state <= 4'b0011;

end

4'b0011:begin

next_state <= 4'b0100;

end
 4'b0100:begin

next_state <= 4'b0101;

end

4'b0101:begin

next_state <= 4'b0110;

end

4'b0110:begin

next_state <= 4'b0111;

end

4'b0111:begin

next_state <= 4'b1000;

end

4'b1000:begin

next_state <= 4'b1001;

end

4'b1001:begin

next_state <= 4'b0000;

end

endcase

end

always@(counter_state)begin

case(counter_state)

4'b0000:begin

bcd_counter <= 7'b1111110;

end

4'b0001:begin

bcd_counter <= 7'b0110000;

end

4'b0010:begin

bcd_counter <= 7'b1101101;

end

4'b0011:begin
 bcd_counter <= 7'b1111001;

end

4'b0100:begin

bcd_counter <= 7'b0110011;

end

4'b0101:begin

bcd_counter <= 7'b1011011;

end

4'b0110:begin

bcd_counter <= 7'b1011111;

end

4'b0111:begin

bcd_counter <= 7'b1110000;

end

4'b1000:begin

bcd_counter <= 7'b1111111;

end

4'b1001:begin

bcd_counter <= 7'b1111011;

end

default:begin

bcd_counter <= 7'b0000000;

end

endcase

end

endmodule

Verilog Testbench:
module TB_Lab_11;

// Inputs

reg clk;

reg reset;
 // Outputs

wire [6:0] bcd_counter;

// Instantiate the Unit Under Test (UUT)

Lab_11 uut (

.clk(clk),

.reset(reset),

.bcd_counter(bcd_counter)

);

always

begin

clk = 0;

#10;

clk = 1;

#10;

end

initial begin

// Initialize Inputs

reset = 1;

#10;

reset = 0;

#10;

// Add stimulus here

end

endmodule

Waveform: