Analog Integrated Circuits and Signal Processing

https://doi.org/10.1007/s10470-018-1158-9(0123456789().,-volV)(0123456789().,-volV)

Square root circuit using FGMOS translinear principle

Sinem Keleş1 · Fatih Keleş2 · Hulusi Hakan Kuntman3

Received: 30 September 2017 / Revised: 22 February 2018 / Accepted: 6 March 2018

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Abstract
A novel square root circuit using floating gate MOS (FGMOS) transistors operating in the saturation region is presented.
FGMOS transistors are being utilized in a number of new and exciting analog applications. These devices are available in
standard CMOS technology because they are being widely used in digital circuits. FGMOS structures are also known as
multi-input MOS and their multi input advantages make it simpler to realize an arithmetic signal processing circuit. Thus
floating gate devices are now finding wider applications by analog researchers. The FGMOS drain current is proportional to
the square of the weighted sum of the input signals. This square law characteristic of the FGMOS transistor is used to
implement the quarter square identity by utilizing only four FGMOS transistors in proposed square-root circuit. The main
feature of this remarkably simple square root circuit is to reduce the errors generated by the second order effects in the
current mode circuits employing translinear loop.

Keywords FGMOS · Square root · Second order effects · Translinear

1 Introduction have found many applications in electronic programming,

Floating gate (FG) MOSFETs are being utilized in a
number of new and exciting analog applications. These
devices are available in standard CMOS technology
because they are being widely used in digital circuits. Thus
floating gate devices are now finding wider applications by
analog researchers. As a result the floating gate devices are
not only used for memories but are also being used as
circuit elements such as analog memory elements, part of
capacitive biased circuits and adaptive circuit elements [1].
FGMOS structures are also known as multi-input MOS
and their multi input advantages make simpler to realize
arithmetic signal processing circuits. The FGMOS drain
current is proportional to the square of the weighted sum of
the input signals. In the last few years, FGMOS transistors
& Sinem Keleş
sinem.keles@medeniyet.edu.tr; sinem.keles@gmail.com
1
Department of Electrical and Electronics Engineering,
Istanbul Medeniyet University, Istanbul, Turkey
2
Department of Computer Engineering, Istanbul University,
Istanbul, Turkey
3
Department of Electronics and Communication Engineering,
Istanbul Technical University, Istanbul, Turkey
Op-amp offset compensation, D/A and A/D converters,
inverters and amplifiers, voltage attenuators, current mir-
rors and low voltage analog circuits. Recently, an increased
number of publications on the use of the FGMOS in analog
computational circuits have been reported as voltage
squarers and multipliers [2].
The FGMOS transistor can, in general, be treated as a
normal MOS transistor. It can be fabricated in any MOS
technology, although for a good performance, a double
polysilicon layer is recommended. The physical models
used to describe the MOS transistor can be adapted for the
FGMOS just by applying a change of variables into the
equations. Similarly, the same simulation models can be
used, as long as the simulations are set up properly. The
equivalent schematic for an n-input n-channel FGMOS
transistor is given in Fig. 1.
In this paper, a novel square root circuit using FGMOS
transistors operating in the saturation region is presented.
The drain current is proportional to the square of the
weighted sum of the input signals. This square law char-
acteristic of the FGMOS transistor is used to implement the
quarter square identity by utilizing only four FGMOS
transistors. The main feature of this remarkably simple
square root circuit configuration is to reduce the errors

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Fig. 1 Diagram of an n-input n-channel FGMOS transistor
generated by the second order effects in the current mode
circuits employing translinear loop.
Reduction occurred in the size of MOSFETs in inte-
grated circuit technology affects the MOSFET perfor-
mance and the quadratic relationship gives its place to the
linear V–I relationship. This may cause errors in circuits
including small-sized transistors. So the conventional
approaches cannot be used in the MTL circuits which use
small transistors. Menekay [3] proposed a method to cancel
mobility reduction effect in MTL circuits. A resistor is
added between the transistors forming the translinear loop
in order to shift the voltage level and the error is reduced
by forcing the output current to flow via this resistor. In this
approach small transistors can be used in MTL circuits, but
their method needs a control voltage and this control
voltage changes the gate-source voltage of a MOS tran-
sistor acting as an adjustable resistor placed in the loop. So
this control voltage is expected to work properly. Another
drawback of this circuit is that, changes in VDS of this
transistor causes variations in the value of the resistance
which can affect the functionality of the circuit. Tavassoli
[4] proposed a similar method to reduce the error caused by
mobility reduction effect. The proposed method is said to
be a more simple solution than previous work [3] in which
a control voltage is needed to guarantee the functionality of
the circuit. By means of this method, two transistors and a
resistor are added to the conventional circuit in order to use
small transistors in MTL. By cancelling the mobility
reduction effect, higher precision is said to be achieved.
The drawback of this design is the use of a resistor to
compensate for the errors of the voltage term that is added
to the MTL loop and this will increase the silicon area of
the circuit. As against with these two earlier approach,
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Analog Integrated Circuits and Signal Processing
proposed FGMOS square root circuit has less transistors
and the most importantly there isn’t any need to use a
resistor and control voltage to shift the voltage level as in
[3, 4].
In this paper, a method to reduce the errors generated by
the second order effects in the current-mode circuits
employing FGMOS translinear loop is proposed and this
method is applied to the square-root circuit. The main
advantage of the proposed circuit is reducing the errors of
the output current function. It is clearly seen that the pro-
posed FGMOS square root circuit gives less errors than the
conventional MOS square root circuit. In proposed
FGMOS square root circuit, output current results already
complies with the ideal results without an additional
resistor or control voltage.
Remainder of this paper is organized as follows. In
Sect. 2, translinear circuit principle for FGMOS transistors
is described. Proposed FGMOS square root circuit is pre-
sented in Sect. 3. Simulation results of the proposed circuit
are shown in Sect. 4 followed by conclusion in Sect. 5.
2 Translinear circuit principle for FGMOS
transistors
Translinear circuit principle which was originally formu-
lated for loops of bipolar transistors is generalized and the
MOS translinear principle is derived by Seevinck [5] MOS
translinear circuits are used in a lot of analog building
blocks such as square-root domain integrators [6], differ-
entiators [7], filters [8], oscillators [9], multipliers [10] and
RMS_DC converters [11].
The FGMOS transistor can, in general, be treated as a
normal MOS transistor. It can be fabricated in any MOS
technology, although for a good performance, a double
polysilicon layer is recommended. The physical models
used to describe the MOS transistor can be adapted for the
FGMOS just by applying a change of variables into the
equations. Similarly, the same simulation models can be
used, as long as the simulations are set up properly. So,
MOS translinear principle can be used for FGMOS tran-
sistor loops, too.
General current equation can be written for the FGMOS
transistors seen in Fig. 2;
!2
X
N;M
Ci
IDk ffi bFG Vki  VT 0 ; k ¼ 1; 2 ð1Þ
i¼1 T
C
 
l0 Cox W Ci 2
bFG ¼ ð2Þ
2 L CT
Analog Integrated Circuits and Signal Processing

ID1 ID2 square root circuit operating according to translinear circuit

principles will be mentioned.
One of the circuits created using translinear circuit
V0i=V1j principle is square root circuit. Figure 3 shows the
V01 V11
M1 M2 translinear loop cell used in the square root circuit.
V0N V1M
Considering a loop of MOS transistors as indicated in
Fig. 3, according to the translinear loop principle Eq. (8)
0 0 can be written as;
X X
VGS ¼ VGS ð8Þ
Fig. 2 Common input FGMOS transistor pair
cw ccw

CT CGB XN
Cj QFG CT where the subscripts cw and ccw indicate the devices
VT 0 ¼ VT  VBS  VkJ  ¼ VTFG ; k connected clockwise and counterclockwise in the loop,
Ci Ci j¼1
C i Ci Ci
j6¼1
respectively. Assuming well-matched threshold voltages
¼ 0; 1 and neglecting body effect allows the threshold voltages to
be dropped in VGS voltage expression obtained from the
ð3Þ quadratic current correlation as;
Drain currents of M1 and M2 can be expressed as in sffiffiffiffiffiffiffi sffiffiffiffiffiffiffi
X 2ID X 2ID
Eqs. (4) and (5). ¼ ð9Þ
!2 cw
b ccw
b
b0 X N
C0i
ID1 ffi V0i  VT 0 ð4Þ Relation Eq. (9) is a statement of the MTL circuit
2 i¼1 CT
principle [12].
!2 Square root circuit is one of the MTL circuits. Figure 4
b X M
C1j
ID2 ffi 1 V1j  VT 0 ð5Þ shows the proposed FGMOS square root circuit based on
2 j¼1 CT
conventional MOS square root circuit which is generated
Since one input of both M1 and M2 are common and the by using square root cell of Fig. 3.
translinear loop in Fig. 2 is expressed based on the current If there is a relationship between the transconductance
relationship, the following equations are obtained. of the MOS transistor parameters as 2β1 =2β2 =β3 =β4 =2β,
the following is obtained;
V0i ¼ V1j ð6Þ sffiffiffiffiffiffi sffiffiffiffiffiffi sffiffiffiffiffiffi sffiffiffiffiffiffi
0 1 2I1 2I2 2I3 2I4
þ ¼ þ ð10Þ
Bsffiffiffiffiffiffiffiffiffi X C b b 2b 2b
CT BB 2ID1 þ VT 0 
N
C0k C
B V0k C
C
C0i @ b0 CT A Drain currents of transistors M3 and M4 are equal
k¼1 according to Fig. 3 and taking the square on both sides of
0 k 6¼ i 1 Eq. (10), the equaion can be rewritten as follows.
B s ffiffiffiffiffiffiffiffi
ffi C pffiffiffiffiffiffiffiffi 1
CT B XM C I3 ¼ I1 I2 þ ðI1 þ I2 Þ ð11Þ
¼ B 2ID2 þ VT 0  C1k
V C ð7Þ 2
B
C1j @ b1 CT
1k C
k¼1 A
k 6¼ j
(I1+I2)/2
Iout
I1
3 Proposed FGMOS square root circuit
M2
M3
Reduction occurred in the size of MOSFETs in integrated
circuit technology affects the MOSFET performance and
M1 I3=I4
the quadratic relationship gives its place to the linear V–I
relationship. This may cause errors in circuits including I2
small-sized transistors. In this section, advantages of using M4
FGMOS transistors in order to reduce the error rate in a

Fig. 3 Square root cell

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 Analog Integrated Circuits and Signal Processing

P 2
N
When the Kirchhoff’s current law is applied to the
b
Ci
i¼1 CT ViS  VT 0
output node, Eq. (11) can be obtained as follows. ID ¼   ð14Þ
2 1 þ h0 PN Ci
ViS  VT 0
i¼1 CT

1 pffiffiffiffiffiffiffiffi Ѳ’ is the new mobility reduction parameter that can be

Iout ¼ I3  ðI1 þ I2 Þ ¼ I1 I2 ð12Þ
2 expressed as in Eq. (15).
Translinear circuit principle is derived for MOS tran-
sistors with an ideal square law characteristic in Eq. (9), but l
h0 ¼ h þ ð15Þ
various effects which are called second order effects cause vmaks Leff ð1 þ FB Þ
a deviation from the ideal square law behavior and
translinear circuit principle. These effects are the body Ѳ is the mobility reduction parameter, µ is the carrier
effect, mobility reduction, weak inversion, channel length mobility, vmaks is the maximum carrier velocity, Leff is the
modulation, component mismatches, errors caused by channel length and FB is the bulk charge parameter.
parasitic resistance and capacitance and temperature PN
CT ViS  VT voltage can be
Ci
According to the Eq. (14) 0
dependence. i¼1
The mobility reduction affects the statement of the written as;
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
translinear circuit principle for FGMOS transistors that is
X  0 2
0
N
Ci ID h ID h 2ID
obtained in (9) as shown below. ViS  VT 0 ¼ þ þ ð16Þ
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
iffi CT b b b
u h P i¼1
u
X t2ID 1 þ h
N Ci
i¼1 CT ViS  VT 0
Assuming that the drain current is small as follows:
b  0 2
cw vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
iffi ID h
u h P

2ID
ð17Þ
u
X t2ID 1 þ h
N Ci
i¼1 CT ViS  VT 0 b b
¼ ð13Þ
ccw
b P
N

CT ViS  VT voltage equation can be expressed as in

Ci
0

Ѳ is the mobility reduction parameter in Eq. (13). Current i¼1

relation for a FGMOS transistor operating in the saturation Eq. (18).
region is as given in (14) when considering mobility sffiffiffiffiffiffiffi
X
N
Ci ID h0 2ID
reduction parameter. ViS  VT 0  þ ð18Þ
i¼1
CT b b

VDD

M5 M6
M12

M4
I4
M1
I3 I2
I1 M2 M3
I1 Iout
I2

M7 M13
M8 M9 M10
M11 M14

VSS

Fig. 4 Proposed FGMOS square root circuit

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Analog Integrated Circuits and Signal Processing

Fig. 5 Output currents of MOS 12u

and proposed FGMOS square
root circuits
MOS

8u
ideal

Iout
A
FGMOS
4u

-4u
0s 0.2ms 0.4ms 0.6ms 0.8ms 1.0ms 1.2ms 1.4ms 1.6ms 1.8ms 2.0ms
SQRT(I(Iss1)*I(Iss2)) IS(my3) IS(my33) Time

Table 1 Comparison with previous papers which proposed a method to cancel mobility reduction effect in MTL circuits
Publication Circuit simplicity Precision Component used for level shifting

Menekay et al. [3] 19 transistors+control voltage Not mentioned Control voltage and MOS transistor acting as a resistor
Tavassoli et al. [4] 16 transistors+resistor Less than 18% (IO\10 µA) Resistor
Less than 4% (IO[10 µA)
Proposed SR-circuit 14 transistors Less than 3% –

pffiffiffiffiffiffiffiffi
If there is a relationship between the transconductance I1 I2
E¼  ð22Þ
parameters of the transistors M1–M4, which are forming I1 þI2
2  hb0 VE
the translinear loop, as 2β1 =2β2 =β3 =β4 =2β; translinear
circuit principle can be expressed as below. As seen from the Eq. (22) Ci capacity values must be
XX
N X XX
N X chosen carefully to minimize the error term VE.
Ci Cm
ViSj  VT 0 k ¼ VmSl  VT 0 n
j¼1;2 i¼1
CT k¼1;2 l¼1;2 m¼1
CT n¼1;2

ð19Þ 4 Simulation results

If all the terms except VT in Eq. (3) are called VE and Proposed FGMOS square root circuit is simulated by using
the Eq. (18) is transferred to the Eq. (19), below equation is TSMC 0.35 μm technology parameters in SPICE simula-
obtained. tion program. Supply voltages are chosen as±1.5 V. Input
current I1 is taken as DC current with amplitude 5 μA and
h0 the other input current I2 is taken as a triangular wave with
VE1 þ VE2  VE3  VE4 ¼ ðI 1 þ I 2  I 3 Þ ð20Þ amplitude 20 μA. While the input capacitor values are
b
chosen as Ci =60 fF for M1–M2 and Ci =120 fF for M3–
If the left side of the Eq. (20) is called briefly VE and M4, CFGD and CFGS capacitor values are calculated as 0.9
Eq. (11) is used, output current of FGMOS square root and 3 fF for M1–M2 and 1.8 and 6 fF for M3–M4,
circuit is obtained as given below. respectively. Transistor aspect ratios are chosen as W/L=
 
pffiffiffiffiffiffiffiffi I1 þ I2 b 3 μm/0.7 μm for M1–M2 and M9–M10 and W/L=6 μm/
Iout ¼ I1 I2 ¼  0 VE E ð21Þ 0.7 μm for all other transistors. The output currents of the
2 h
proposed FGMOS square-root circuit and the conventional
E is defined as; MOS square-root circuit are simulated with the ideal
function as shown in Fig. 5. The maximum error of

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FGMOS square root circuit is measured as 0.3 μA while
this error is 1.63 μA for MOS square root circuit.
A comparison of this paper and previous papers is given
in Table 1. The method in Menekay et al. [3] needs a
control voltage, which changes the gate-source voltage of a
MOS transistor acting as an adjustable resistor placed in
the loop, to work properly and another drawback of this
circuit is that the changes in VDS of this transistor cause
variations in the value of the resistance which can affect
the functionality of the circuit. The drawback of Tavassoli
et al. [4] is the use of a resistor to compensate for the errors
of the voltage term that is added to the MTL loop and this
will increase the silicon area of the circuit. In [3, 4], a
resistor is added between the transistors forming the
translinear loop in order to shift the voltage level and the
error is reduced by forcing the output current to flow via
this resistor. In proposed FGMOS square root circuit,
output current results already complies with the ideal
results without an additional resistor because of the level
shifting property of FGMOS transistors.
When the proposed FGMOS square root circuit is
compared with the square root circuits that have been
proposed earlier in literature [3, 4, 13, 14], it is seen that
proposed FGMOS square root circuit has less transistors,
lower supply voltages, wider input current range and the
most importantly there isn’t any need to use a resistor to
shift the voltage level as in [3, 4].
5 Conclusions
In this paper, a method to reduce the errors generated by
the second order effects in the current-mode circuits
employing FGMOS translinear loop is proposed and this
method is applied to the square-root circuit. The main
advantage of the proposed circuit is reducing the errors of
the output current function. It is clearly seen that the pro-
posed FGMOS square root circuit gives less errors than the
conventional MOS square root circuit.
References
1. Rodriguez-Villegas, E. (2006). Low power and low voltage cir-
cuit design with the FGMOS transistor. London, United King-
dom: The Institution of Engineering and Technology.
2. Keleş, S., & Kuntman, H. (2011). Four quadrant FGMOS analog
multiplier. TJEECS: Turkish Journal of Electrical Engineering
and Computer Sciences, 19(2), 291–301.
3. Menekay, S., Tarcan, R. C., & Kuntman, H. (2009). Novel high-
precision current-mode circuits based on the MOS-translinear
principle. International Journal of Electronics and Communica-
tions, 63, 992–997.
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4. Tavassoli, M., Khoei, A., & Hadidi, K. (2011). High-precision
MOS-trans-linear loop-based squarer/divider circuit free from
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Sinem Keleş received her B.Sc.,
M.Sc. and Ph.D. degrees in
Electronics and Communication
Engineering from Istanbul
Technical University, Istanbul,
Turkey in 2002, 2005 and 2013,
respectively. In 2002 she joined
the Electronics and Communi-
cation Engineering Department
of Istanbul Technical Univer-
sity. Since 2016 she is an
Assistant Professor in Istanbul
Medeniyet University. Her cur-
rent research interests are ana-
log circuit design, active filters,
FGMOS circuits and design of analog IC topologies.
Analog Integrated Circuits and Signal Processing

Fatih Keleş received his B.Sc., on modeling and simulation of electron devices and electronic circuits
M.Sc. and Ph.D. degrees in for computer aided design, analog VLSI design and active circuit
Electronics and Communication design. He is the author or the coauthor of 129 journal papers pub-
Engineering from Yildiz Tech- lished or accepted for publishing in international journals reviewed by
nical University, Istanbul, Tur- SCI and EI, 15 journal papers published in other journals, 180 con-
key in 2000, 2003 and 2010, ference papers presented or accepted for presentation in international
respectively. In 2001 he joined conferences, 161 Turkish conference papers presented in national
the Computer Engineering conferences and 10 books related to the above-mentioned areas.
Department of Yildiz Technical
University. Since 2011 he is an
Assistant Professor in Istanbul
University. His current research
interests are analog circuit
design and hardware imple-
mentations of neural networks.

Hulusi Hakan Kuntman received

his B.Sc., M.Sc. and Ph.D.
degrees from Istanbul Technical
University in 1974, 1977 and
1982, respectively. In 1974 he
joined the Electronics and
Communication Engineering
Department of Istanbul Techni-
cal University. Since 1993 he is
a professor of electronics in the
same department. His research
interest includes design of elec-
tronic circuits, modeling of
electron devices and electronic
systems, active filters, design of
analog IC topologies. Dr. Kuntman has authored many publications

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