Semiconductor Processing & Fabrication Technology

ECE 4201

PACKAGING OF IC

Presented By:
Etu Podder
Lecturer
ECE Discipline,
Khulna University, Khulna-9208.

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 Contents
 Introduction
 What is Packaging?
 Function of Packaging
 Parts of Package
 Packaging Process
• Backside Preparation • Bonding
• Wafer Testing • Preseal Inspection
• Die Separation • Sealing
• Die Pick and Place • Lead Plating & Trimming
• Die Inspection • Package Marking
• Die Attach • Final Testing
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 References

1. Peter Van Zant, “Microchip Fabrication”, McGraw-Hill, 2014.

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 Introduction
 Once the wafer has been fabricated, with all the layers deposited and connecting paths
etched, it can then move on to the final processing stages.
 This series of processes is known variously as packaging, assembly, or the back-end
process.

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 What is Packaging?
 Packaging refers to the set of processes that provide the electrical connectivity between IC and
external devices, thus allowing the chip to be integrated into a larger electronic system.
 In the packaging process, the chips are called dies or dice.
 During this stage, the dies gets covered in a package which provides the physical protection to the
chip.
 The process of putting the IC inside a package makes it reliable and convenient to use.
 Over the years, the direction of packaging technology is to develop smaller, cheaper, more reliable
and more environment friendly packages.
 Just like wafer fabrication technology, the advent of the VLSI/ULSI era in chip density has brought
a radical upgrading of chip packaging technology.

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 Function of Packaging
 There are four basic functions performed by a semiconductor package. They
are to provide:

 A substantial lead system

 Physical protection

 Environmental protection

 Heat dissipation

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 Parts of Packages
 The four functions of a chip package are accomplished through the use of a wide variety
of package designs.
 However, most packages have five common parts. Such as-

 Die-Attachment Area.

 Inner Leads.

 Outer Leads.

 Bonding Wires.

 Enclosure or Body.
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 Packaging Process
In general, the packaging process would consist of following steps-
 Backside Preparation
 Wafer Testing
 Die Separation
 Die Pick and Place Backside
Wafer Testing
Preparation
 Die Inspection
Die Pick and Place
 Die Attach
Die Inspection
 Bonding
 Preseal Inspection
 Sealing
 Lead Plating & Trimming
 Package Marking Bonding
 Final Testing
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 Backside Preparation
 After the wafer fabrication, one or two additional processes may be performed on the
wafer before transfer to packaging.
 These steps includes wafer thinning and backside gold, which are optional, depending on
the wafer thickness and the particular circuit design.
 The thickness of the wafers can affect die separation and packaging and hence the wafers
need to be thinned to the correct wafer thickness before assembly which is known as
wafer thinning.
 Another optional wafer process is adding a layer of gold in the fabrication area of wafers
by sputtering.

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 Wafer Testing
 It is practical to perform certain functional tests on the ICs while they are still attached
together on the wafer before the IC chips are separated.
 Computer controlled test equipment uses probes, which are configured to relay with the
connecting pads on the surface of the chip, to test the functionality of the chips.
 A series of tests are carried out to detect short circuits and other faults, followed by a
functional test of the IC.
 Any chips which do not pass the test are marked and are to be discarded after chip
separation.

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 Die Separation
 The traditional chip-packaging process starts with the separation of the wafer into
individual dies.
 After wafer sort, the chips are still part of the wafer.
 For use in a circuit or electronic product, they must be separated from the wafer.
 This is usually done by sawing or scribing the wafer, using a diamond saw or scribe, on
pre patterned scribe lines.

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 Die Pick and Place
 After die separation, the good dies are picked up for further processing.
 Prior to this, good/bad dies are identified in by wafer testing.
 In operation, a memory tape or disk that has recorded the locations of the good die and is loaded into
an automatic “pick” tool.
 A vacuum wand picks up the good die and automatically places them in a sectioned plate for transfer
to the next operation.

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 Die Inspection
 After die pick, the dies are inspected for cracks or defects on the good dies.
 This inspection is done using an optical microscope and the process is
automated.
 This inspection also sorts out surface irregularities, such as scratches and
contamination.
 The identification of damaged die saves the expenses and time of packaging a
failed die.

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 Die Attach
 After passing inspection, the die is then attached to the specific area of the package.
 The die attach process is used to create a strong bond between the die and package to
provide either an electrical conducting or insulating contact between the die and the
package, and to serve as a medium to transfer heat from the chip to the package.
 The die attachment can be conductive e.g. using a gold-silicon eutectic. The eutectic has a
melting point of 380◦C. Hence, gold is plated on the bottom of the die, in contact with Si
and then heated, so that the eutectic is formed and melts to form the bond.
 Non conducting attachments are also used. In this case, a epoxy adhesive material is used
to attach the die to the package.

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 Bonding:
 Bonding is the most important step in the packaging process.
 In bonding, wires are connected to the leads in the IC, so that the IC is electrically connected
with other devices.
 Bonding usually follows die attach, two steps are combined in the flip chip process.
 There are three main techniques for bonding-
 Wire bonding
 Tape bonding
 Flip-chip bonding

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 Bonding:
Wire Bonding:
 The process of providing electrical connection between the chip and the lead of the semiconductor
device using very fine Bonding Wires. The chips are bonded to their packaging.

 While simple in concept and procedure, wire bonding

is critical because of the precise wire placement and
electrical contact requirements.
 Wire bonding is done with either gold or aluminum
wires which are highly conductive and ductile enough
to withstand deformation during the bonding steps and
still remain strong and reliable.

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 Bonding:
Gold Wire Bonding:
 Gold has several pluses as a bonding wire material as it is the best known room temperature
conductor and is an excellent heat conductor.
 Two methods are used for gold bonding.
• Thermocompression Bonding.
• Thermosonic Bonding.
 In thermocompression bonding, the gold wire is fed through a
capillary and by thermo mechanical compression is bonded with
the die and lead. This is also called ball bonding. Gold ball wire bonding.
 Thermosonic bonding follows the same steps, but takes place at a lower temperature, provided by a
pulse of ultrasonic energy sent through the capillary into the wire which is sufficient to provide the
heat and friction to form a strong alloy bond.
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 Bonding:
Aluminum Wire Bonding:
 The Al wire bonding follows the same major steps as gold bonding.
 However, the method of forming the bond is different. No ball is formed.
 Here, a wedge bond is formed between the die and the lead. This is achieved by using ultrasonic
vibration.
 After the bond is formed, the wire is spanned to the inner lead
where another ultrasonic-assisted wedge bond is formed.
 This type of bonding is known variously as ultrasonic or wedge
bonding.
 The advantage of using Al is that, lower temperatures are needed
and it is cheaper than gold.
Aluminum wedge bonding

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 Bonding:
Disadvantages of Wire Bonding:
 There are electrical resistances associated with each bond.
 There are minimum height limits imposed by the required wire loops.
 There is the chance of electrical performance problems or shorting if the wires come to close to
each-other.
 The wires require an individual bonding step at both the chip bonding pad and at the package lead.
 Perhaps the biggest problem results from the increasing number of connections (pin count) needed
to operate larger circuits.
 Chip designers simply run out of space to locate the required number of connections around the
periphery of the chip.

 These issues are addressed by replacing wires with a deposited metal bump on each bonding pad.
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 Bonding:
Tape Bonding:
 Used for extremely thin device fabrication, also known as tape automated bonding (TAB).
 The electrical lead system is deposited on a flexible tape by sputtering or thermal evaporation.
 This is combined with a patterning or stamping process to make the leads on the tape.

 For bonding, the die is positioned and aligned

with the leads on the tape and the bonding is
completed by a tool called the thermode.
 The thermode has a heated flat diamond surface
that forces the tape onto the die and makes bond.

 The advantages of TAB are speed, in that all of the bonds to the chip are made in one action, and
the ease of automation offered by the system.
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 Bonding:
Flip-chip Bonding:
 This is also called bump and ball bonding or controlled collapse chip connection.
 It is currently in use in the IC industry, due to the large number of leads and the small spacing
between them.
 In this process, the wires are replaced by a reflowed solder bump.

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 Bonding:
Flip-chip Bonding:
 The metal bumps are deposited on top of the leads on the die and the chip is then flipped and bonded
with the package using the solder bumps.
 There is no separate die attach step, since both attach and bonding takes place through solder bumps.
 For additional mechanical stability, an epoxy filling is also used.

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 Preseal Inspection
 After bonding, there is an inspection step, preseal or precap inspection, sometimes called third optical
inspection to check the bonds formed.
 This inspection uses optical measurements to provide feedback on the quality of the operations
performed.
 There are different inspection criteria depending on the nature of the application such as commercial
and high-reliability.
 Commercial-level inspections screen the bonded chips for die-attach quality, correct placement of the
bonds on the bonding pads and inner leads, the shape and quality of the ball or wedge bond, and the
general condition of the chip surface in regard to contamination, scratches, etc.
 High reliability also specifies criteria for the chip surface, including pattern alignment, critical
dimensions, and surface irregularities, such as small scratches, voids, and small defects.
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 Sealing:
 After the bonded chip passes the optical inspection, it is ready for sealing in a protective
enclosure.
 Seals can be hermetic or non-hermetic, depending on the application.
 Several methods are used to achieve the enclosure of the chip depending on whether the
seal must be hermetic or nonhermetic and which type of package is to be used.
 Hermetic seals help in isolating the die from the atmosphere and include welding,
soldering, and glass sealing while premade packages are used.
 Non hermetic seals use epoxy molding, produces the traditional plastic package.

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 Sealing:
 If the package is a metal-can type, a hermetic seal is achieved by welding the flanged lid to a matching
flange on the base of the package.
 Premade ceramic packages are hermonic sealed by one of two methods, metal or ceramic lids.
 A completed Ceramic Dual In-Line Package (CERDIP ) results in a hermetic seal around the chip and
bonding wires, accomplished with glass, similar to the ceramic seal on the premade packages.
 The fourth major method of enclosure, epoxy molding, produces the traditional plastic package

Premade ceramic package.

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 Lead Plating
 Most package leads are coated with lead-tin solder, tin plate, or gold plate.
 The plating serves several important functions.
 The additional metal finish improves the lead solderability, resulting in a more reliable electrical
connection of the package and the printed circuit.
 It protects the leads from oxidation or corrosion during periods of storage prior to mounting on the
circuit board.
 Another benefit of lead plating is the protection of the leads from corrosive agents (solder flux,
corrosive cleaners, and even tap water) in the packaging and printed circuit-board mounting
processes.
 The plating continues to protect the leads during their lifetime of use.

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 Lead Trimming
 One of the last steps in the package-assembly process is trimming away excess material from the
leads.

 The outer leads of DIP (Dual in package) and flat-pack

packages are made with a tie-bar to keeps the leads from

becoming bent during the packaging process.

 At the end of the process, the package goes through a simple

trimming machine that simultaneously trims away the tie-bar

and trims the leads to the proper length.

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 Lead Trimming
 Plastic package lead frames have an additional piece of

material that functions as a dam to prevent the liquid

epoxy material. The dam is cut away from the frame with a

series of precise cutting tools.

 If the package is a surface-mount type, the leads will be

bent into the required shape.

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 Deflashing

 Plastic packages receive an additional process, called deflashing, which is

required to remove excess molding material from the package enclosure.

 Deflashing is done by either dipping the packages in a chemical bath followed

by a rinse or by a physical abrasion process.

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 Package Marking
 Once completed, a package is identified with key information.
 Typical information coded on the package is the product type, device specifications, date, lot
number, and where it was made.
 The main methods of marking are ink printing and laser inscription.
 In Ink printing process, the ink is applied by an offset printer followed by a curing step. It has the
advantage of good adherence to all of the package materials.
 Laser mark is permanently inscribed in the package surface and can provide good contrast on the
dark packages. It is fast and non contaminating since no foreign material is added to the package
surface, and no curing step is required.
 A drawback to laser marking is the difficulty of changing the mark if a wrong code was used or the
status of the device is changed.

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 Final Testing
 At the conclusion of the packaging process, the completed package is put through a series
of tests. Such as-
• Environmental Tests
• Electrical Tests
• Reliability Tests
 These tests vary in type and specifications, depending on the customer and use of the
packaged devices.
 The tests may be performed on all of the packages in a lot or on selected samples.

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 Final Testing
Environmental Tests

 Environmental tests are performed to weed out leaking and defective packages.
 Defects detected are loose chips, contaminants and particles in the die-attach cavity, and
faulty bonding.
 This testing series starts with a stabilization bake to drive off any volatile substances in the
package.
 A typical bake is at 150°C for 24 hours.

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 Final Testing
Environmental Tests

 The first environmental test is temperature cycling.

 The packages are loaded into a chamber and cycled between two temperature extremes.
The number of cycles may reach several hundred.
 The high and low temperatures of this test vary with the device use.
 During the cycling, any weakness in the seal, die attachment, or bonding will be
aggravated and detected in later electrical tests.

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 Final Testing
Environmental Tests
 A second environmental test is constant acceleration.
 In this test, the packages are accelerated in a centrifuge that creates a force as high as
30,000 times the pull of gravity on the Earth (30,000 g’s).

 During the acceleration, loose particles in the

package, poorly attached dies, and weakly
attached bonds are stressed so that they will be
detected at the final electrical tests.

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 Final Testing
Environmental Tests
 Leaks in the package enclosure are detected by Gross leak testing which is conducted by
submerging the packages in hot liquid.
 The heated liquid raises the temperature of the package and forces trapped gases in the
cavity to escape.
 The escaping gases are observable as bubbles rising in the liquid.
 Smaller (or fine) leaks are detected by using tracer gases.

 This test uses the helium gas or radioactive gas krypton-85

which is pumped through any leaks into the package under
pressure.
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 Final Testing
Electrical Testing

 The purpose of the wafer fabrication and packaging processes is to provide to the
customer a specific semiconductor device that performs to specific parameters.
 Thus, one of the last steps is an electrical test of the completed unit to verify that it
performs to specifications.
 The tests are similar to the wafer-sort tests.
 The overall objective is to verify that the good chips identified at wafer sort have not
been compromised by the packaging process.

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 Final Testing
Electrical Testing
 There is a series of parametric tests.
 These electrical tests check the general performance of the device or circuit and ensure
that it meets certain input and output voltage, capacitance, and current specifications.
 The second part of the final test is called the functional test. This test actually exercises the
specific chip functioning.
 Logic chips are put through logic tests, and memory chips are exercised in their data-
storage and retrieval capabilities.

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 Final Testing
Electrical Testing
 The electrical tests are performed by a computer-controlled tester that directs the
sequences and levels of the parametric and functional tests.
 The packages are connected to the tester through sockets; the socket unit is known as the
test head.
 The packages are inserted into the test head
manually or by an automatic unit known as a
handler.
 This handler may be mechanical or robotic,
depending on the speed and complexity of the
operation.
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 Final Testing
Reliability Testing
 The burn-in test is required for all high-reliability device lots, but it is optional on
commercial devices.
 The test requires the insertion of the packages in sockets and mounting in a chamber with
temperature-cycling capability.
 During the test, the circuits are temperature-cycled while under an electrical bias.
 By conducting burn-in tests, the early failures are detected.
 The devices passing the test are statistically more reliable.

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Thank you