Mode

Interfacing 8251A to 8086 in /O Mapped l/O

10.11
Fig
Fig. 10.11.1 shows the interfacing of 8251A with 8086 in I/O mapped 1/0
technique.
Here, RD and WR signals are activated when M/1O signal is low, indicating I/0
bus cycle.
O n l y lower data bus (Do - D,) is used as 8251A is 8-bit devic

Reset out signal from clock generator is connected to the reset of the 825lA
signal
I/O Map:

Register Address lines

Address
A7 Ag As A Ag A2 A Ag
Data Register 0 0 0 0 0 00 0OH
Control Register 00 0 0 00 1
wwwwww.w.owiveii ieriwweci 0 02H
erooroceSsor and Microcontroller
10- 17
Serial Communication Interfac
8251

Do Do-D7
D7 TxD
Reset out
Reset RxD
Clock out
CLK
M/TO
RD RD
Ao
WR 8251A
WR-
RXC- From pulse
A- A CID generator or
TXC timer

A-
As
Ay- CTS GND

with 8086 in VO mapped lVO

Fig. 10.11.1 Interfacing of 8251A
l/O
Interfacing 8251A to 8086 in Memory Mapped
10.12
uses 20 address
lines to identify an I/O
the 8086
I n this type of I/O interfacing,
a memory register.
connected as if it is
aevice; an I/O device is as those of memory.
and instructions to access I/O
n e 8086 uses same control signals I/0
8251A with 8086 in memory mapped
of
shows the interfacing
10.12.1
technique. activated when
M/1O signal is high, indicating

Her D and WR
K
signals are

The
register.
nemory bus cycle. register or
control
either data 8251A.
select addresses for
Address line A is used used to
used to
decoder the
are
aining address lines Az-A19
OMap
Ag 42 A1 A0 Addre
AAs A4
A10 A9 Ag
A 0 o0000H

A12 A11
A1s A17 A16 A15 14 13
A14 0 0
0 0 00002H
00
0

00 0 0
******

knowledge

thrust for
n" An up
Microprocessor and Microcontroller 10-18 Serial Communication Interface.BYk

Do-D7 TxD
Reset out RxD
Reset
Clock out CLK

MO-RD RD

8251A
WR
WR
RxC From pulse
A2 A C/D generatoror
TxC timer

CS

A1g- CTS GND

mapped VO
Fig. 10.12.1 Interfacing of 8251A with 8086 in memory