Digital Logic

CACS105 – Assignment #03

Naming Convention: YourName_CRN_Asmt#03

1) Define Encoder and Decoder. Construct 8*3 Encoder and 3*8 Decoder.
2) Implement full adder circuit using Decoder.
3) Define Multiplexer and De-Multiplexer. Construct 8×1 MUX using 4×1 Mux and explain
with truth table.
4) Construct 8*1 MUX and 1*8 DMUX with required function table and Boolean
expression.
5) Implement FA using MUX.
6) Explain N-bit binary parallel adder. And why N-bit binary parallel adder is required?
7) Explain the drawbacks of HA. How FA overcome the drawbacks of HA? Explain.
8) What is parity generator? Explain even and odd parity generator.
9) What is parity checker? Implement even and odd parity checker using multiplexer.
10) Implement even and odd parity generator using multiplexer.
11) Define ROM. Implement the following combinational logic function using ROM.

A B F F
1 2

0 0 1 0

0 1 0 1

1 0 1 1

1 1 1 0

12) Differentiate between PLA and ROM. Implement the following:

i. F(A,B,C)=∑(1,3,5,6) (Using MUX)
ii. F1=∑(0,2,5) F2=∑(3,4,7) F3=∑(6,7) (Using ROM)
13) Implement the following with appropriate MUX:
i. F(A,B,C)=∑(1,3,5,6)
ii. F(A,B,C,D)=∑(0,1,3,4,8,9,15)
14) Define PLA. Implement the following functions using PLA
i. F1(A,B,C)=∑(3,5,6,7)
ii. F2(A,B,C,D)=∑(0,2,4,7)
15) Differentiate between Combinational logic circuits and Sequential logic circuits. Explain
the design procedure of combinational logic.
16) What is edge triggering and level triggering? Is flip-flop is edge triggering? Explain
17) What are the drawbacks of clocked RS flip-flop? Explain the operation of JK flip-flop
along with its circuit diagram, function table, characteristics table, and timing diagram.
 Digital Logic
CACS105 – Assignment #03

18) What is T-flip-flop? Explain T flip-flop with required circuit diagram and characteristics
table.
19) Explain about D flip-flop and SR flip-flop.
20) Construct JK flip flop with D flip-flop.
21) Define excitation table of flip-flop? Write excitation table of all the flip-flop.