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  • MJCET Electrical Engineering Practice Test (2016-17, II Sem

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    This document contains a practice test for a Digital Electronics and Design (DELD) course. It consists of 20 multiple choice and descriptive questions across 5 units: 1. Logic functions including DeMorgan's theorem, Karnaugh maps, and logic gate implementations. 2. Basic digital components like data selectors and CMOS inverters. 3. Binary arithmetic including excess-3 code and BCD subtraction. 4. Combinational and sequential circuits including flip flops, counters, and comparators. 5. Programmable logic devices including ROM, PLA, and state machines. The test was prepared by two faculty members to evaluate students in their second semester of

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    This document contains a practice test for a Digital Electronics and Design (DELD) course. It consists of 20 multiple choice and descriptive questions across 5 units: 1. Logic functions including DeMorgan's theorem, Karnaugh maps, and logic gate implementations. 2. Basic digital components like data selectors and CMOS inverters. 3. Binary arithmetic including excess-3 code and BCD subtraction. 4. Combinational and sequential circuits including flip flops, counters, and comparators. 5. Programmable logic devices including ROM, PLA, and state machines. The test was prepared by two faculty members to evaluate students in their second semester of

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    © All Rights Reserved
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    34 views2 pages

    MJCET Electrical Engineering Practice Test (2016-17, II Sem

    Uploaded by

    Sajid Uddin
    This document contains a practice test for a Digital Electronics and Design (DELD) course. It consists of 20 multiple choice and descriptive questions across 5 units: 1. Logic functions including DeMorgan's theorem, Karnaugh maps, and logic gate implementations. 2. Basic digital components like data selectors and CMOS inverters. 3. Binary arithmetic including excess-3 code and BCD subtraction. 4. Combinational and sequential circuits including flip flops, counters, and comparators. 5. Programmable logic devices including ROM, PLA, and state machines. The test was prepared by two faculty members to evaluate students in their second semester of

    Copyright:

    © All Rights Reserved
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    of 2

    Muffakham Jah College of Engineering and Technology

    Electrical Engineering Department


    Practice Test (2016-17, II Sem)
    Subject: DELD (EE304) Class: B.E ¾ EEE and EIE

    QUESTIONS

    UNIT-1

    1. State and explain Demorgan’s Theorem. (2M)


    2. Simplify using Boolean Algebra Y=A[B+C(AB+AC)]. (2M)
    3. Using K-Map, find minimal SOP expressions for the following logic functions.
    (5+5)

    a) F= 𝐴, 𝐵, 𝐶, 𝐷 0,1,2,3,7,8,10,11,15 .

    b) F= 𝐴, 𝐵, 𝐶, 𝐷 1,5,12,13,14,15 + 𝑑(7,9).

    4. a) Find the complement of the function F=XYZ+ X YZ by finding the dual of the function.
    (4M)
    b) Implement NOT, AND, OR, NOR, XOR and XNOR using minimum number of NAND
    gates. (6M)

    UNIT-2

    5. Explain what is data selector? (2M)


    6. Draw a CMOS inverter and explain its operation. (3M)
    7. Obtain the prime implicant chart for the following logic function and obtain the minimal
    expression (10M)
    F= 𝐴, 𝐵, 𝐶, 𝐷, 𝐸 = 0,1,2,3,4,5,10,14,15,20,21,24,25,26,27,28,29,30 .
    8. a) Design a 4 to 16 decoder using 3 to 8 decoders. (5M)
    b) Explain TTL family. (5M)

    UNIT-3

    9. Perform 4+3 in Excess-3 code. (2M)


    10. Perform the following decimal subtraction in BCD by 9’s complement method 679.6 –
    885.9 (3M)
    11. a) Realize a 4- bit carry look ahead adder. (7M)
    b) Design one –bit comparator and explain its operation. (3M)
    12. Design decimal to ex-3 code converter. (10M)

    UNIT-4

    13. Explain Race around condition. (2M)

    14. Distinguish between combinational and sequential circuits. (3M)


    15. Design a following count sequence 0,1,3,2,6,4,5,7 and repeat using D Flip – Flop. (10M)

    16. Convert the following


    a) JK flip flop – T flip flop. (5M)
    b) RS flip flop – D flip flop. (5M)

    UNIT -5

    17. Implement the following Boolean function using ROM.


    F1(A,B)= 𝑚(0,2,3) and F2(A,B)= 𝑚(1,3) (3M)

    18. Distinguish between PAL and PLA. (2M)


    19. Design and draw the PLA implementation of the combinational circuit whose truth table is
    (10M)
    INPUTS OUTPUTS
    X Y Z F1 F2
    0 0 0 1 1
    0 0 1 0 1
    0 1 0 0 1
    0 1 1 1 0
    1 0 0 1 0
    1 0 1 0 0
    1 1 0 1 0
    1 1 1 1 1

    20. a) Draw the state diagram of the following state table. (5M)
    Present Next State Output
    State X=0 X=1 X=0 X=1
    AB AB AB Y Y
    00 00 10 0 0
    01 01 00 0 0
    10 11 10 0 1
    11 01 11 0 0

    b) Find the number of flip flops required to generate the sequence 1101011 and write its
    state table using D flip flop. (5M)

    Prepared by: 1) Mrs. Narjis.B. Sr. Asst. Prof. EED.

    2) Mr. Md. Umair Quadri. Asst. Prof, EED

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