SESSION SESI 1 : 2021/2022

INFORMATION
TECHNOLOGY & DFC10093 COMPUTER SYSTEM
COURSE
COMMUNICATION ARCHITECTURE
DEPARTMENT ASSESSMENT
CASE STUDY 2
METHOD

TOPIC TOPIC 1

APPROVED BY:
CHECKED BY:
PREPARED BY: (Head of
CLO (Course Coordinator/
(Course Lecturer) Department/ Head
Head of Programme)
of Programme)

CLO 1 : Explain computer

function in central
processing unit, arithmetic,
logic and assembly
language in computer 29/10/21
21
system. ( C2 , PLO 1 ) (HAWARIYAH BINTI (HAZILA BINTI
RAHIM) HASAN)

NAME : __________________________________________
REGISTRATION NO. : __________________________________________ 28
Answer all question.

1. Convert 1110101.110112 to hexadecimal. C2 (2 marks)

2. Convert 37.3128 to binary. C2 (2 marks)

3. Represent – 7210 as 2’s complement. C2(3 marks)

4. Demonstrate the operation below by using 2’s complement. C2
- 3510 + 4710 (5 marks)

5. Illustrate a logic gate circuit for the simplified expression. C2

(AB + C)D (4 marks)

6. a) List the truth table for SR flip-flop with positive edge below. C1 ( 2 Marks )
b) Illustrate timing diagram based on the table. C2 ( 2 Marks )

S R Q
0 1 0 init
0 0
1 0
0 1
0 0
 CLK

QSR

7. Refers to below timing diagram. Illustrate the output for QJK with positive edge, and Q .
T

Assume Q is 0. C2 (8 marks)
0

QJK

QT