MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

PS21964-T
INTEGRATED POWER FUNCTIONS
600V/15A low-loss 5th generation IGBT inverter bridge for
three phase DC-to-AC power conversion

INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS

• For upper-leg IGBTS : Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection.
• For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC), Over temperature protection (OT).
• Fault signaling : Corresponding to an SC fault (Lower-leg IGBT), a UV fault (Lower-side supply) or an OT fault (LVIC temperature).
• Input interface : 3V, 5V line (High Active).
• UL Approved : Yellow Card No. E80276

APPLICATION
AC100V~200V three-phase inverter drive for small power motor control.

Fig. 1 PACKAGE OUTLINES (PS21964-T) Dimensions in mm

A B
38 ±0.5
20×1.778(=35.56) TERMINAL CODE
0.28 3.5
35 ±0.3 1. NC
1.778 ±0.2 16-0.5 1.5 ±0.05 2. VUFB
3. VVFB
0.4

4. VWFB
5. UP
(1)

17 1 6. VP
7. WP
8. VP1
9. VNC *
14.4 ±0.5

10. UN
(3.3)

11. VN
(3.5)

12. WN
13. VN1
29.2 ±0.5
24 ±0.5

14. FO
15. CIN
.6
QR Type name 0.8
16. VNC *
R1 17. NC
14.4 ±0.5
12

2- Code Lot No. 18. NC

HEAT SINK SIDE 19. NC
3 MIN 20. N
21. W
22. V
18 25 23. U
0.4

8-0.6 4-C1.2 24. P

0.28
25. NC
2.54 ±0.2
(0~5°)

14×2.54 (=35.56) 2.5 MIN

0.5 0.5 1.5 M

IN
0.5 0.5 (2.656)
9.5±0.5

(1.2)
5.5±0.5

(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A DETAIL B

*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.

Mar. 2009
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 2 LONG TERMINAL TYPE PACKAGE OUTLINES (PS21964-AT) Dimensions in mm

A B
38 ±0.5
20×1.778(=35.56) TERMINAL CODE
0.28 3.5
35 ±0.3 1. NC
1.778 ±0.2 16-0.5 1.5 ±0.05 2. VUFB
3. VVFB

0.4
4. VWFB
5. UP

(1)
17 1 6. VP
7. WP
8. VP1
9. VNC *

14.4 ±0.5
10. UN

(3.3)
11. VN

(3.5)
12. WN
13. VN1

29.4 ±0.5
24 ±0.5
14. FO
15. CIN
.6
QR Type name 0.8
16. VNC *
R1 17. NC

14.4 ±0.5
12

2- Code Lot No. 18. NC

HEAT SINK SIDE 19. NC
3 MIN 20. N
21. W
22. V
18 25 23. U
0.28 4-C1.2 24. P
0.4
8-0.6
2.54 ±0.2 25. NC
14×2.54 (=35.56)

(0~5°)
2.5 MIN
0.5 0.5
0.5 0.5
1.5 M
IN
(2.656)
14±0.5

(1.2)
5.5±0.5

(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.

Fig. 3 ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21964-CT) Dimensions in mm

A B
38 ±0.5 3.5 TERMINAL CODE
20×1.778(=35.56) 1. NC
1.5 ±0.05
0.28 35 ±0.3 2. VUFB
1.778 ±0.2 16-0.5 3. VVFB
0.4

4. VWFB
5. UP
0.4

6. VP
(1)

17 1 7. WP
8. VP1
±0.5

9. VNC *
18.9

10. UN
14.4 ±0.5

11. VN
12. WN
(3.5)
33.7±0.5

13. VN1
14. FO
29.2 ±0.5
24 ±0.5

15. CIN
16. VNC *
.6
QR Type name 0.8
17. NC
R1 18. NC
14.4 ±0.5
12

2- Code Lot No. 19. NC

HEAT SINK SIDE 20. N
3 MIN 21. W
22. V
23. U
(0~5°)

18 25 24. P
0.4

4-C1.2 25. NC
0.28 8-0.6
2.54 ±0.2
14×2.54 (=35.56)
(0~5°)

0.5
1.5 M
0.5 0.5 (2.656) IN
±0.5

(1.2)
9.5
5.5±0.5

(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A DETAIL B

*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.

Mar. 2009

2
 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 4 BOTH SIDES ZIGZAG TERMINAL TYPE PACKAGE OUTLINES (PS21964-TW) Dimensions in mm
A B
38 ±0.5
3.5
20×1.778(=35.56) TERMINAL CODE
1.5 ±0.05
0.28 35 ±0.3 1. NC
1.778 ±0.25 16-0.5 2. VUFB

0.4
3. VVFB
4. VWFB
5. UP

(1)
17 1 6. VP

0.4
7. WP
8. VP1

17.4 ±0.5
9. VNC *

14.4 ±0.5
10. UN
11. VN

(3.5)
12. WN
13. VN1

35.2 ±0.6
29.2 ±0.5
24 ±0.5
14. FO
15. CIN
.6
QR Type name 0.8
16. VNC *
R1 17. NC

14.4 ±0.5
12

2- Code Lot No.

17.4 ±0.5
18. NC
HEAT SINK SIDE 19. NC
3 MIN 20. N

0.4
21. W
22. V
(1.8)

18 25 23. U

(0~5°)
0.28 7-0.6 4-C1.2 24. P
25. NC

0.4
2.54 ±0.25

(0~5°)
14×2.54(=35.56) 2.5 MIN

0.5
1.5 M
0.5 0.5 IN
(2.656)
11±0.5

(1.2)
5.5±0.5

(1.2)
(2.756)
HEAT SINK SIDE
DETAIL A DETAIL B
*) Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open. QR Code is registered trademark of DENSO WAVE INCORPORATED in Japan and other countries.

Fig. 5 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)

CBU–

CBV–

CBW–
CBU+

CBV+

CBW+

High-side input (PWM)

C1 : Electrolytic type with good temperature and frequency (3V, 5V line) (Note 1, 2)
characteristics C2
(Note : The capacitance value depends on the PWM control C1
Input signal Input signal Input signal (Note 6)
scheme used in the applied system). conditioning conditioning conditioning
C2 : 0.22~2µF R-category ceramic capacitor for noise filtering.
Level shifter Level shifter Level shifter
(Note 5)
Protection
circuit (UV)
Inrush current
limiter circuit Drive circuit Drive circuit Drive circuit

P
H-side IGBTS
DIPIPM
AC line input
U
(Note 4) V
W M
(Note 7)
AC line output

Z C
N1 N
L-side IGBTS
VNC
CIN
Z : Surge absorber Drive circuit
C : AC filter (Ceramic capacitor 2.2~6.5nF)
(Note : Additionally, an appropriate line-to line Input signal conditioning Fo logic Protection Control supply
surge absorber circuit may become necessary circuit Under-Voltage
depending on the application environment). protection

Low-side input (PWM) FO (Note 6)

(3V, 5V line)(Note 1, 2) Fault output (5V line)
(Note 3) VNC VD
(15V line)
Note1: Input logic is high-active. There is a 3.3kΩ (min) pull-down resistor built-in each input circuit. When using an external CR filter, please make it satisfy the
input threshold voltage.
2: By virtue of integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer
isolation is possible. (see also Fig. 11)
3: This output is open drain type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 10kΩ resistor.
(see also Fig. 11)
4: The wiring between the power DC link capacitor and the P, N1 terminals should be as short as possible to protect the DIPIPM against catastrophic high
surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to
these P & N1 DC power input pins.
5: High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit.
6: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
7: Bootstrap negative electrodes should be connected to U, V, W terminals directly and separated from the main output wires.

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 6 EXTERNAL PART OF THE DIPIPM PROTECTION CIRCUIT

DIPIPM
Short Circuit Protective Function (SC) :
SC protection is achieved by sensing the L-side DC-Bus current (through the external
Drive circuit
P shunt resistor) after allowing a suitable filtering time (defined by the RC circuit).
When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned
OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is
recommended to stop the system when the Fo signal is received and check the fault.
IC (A)
SC Protection
H-side IGBTS Trip Level
U
V
W
L-side IGBTS
External protection circuit

N1 Shunt Resistor A N
(Note 1)
VNC
C R Drive circuit
CIN
B Collector current
Protection circuit waveform
C
(Note 2) 0
Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2 tw (µs)
2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.

MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Symbol Parameter Condition Ratings Unit
VCC Supply voltage Applied between P-N 450 V
VCC(surge) Supply voltage (surge) Applied between P-N 500 V
VCES Collector-emitter voltage 600 V
±IC Each IGBT collector current TC = 25°C 15 A
±ICP Each IGBT collector current (peak) TC = 25°C, less than 1ms 30 A
PC Collector dissipation TC = 25°C, per 1 chip 33.3 W
Tj Junction temperature (Note 1) –20~+125 °C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIPIPM is 150°C (@ TC ≤ 100°C). However, to en-
sure safe operation of the DIPIPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C).

CONTROL (PROTECTION) PART

Symbol Parameter Condition Ratings Unit
VD Control supply voltage Applied between VP1-VNC, VN1-VNC 20 V
VDB Control supply voltage Applied between VUFB-U, VVFB-V, VWFB-W 20 V
Applied between UP, VP, WP, UN, VN,
VIN Input voltage –0.5~VD+0.5 V
WN-VNC
VFO Fault output supply voltage Applied between FO-VNC –0.5~VD+0.5 V
IFO Fault output current Sink current at FO terminal 1 mA
VSC Current sensing input voltage Applied between CIN-VNC –0.5~VD+0.5 V

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

TOTAL SYSTEM
Symbol Parameter Condition Ratings Unit
VD = 13.5~16.5V, Inverter part
VCC(PROT) Self protection supply voltage limit 400 V
(short circuit protection capability) Tj = 125°C, non-repetitive, less than 2µs
TC Module case operation temperature (Note 2) –20~+100 °C
Tstg Storage temperature –40~+125 °C
60Hz, Sinusoidal, 1 minute,
Viso Isolation voltage 1500 Vrms
Between pins and heat-sink plate

Note 2: TC measurement point

Control terminals

11.6mm
3mm

IGBT chip position

TC point
FWD chip position
Heat sink side

Power terminals

THERMAL RESISTANCE
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Rth(j-c)Q Junction to case thermal Inverter IGBT part (per 1/6 module) — — 3.0 °C/W
Rth(j-c)F resistance (Note 3) Inverter FWD part (per 1/6 module) — — 3.9 °C/W
Note 3 : Grease with good thermal conductivity should be applied evenly with about +100µm~+200µm on the contacting surface of DIPIPM and
heat-sink.
The contacting thermal resistance between DIPIPM case and heat sink (Rth(c-f)) is determined by the thickness and the thermal con-
ductivity of the applied grease. For reference, Rth(c-f) (per 1/6 module) is about 0.3°C/W when the grease thickness is 20µm and
the thermal conductivity is 1.0W/m·k.

ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted)

INVERTER PART
Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
Collector-emitter saturation VD = VDB = 15V IC = 15A, Tj = 25°C — 1.70 2.20
VCE(sat) V
voltage VIN = 5V IC = 15A, Tj = 125°C — 1.80 2.30
VEC FWD forward voltage Tj = 25°C, –IC = 15A, VIN = 0V — 1.70 2.20 V
ton 0.70 1.30 1.90 µs
trr VCC = 300V, VD = VDB = 15V — 0.30 — µs
tc(on) Switching times IC = 15A, Tj = 125°C, VIN = 0 ↔ 5V — 0.50 0.75 µs
toff Inductive load (upper-lower arm) — 1.60 2.20 µs
tc(off) — 0.50 0.80 µs
Collector-emitter cut-off Tj = 25°C — — 1
ICES VCE = VCES mA
current Tj = 125°C — — 10

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

CONTROL (PROTECTION) PART

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VD = VDB = 15V Total of VP1-VNC, VN1-VNC — — 2.80 mA
VIN = 5V VUFB-U, VVFB-V, VWFB-W — — 0.55 mA
ID Circuit current
VD = VDB = 15V Total of VP1-VNC, VN1-VNC — — 2.80 mA
VIN = 0V VUFB-U, VVFB-V, VWFB-W — — 0.55 mA
VFOH VSC = 0V, FO terminal pull-up to 5V by 10kΩ 4.9 — — V
Fault output voltage
VFOL VSC = 1V, IFO = 1mA — — 0.95 V
VSC(ref) Short circuit trip level Tj = 25°C, VD = 15V (Note 4) 0.43 0.48 0.53 V
IIN Input current VIN = 5V 0.70 1.00 1.50 mA
OTt Over temperature protection VD = 15V, Trip level 100 120 140
°C
OTrh (Note 5) At temperature of LVIC Trip/reset hysteresis — 10 —
UVDBt Trip level 10.0 — 12.0 V
UVDBr Control supply under-voltage Reset level 10.5 — 12.5 V
protection Tj ≤ 125°C
UVDt Trip level 10.3 — 12.5 V
UVDr Reset level 10.8 — 13.0 V
tFO Fault output pulse width (Note 6) 20 — — µs
Vth(on) ON threshold voltage — 2.1 2.6 V
Vth(off) OFF threshold voltage 0.8 1.3 — V
Applied between UP, VP, WP, UN, VN, WN-VNC
ON/OFF threshold hysteresis
Vth(hys) 0.35 0.65 — V
voltage
Note 4 : Short circuit protection is functioning only for the lower-arms. Please select the external shunt resistance such that the SC trip-level is
less than 1.7 times of the current rating.
5 : Over temperature protection (OT) outputs fault signal, when the LVIC temperature exceeds OT trip temperature level (OTt). In that case
if the heat sink comes off DIPIPM or fixed loosely, don’t reuse that DIPIPM. (There is a possibility that junction temperature of power chips
exceeded maximum Tj (150°C)).
6 : Fault signal is asserted only corresponding to a SC, a UV or an OT failure at lower side, and the FO pulse width is different for each fail-
ure modes. For SC failure, FO output is with a fixed width of 20µsec(min), but for UV or OT failure, FO output continuously during the
whole UV or OT period, however, the minimum FO pulse width is 20µsec(min) for very short UV or OT period less than 20µsec.

MECHANICAL CHARACTERISTICS AND RATINGS

Limits
Parameter Condition Unit
Min. Typ. Max.
Mounting screw : M3
Mounting torque Recommended : 0.69 N·m 0.59 — 0.78 N·m
(Note 7)
Weight — 10 — g
Heat-sink flatness (Note 8) –50 — 100 µm
Note 7 : Plain washers (ISO 7089~7094) are recommended.

Note 8: Flatness measurement position

Measurement position
+ – 4.6mm

Heat sink side

–
+
Heat sink side

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

RECOMMENDED OPERATION CONDITIONS

Limits
Symbol Parameter Condition Unit
Min. Typ. Max.
VCC Supply voltage Applied between P-N 0 300 400 V
VD Control supply voltage Applied between VP1-VNC, VN1-VNC 13.5 15.0 16.5 V
VDB Control supply voltage Applied between VUFB-U, VVFB-V, VWFB-W 13.0 15.0 18.5 V
∆VD, ∆VDB Control supply variation –1 — 1 V/µs
tdead Arm shoot-through blocking time For each input signal, TC ≤ 100°C 1.5 — — µs
fPWM PWM input frequency TC ≤ 100°C, Tj ≤ 125°C — — 20 kHz
VCC = 300V, VD = VDB = 15V, fPWM = 5kHz — — 7.5
IO Allowable r.m.s. current P.F = 0.8, sinusoidal PWM, Arms
Tj ≤ 125°C, TC ≤ 100°C (Note 9) fPWM = 15kHz — — 4.5
PWIN(on) Allowable minimum input 0.5 — —
µs
PWIN(off) pulse width (Note 10) 0.5 — —
VNC VNC variation Between VNC-N (including surge) –5.0 — 5.0 V
Note 9 : The allowable r.m.s. current value depends on the actual application conditions.
10 : IPM might not make response if the input signal pulse width is less than the recommended minimum value.

Fig. 7 THE DIPIPM INTERNAL CIRCUIT

VUFB
HVIC P

VP1 VCC VUB IGBT1 Di1

UP UP UOUT

VNC COM VUS U

VVFB VVB IGBT2 Di2

VP VP VOUT

VVS V

VWFB VWB IGBT3 Di3

WP WP WOUT

VWS W

IGBT4 Di4
LVIC
UOUT

VN1 VCC

IGBT5 Di5

VOUT

UN UN

VN VN IGBT6 Di6

WN WN
WOUT

Fo Fo CIN
VNO
VNC GND N

CIN

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 8 TIMING CHART OF THE DIPIPM PROTECTIVE FUNCTIONS

[A] Short-Circuit Protection (Lower-side only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current.
a2. Short circuit detection (SC trigger).
a3. IGBT gate hard interruption.
a4. IGBT turns OFF.
a5. FO outputs (tFO(min) = 20µs).
a6. Input “L” : IGBT OFF.
a7. Input “H” : IGBT ON.
a8. IGBT OFF in spite of input “H”.

Lower-side control a6 a7
input

Protection circuit state SET RESET

Internal IGBT gate

a3
a2

SC a4
a1
Output current Ic a8
SC reference voltage
Sense voltage of the
shunt resistor

CR circuit time
constant DELAY
Error output Fo a5

[B] Under-Voltage Protection (Lower-side, UVD)

b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied.
b2. Normal operation : IGBT ON and carrying current.
b3. Under voltage trip (UVDt).
b4. IGBT OFF in spite of control input condition.
b5. FO outputs (tFO ≥ 20µs and FO outputs continuously during UV period).
b6. Under voltage reset (UVDr).
b7. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET

RESET

UVDr
Control supply voltage VD b1 UVDt b6
b3

b4
b2 b7

Output current Ic

Error output Fo
b5

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

[C] Under-Voltage Protection (Upper-side, UVDB)

c1. Control supply voltage rising : After the voltage level reaches UVDBr, the circuits start to operate when next input is applied.
c2. Normal operation : IGBT ON and carrying current.
c3. Under voltage trip (UVDBt).
c4. IGBT OFF in spite of control input signal level, but there is no FO signal outputs.
c5. Under voltage reset (UVDBr).
c6. Normal operation : IGBT ON and carrying current.

Control input

Protection circuit state RESET SET RESET

UVDBr
Control supply voltage VDB c1 UVDBt c5
c3

c2 c4 c6
Output current Ic

High-level (no fault output)

Error output Fo

[D] Over Temperature Protection (Lower-side, OT)

d1. Normal operation : IGBT ON and carrying current.
d2. LVIC temperature exceeds over temperature trip level (OTt).
d3. IGBT OFF in spite of control input condition.
d4. FO outputs during over temperature period, however, the minimum pulse width is 20µs.
d5. LVIC temperature becomes under over temperature reset level.
d6. Circuits start to operate normally when next input is applied.
Control input

Protection circuit state SET RESET

OTt
LVIC temperature d2 d5

OTrh
d1 d3 d6
Output current Ic

Fault output Fo d4

Fig. 9 RECOMMENDED MCU I/O INTERFACE CIRCUIT

5V line

10kΩ DIPIPM

UP,VP,WP,UN,VN,WN

MCU
3.3kΩ (min)
Fo

VNC(Logic)

Note : The setting of RC coupling at each input (parts shown dotted) depends on the PWM control scheme and the
wiring impedance of the printed circuit board.
The DIPIPM input section integrates a 3.3kΩ (min) pull-down resistor. Therefore, when using an external fil-
tering resistor, pay attention to the turn-on threshold voltage.
Fig. 10 WIRING CONNECTION OF SHUNT RESISTOR

DIPIPM
Wiring inductance should be less than 10nH.
Equivalent to the inductance of a copper
pattern in dimension of width=3mm,
VNC thickness=100µm, length=17mm

N
Shunt resistor

Please make the GND wiring connection

of shunt resistor to the VNC terminal
as close as possible.

Mar. 2009

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 MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>

PS21964-T/-AT/-CT/-TW
TRANSFER-MOLD TYPE
INSULATED TYPE

Fig. 11 AN EXAMPLE OF TYPICAL DIPIPM APPLICATION CIRCUIT

C1: Electrolytic capacitor with good temperature characteristics
C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering

C2 C1 C2 C1 C2 C1

Bootstrap negative
electrodes should be
connected to U, V, W
terminals directly and
separated from the
VUFB VVFB VWFB main output wires.
P
HVIC
VP1
VCC VUB
C3
UP UP UOUT
U
VUS

VVB
VP
VP VOUT
V
VVS M

VWB
WP WOUT
WP
MCU

VNC W
COM VWS

LVIC
UOUT
VN1
VCC
5V line C3

VOUT
UN
UN
VN
VN
WN Long wiring here might
WN
WOUT cause short-circuit.
Fo
Fo
N
VNC
GND
C
CIN

Long GND wiring here might B R1

15V line Shunt
generate noise to input and C4
cause IGBT malfunction. resistor
A
N1
Long wiring here might cause SC
level fluctuation and malfunction.

Note 1 : Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the
wiring of each input should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on
and turn-off threshold voltage.
2 : Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
3 : FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.
4 : To prevent erroneous protection, the wiring of A, B, C should be as short as possible.
5 : The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4.
6 : All capacitors should be mounted as close to the terminals of the DIPIPM as possible. (C1: good temperature, frequency character-
istic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)
7 : To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.
8 : Two VNC terminals (9 & 16 pin) are connected inside DIPIPM, please connect either one to the 15V power supply GND outside and
leave another one open.
9 : It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended
to connect control GND and power GND at only a point.

Mar. 2009

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