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BATCH NO-06

Date:28 -09-2022

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY-GURAJADA,


VIZIANAGARAM
PROJECT STATUS REPORT-1
COURSE NAME: B. TECH (Electronics and Communication Engineering)
PROJECT NAME: Design and Development of 32-Bit Hybrid Adders in
VLSI Environment

DATE STATUS DETAILS


AUG 3rd COMPLETED Project batches division.

AUG7th-AUG15th COMPLETED Selection of the required domain to perform the Project.


AUG15th-AUG22nd COMPLETED Study of different papers based on the domain of the
project.
AUG22nd-AUG30th COMPLETED Base paper identification.

SEP2nd-SEP10th COMPLETED Study of the reference papers related to the base


paper.

SEP15th-SEP20th COMPLETED Identification of tools required for the project.

SEP20th-SEP25th COMPLETED Preparation of Abstract for the Project


development based on understanding of base
paper.
SEP26th-OCT7th IN PROGRESS Learning of the tools required for project implementation.

DATE STATUS DETAILS


OCT10th-OCT17th Yet to be completed Completion of the pre-processing steps for project
development.
OCT17th-OCT30th Yet to be completed Block diagram implementation mentioned in the Base
paper.
OCT31th-NOV10th Yet to be completed Identification of parameters, Result and Analysis of the
project.

PROJECT MEMBERS:
U. Chandrika(20VV5A0468)
PROF. K. BABULU
A. Ganesh (19VV1A0419)
(Project Supervisor)
Y. Surya Chandra Rao(19VV1A0463)
G. Bhuvana Siri(19VV1A0420)
K. Alex Joshi(19VV1A0432)

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