workbook 2023 a Detailed Explanations of Try Yourself Questions Electronics Engineering Computer Organization bs Ges) MADE ERSYMachine Instructions and Addressing Modes Detalled Explanation of Try Yourself Questions (16383) © 6 6 Opcade | Rs | Re | immedita — 2 —-s 82-(6 +6 +6) = 14 bits for immediate field 2°41 = 16383 maximum possible value of immediate operand Panera) (d) wif our | peo Qe o18E © " 100 ‘Stack Just before CALL instruction execution, SP contains 016E While CALL execution: (PC contents are pushed ie., SP incremented by 2 SP = 0170 (a) PSW contents are pushed ie., SP incremented by 2 SP = 0172 The value of stack pointer is (0172), “wwwmadeeasypublications.org MADE EASY ‘© Copyright )MADE EASY Detailed Explanations of Try Yourself Questions : GATE 2023 3 ry (ce) EA = PC + Address field value EA = 38248 + (12) = 38236 a are (b) Number of registers = 128 Number of bits = log 128 =7 Opcode | Register| index adcress| bis bis 7+20bEs In indexing addressing mode effective memory location is stored in register. So Index Address bit = Register bit + Address bit = 7420=27 +7427 = n+34is length of the instruction. Poe cay (ec) The given instruction is stored in 16 bits fegister. The first byte (lower byte) of the instruction store at the memory location 4002 and second byte (higher byte) stored at 4003, When we use litte-endian mechanism the lower byte of the instrunction is copied into lower byte of the register and higher byte of the instruction is copied into higher byte of the register. Higher byte_[ TFC OAH) denotes that the number fs in Hexa decimal form Conte ema me — Lower byte When we use big endian mechanism the lower byte of the instruction is copied into higher byte of the register and higher byte of the instruetion is copied into lower byte of register. ‘OAFCH Poe cay (500) 4 ——______, ‘opcode [ Reg | Reg | Reg |12bit immediate aut iStCiSSC 2 One instruction size = 34 bit = 5 bytes 100 instruction occupies 500 bytes. a © Copyright MADE EASY ‘wwrn.madeeasypublications.org4 Electronics Engineering © Computer Organization & Architecture MFIDE ERSY (b) Average of time = {(0.2 x 0) + (0.2 x 0) + (0.2 x 4) + (0.1 x8) + (0.17 x6) + (0.13 x 6)) =3.4 cycles 1 Clock eycletime = ;GHz= ins So, average of ime = 3.4 cycles x 1ns = 3.4ns J operand 3.4ns Number of operands in 1 soc Number ofoperands = 12284 9 20411 x 10° r lumber of operands = SPSS x 10° operandisee Operand fetch rate = 294.11 million words/sec iy (a) * Indirect addressing — Passing array as parameter. © Indexed addressing — Array implementation, * Base register addressing — Writing relocatable code. ‘wowwmadeeasypublications.org MADE EASY ‘© CopyrightALU, data-path and Control Unit Detalled Explanation f Try Yourself Questions Perey (a) Average CPI = Z{IC x CPI) cycle time: (45000 1) + (82000 x 2) + (15000 x 2) + (8000 x 2) Totaal IG = otaalic “45000 +-32000 + 15000 +8000 = 1.85 cycles Cycle time SOC = 0.0125 psec 1 S0MHZ Average instruction ET = (1.55 x 0.0125) = 0.019975 usec instruction = 0.019376 usec Number of instructions int sec Number finstructions = ———— x 108 inst./se = 1.61 MIPS (c) In the given u-program we have used the register MAR, MBR and Instruction Register (IR). IRisused only during fetching of the instruction. Hence operation is instruction fetching, Pees (b) Configurations for CPU in decreasing order of operating speeds: Hardwired control > Horizontal micro- programming > Vertical micro-programming (slowest because it involves decoding). © Copyright MADE EASY www madeeasypublications.org )6 Electronics Engineering © Computer Organization & Architecture MFIDE ERSY (10) Atmost 2 control signals are active, that means for one signals minimum log (2) bits required i.e. § For 2 control signals = § x 2 = 10 bits required. ~ | wermadeeasypublications org MADE EASY ‘© CopyrightInstruction Pipelining Detalled Explanation of Try Yourself Questions a (4) Pipe depth Speed uelS) = 77 ¥siallsjinsiruction) Number of stalisfinstruction = 0.75 x0 +025 x 2=05 Pane tcay (c) Clock eycle times Maximum of stage delays. For P14; clock cycle time = Maximum is 2 For P2; clock eycle time = Maximum is 1.5 For P3: clock cycle time = Maximum is 1 For P4: clock oycle time = Maximum is 1.1 Minimum clock cycle time gives the high clock rate, Minimum of (2, 1.5, 1, 1.1) = 4 P3 has peak clock cyole rate © Copyright MADE EASY wwwmadeeasypublications.org8 Electronics Engineering © Computer Organization & Architecture MFIDE ERSY (3.2) Non-pipelined processor: For ninstructions execution time = (nx 4) /2.6 = 1.6 nanoseconds Pipelined processor: For n instructions execution time = n/2 = 0.5 n nanoseconds. Speedup = 16n/05n=32 (e) Ss 5 [a s[a[a[4 So total 1Sinstruction are executed. K = 4:n=18,t,=4ne ET = (Ken-1 +h, = (44 13-1) 4ns = 64s ec,] 66; 60, [cos] eo, | 0, 6c, | co, | 66, [6c] te | 1D | oF | aril ex | ma | we 4 iF | [aw | oF | ex | nea | we hf iF [ar | 10 | oF | ex | ma | we Poe cay (33.28) Pj: 4-stage f, = Max (stage delay) 800 ps 1 instruction — 800 ps ‘7 number of instruction —1 sec TPalthroughput) = 1250 instruction/sec P, stage 4, = 600ps 1 instruction — 600 ps 7 number of instruction — 1 sec TPpx(thvoughput) = 1666 instruction’sec ‘wowwmadeeasypublications.org MADE EASY ‘© CopyrightMADE EASY Detailed Explanations of Try Yourself Questions : GATE 2023 9 1250 — 100% (old) (1666 - 1250) — ? (New) 416 AIS. = osaze > 7280 ie, 33.28% (4) Given that, 3 stage pipeline with stage latencies 5 oe, = 32, Ste ye ae Tih = 94g: =8:3 Ratio of t,: t,: 18 6r, Bx, Sx respectively, So, largest stage time Br. 1 $0, caleulate frequency = > quency = = a = sane Bx = 1 ~ 2aehe () Now, largest stage latency dlivide into 2 half parts i.e., 8x divide into 4x and 4x. So, 4 pipeline with stage latencies are x, 4x, 4x, 3x. Now, largest stage lime = Gr So, calculate new frequency 1 =4GHz O|R P= 1 te 2 =24GHe ttomea. 1] . (copyright MADE EASY vemmadeeaspubtonsorg