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Full name and IC No: Ruvenderan A/l Suburamaniam Date: 27/01/2023

Assignment (Asgmt) Declaration Form

Semester/Year Jan 2023
Student’s Name Ruvenderan A/L Suburamaniam
Student’s ID No: 041200053
Course Code TEL301/03
Course Title ELECTRONIC SYSTEMS PACKAGING
Class Code ESP1-3C
Assignment No: 1
No. of pages of this Assignment 10
(including this page)

Tutor MANDEEP SINGH A/L JIT SINGH

Course Coordinator Ir. Dr. Arjuna Bin Marzuki

T-DF Assignment Declaration Form (1/2020 version #003)

Question 1

a) (i) Signal distribution packaging.

The demand for power chips and modules is growing in products such as motor drives, solar
inverters, and power supplies, and that’s driving the need for greater power density without
increasing the package size.

How can designers accomplish the increase in power density while maintaining package
robustness and reliability? For a start, a package can have a larger lead frame area and thus
accommodate bigger power chips like insulated-gate bipolar transistors (IGBTs). It also results
in lower thermal resistance of the package, which facilitates improved heat dissipation.

Take the case of STMicro’s new system-in-package (SiP) that incorporates four power
MOSFETs in a package that is 60% smaller than a comparable circuit The PWD13F60 package
integrates gate drivers for the power MOSFETs, a bootstrap diode for high-side driving, cross-
conduction protection, and undervoltage lockout.

(ii) Signal distribution packaging.

If silicon chips are simply wrapped in the packaging material? For example, like toffees with
chocolate inside? To protect them from the external environment, they will be unable to
exchange signals with the outside. Attaching metal "legs" consisting of a lead frame (soldered
balls in the case of BGA) allows signals to be sent to semiconductor devices from outside, and
the processing results are accessed.

(iii) Heat dissipation (cooling) packaging.

Silicon chips heat up when in operation. If the temperature of the actual chip becomes too high,
the chip will malfunction. However, packages can effectively release this heat. And in the case of
semiconductor devices that give off especially high levels of heat, such as the CPUs mounted in
a PC, heat release can be induced by mechanisms such as a heat sink or cooling fan.

(iv) Circuit protection packaging.

Moisture and dust in the air are direct causes of semiconductor device defects and vibration and
shock. Lighting and magnets may also cause malfunctions. One function of a package is to
prevent such problems from occurring. In other words, packages shut out external influences and
serve to protect silicon chips.
 (v) Ease of Handling packaging.

Semiconductor devices demonstrate their functions once directly mounted on printed circuit
boards. However, the delicacy of circuits built into silicon chips means they cannot easily be
handled due to their minute size. Terminals are therefore enlarged to a size that makes them
much easier to handle and mount on the chips with more space in between, allowing them to be
connected to a printed circuit board.

b) (i) Level 0 Packaging

Thin-film wires (interconnections) within semiconductor IC chips are an important packaging
component. With integration levels at silicon steadily increasing, an increasing percentage of
wires previously provided by the packaging structures outside the chips have migrated into the
IC chip. However, all interconnections on an IC chip or all internal structures of any other
component (e.g., a crystal or those of discrete capacitors and inductors) are not considered
packaging in the common term.

(ii) Level 1 Packaging

Packaging begins at the interfaces to ICs and other components. The interfaces are the exterior
surfaces of the silicon die itself. The IC chip has an enclosure, commonly referred to as a Single
Chip Module (SCM), a chip carrier, or a header. This is an essential and much-diversified level
of packaging known as Semiconductor Packaging. This package has to make electrical
connections available to the input/output points on the bare die, provide a low thermal resistant
path to the outside world for conducting the heat generated in the silicon die, and provide the
necessary protection to the silicon die from the environment. The single-chip modules (SCMs)
can be broadly classified into the four categories:

• In-line packages
• Small outline packages
• Quad packages
• Array packages

(iii) Level 2 Packaging

Level 2 packaging may be called chipset packaging. In the past, this was represented by hybrid
microcircuit technology. Hybrid microcircuits combined active and passive devices on ceramic
substrates using thick-film or thin-film technologies. Hybrids continue to be used in mixed-
signal (analog and digital) and power control (regulators for alternators in automobiles)
applications and military electronics. The modern hybrid microcircuits are known as multi-chip
modules (MCM). There are three MCM technologies based on the substrate used and
interconnection technologies. MCM-D technology uses a deposited thin-film substrate for
interconnection and chip mounting. MCM-C uses a cofired or thick-film ceramic substrate, and
MCM-L employs a printed circuit board style substrate and interconnections.

(iv) Level 3 Packaging

Groups of chips (packaged in SCMs or MCMs), along with other components such as capacitors,
resistors, inductors, filters, switches, and optical and RF components, are assembled, usually on
copper-clad sheets of epoxy-glass laminates. After patterning the metallic sheet followed by
mechanical drilling and lamination to form interconnections, such structures are commonly
called "printed wiring boards" (PWB) or cards.

(v) Level 4 Packaging

This level of packaging refers to the integration of printed wiring board(s) with items for user
interface (displays, keyboards, etc.), power and signal connections between level-3
subassemblies and to the external world, special components (transformers, CRTs, fans, etc.),
and the protective enclosure into a product. There may be several boards within the box/frame of
large equipment. All the items needed to construct the product must be interconnected
mechanically through racks and electrically with cables and connectors. Larger equipment will
require special cooling arrangements, and some may require special vibration-free mounting. All
these items will be of concern in the thirdlevel packaging.

The continuing increases in the number of circuits or bits per IC chip simplify the packaging
hierarchy. There is even a trend to integrate all functions in a single chip leading to a "system on
chip." However, the performance of a product/system is only as good as the weakest link.
Therefore, the challenge is to ensure that packaging does not reduce the system's performance.
Packaging cannot add to the performance of the products, but it can have adverse effects if it is
not adequately taken care of. At the first and second level packages (SCMs and MCMs)), the
continuing demand for higher performance products is demanding levels of performance
unattainable by the molded plastic and ceramic packages of the past decade. Higher performance
requirements at the third level packages lead to printed circuit board technologies that use micro
vias (with diameters less than 150 microns) and ever decreasing interconnection line widths.

Question 2
a) (i) Chip carrier.

A chip carrier houses the elements of an integrated circuit or a transistor. It is also commonly
known as a chip package or chip container. This packaging enables the chips to be plugged into
or soldered onto a circuit board without damage to their delicate elements. The process of
installing chip carriers has become increasingly intricate as they have decreased in size to
accommodate new forms of technology.

Depending on the design of a chip carrier, it is typically attached to a circuit board by being
plugged in, held in with springs, or soldered. Carriers with plugs, also known as socket mounts,
have pins, or leads, which can be pushed directly into the board. When a carrier is soldered
directly onto the board, it is called a surface mount. The spring mounting method is used when
the force of soldering or pins will damage fragile components. A spring mechanism is installed
in the area where the component is to be installed; then the springs are carefully pushed aside so
that the piece can be locked into place.

Depending on the design of a chip carrier, it is typically attached to a circuit board by being
plugged in, held in with springs, or soldered. Depending on the design of a chip carrier, it is
typically attached to a circuit board by being plugged in, held in with springs, or soldered. There
are dozens of different types of chip carriers, made with a wide array of materials. They can be
composed of a mix of elements including ceramics, silicone, metal, and plastic. The chips inside
also come in several different sizes and thicknesses, though they all tend to have a square or
rectangular shape. Chip carriers come in an array size that is standardized by the electronics
industry. They are classified based on the number of terminals in the carrier.

New, smaller designs of technology such as cell phones and computers have made it necessary to
manufacture the typical chip carrier in increasingly tinier sizes. Some have become so miniscule
that they can no long be installed by human hands. Instead, it is now an intricate, mechanically-
performed process. A chip carrier with plugs tends to be larger and more suited to human
handling, while surface mount carriers are often installed via machine.

The installation of chip carriers onto a circuit board is part of a larger assembly process known as
integrated-circuit packaging. It is also known by various other terms in the electronics industry,
including packaging, assembly, and semiconductor device assembly. Other tasks during this
process include die attaching, integrated circuit bonding and integrated circuit encapsulation.
These processes work to attach, and then provide protection for, all of the elements on the circuit
board.

(ii) Lead frame base package.

A lead frame is a generic term for a type of (mostly) low-cost IC package assembly used for DIL
types packages as well as PLCCs and QFNs.

The frame is typically made of a thin layer of copper, though other materials, such as aluminum
and even gold, have been used. The die is glued to the frame; conductive adhesives are common,
as a die substrate is typically ground, though non-conductive die attach is also possible; the
adhesive can be dispensed by syringe – the most common method – or an adhesive tape can be
applied; the die is placed onto the frame and the die pad wire bonded to the leads; as can be seen
in the image copied below, the leads are not in direct contact with the die pad; not shown is the
outer metal of the frame that holds the leads in place; this is cut, sawn or etched away when the
package body has been formed (molded) to keep the leads in place.

The leads then carry the signals and power to and from die to the outside of the package. If the
lead frame is copper the exposed leads of the package are plated with nickel or tin (or gold) to
avoid oxidation. The package body itself is typically a plastic or resin compound, though ceramic
bodies are also possible especially if the assembly will generate or be subjected to high-
temperatures.

Manufacturing of Lead Frame

The frames are formed on a flat plate of metal, with multiple frames connected together.
Segregation, as mentioned earlier, is achieved by punching, sawing or etching. Etching is used
for high density leads as is can give much closer tolerances and finer detail; high-density QFN
(close to die size) type assemblies are typically etched. For low lead density and larger package
assemblies the preferred process is stamping, which is usually employed in high volume
production runs. The process of stamping is automated and runs at a very high speed, allowing
you to deal with high loads and volumes and distribute the initial tooling costs which may be too
much for low volume productions.

(iii) In line package.

 One of the earliest packaging standards was the rectangular DIP. It has been the mainstream of
the microelectronics industry since 1968 and still accounts for some 80% of all integrated circuit
packaging. The DIP has I/O leads that extend from two opposite sides of the package and are
bent downward. In all of these packages, there is a microelectronic circuit with on-chip pads.

`Leadless' pertains to electronic devices that do not have electrical leads extending from their
enclosures but rather to solder `lands' or `bumps located on the package's top, bottom, or sides.
With the advances in VLSI technology, the lower available pin counts of the rectangular DIP
have become a limiting factor. With pins spaced 2.4 mm apart on only two sides of 11 the
package, the physical size of the DIP has become too great. On the other hand, the physical size
of an unpackaged microelectronic circuit (bare die) has been reduced to a few millimeters,
leading to reduced power consumption and chip delay time due to greater circuit integration -
thus reducing the cost per circuit function. As a result, the DIP package has become up to 50
times larger than the bare die itself, thus defeating the objective of shrinking the size of the
integrated circuits.

It is the most common through-hole IC package used in circuits, especially hobby projects. This
IC has two parallel rows of pins extending perpendicularly out of a rectangular plastic housing.

The overall dimensions of a DIP package depend on its pin count. The most common pin counts
are four, six, eight, fourteen, eighteen, twenty, twenty-eight, and forty pins. The pins on a DIP IC
are spaced 2.54mm apart, which is a standard spacing, perfect for fitting into breadboards,
veroboards, and other prototyping boards.

A DIP IC can also be easily soldered on PCBs. Sometimes, an IC socket is used instead of
soldering an IC directly to the PCB. Using the socket allows for the DIP IC to be removed from
and inserted into the PCB easily.

Question 3
(a) three type of wire bonding process.
  Thermocompression Bonding: This process uses force, heat, and time to weld the two
materials via inter-diffusion. The wire (heated in some cases) gets pressed against a hot
surface (150°C or more). It occurs at high pressure for a limited period. But the process
uses no friction and only works on a gold wire and a gold bond surface.

 Ultrasonic Bonding: This requires pressure, ultrasonics, and time to weld the two
materials. The process involves pressing the wire against the surface at ambient
temperature. Additionally, it should be at a low force with vibration for a limited period
to create the bond. You can use this method with aluminum, gold, silver, palladium,
copper, or platinum (wire or ribbons). It has two forms: wedge and peg bonding.

 Thermosonic Bonding: This bonding process uses force (pressure), heat, ultrasonics,
and time to weld two materials. It should occur at low pressure and undergo vibration for
a limited period to create the bond. Usually heated in some cases, the wire gets pressed
on the hot surface (150°C or less). But like thermocompression bonding, the process only
works with gold wire and a gold bonding surface. However, it has three forms: gold ball
bonding, wedge bonding, and stud bumping (bump bonding).

(b) Ball Bonding

In ball bonding, the wire passes through a hollow capillary. After that, an EFO (Electronic
Flame-Off) system melts the small portion extending outside. The surface tension of the molten
wire forms a ball before the wire solidifies. Next, it gets pressed to the pad using sufficient force
to cause plastic deformation. The result is an intimate bond with the bond pad surface.
Ball bonding is the process in which pads are connected onto a die and lead frame (or substrate)
using very fine diameter wire. The basic steps of ball bonding include the formation of: the first
bond (normally on the chip), the wire loop, and the second bond normally on the substrate.

 At the beginning of the wire cycle, the bonding tool travels down to the first bond
location (Steps 1 and 2).
 The first bond is achieved by bonding a spherical ball to the pad using thermal and
ultrasonic energy (Step 3).
 The initial bond is also referred to as the ball bond. Looping motions are programmed to
meet the package requirement for loop height and shape (Steps 4, 5, and 6).
 The second bond consists of a stitch bond that bonds the opposite end of the wire and a
tail bond (Step 7).
  The tail bond is needed to form a wire tail for the next ball formation. After the bonding
tool rises to pay out the wire tail, the tail is broken off and the bonding tool rises up to the
ball formation height (Steps 8, 9, and 10).
 The ball formation process is achieved by ionization of the air gap in a process called
“electronic flame-off” (EFO). The resulting ball is known as a “free air ball” (FAB).

(c) Wedge Bonding

During wedge bonding, a clamped piece of wire is coupled under a bonding tool (referred to as a
wedge) and a bond pad. Pressure and ultrasonic energy are applied for a given period of time
forming a first wedge bond. The shape and dimensions of this bond are determined by the
dimensions of geometry of wedge (note bond parameters will also have an effect on the final
bond geometry).

The wire is guided through the wedge during this movement making a loop of wire between the
two bond locations. Controlling this movement can help determine the shape, height and length
of this loop. The wire is then guided through the wedge tool to the second bond location and the
pressure and ultrasonic energy are applied again to form the second bond location. The process is
completed by means of breaking the wire in preparation for the next wire bonding cycle, by
clamping the wire and movement of the wire.

Wedge bonding can be performed using Al, and Au wire with the addition of heating the
bonding surface and modifications to the wedge tools material construct and tip shape. Al wire
will use a concave tip shape made from tungsten carbide while Au wire will use a cross-groove
tip shape made from Titanium Carbide. Aluminum ultrasonic bonding is the most common
wedge bonding process because of the low cost and the low working temperature.
The main advantage of gold wire wedge bonding is the possibility of avoiding the need for
hermetic packaging after bonding due to the inert properties of the gold. In addition, a
wedge bond will give a smaller footprint than a ball bond, which specially benefits the
microwave devices with small pads that require a gold wire junction.