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KHOA CƠ KHÍ
BỘ MÔN CƠ ĐIỆN TỬ
KỸ THUẬT ĐIỆN TỬ
(Cho sinh viên ngành Cơ điện tử)
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Năm học: 2022 - 2023
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content – 30 hours
Chapter 1: Introduction
5. Internet
Introduction
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Mercoledì 27 maggio 2015
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Content
1. History
2. Popular electronic devices
✓ Passive devices
✓ Active devices
✓ Opto-Electronic devices
3. Voltage, current and fundamental laws
✓ Voltage and Current
✓ Voltage source and Current source
✓ Ohm law
✓ Kirchoff voltage law (KVL)
Dr. Dang
✓ Phuoc Vinh current
Kirchoff law (KCL)
Faculty of Mechanical Engineering
19
Symbols
Devices
Politecnico di Milano e Veneranda Fabbrica
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Classification
1. Passive device
2. Active device
3. Opto-Electronic devices
▪ Resistor
▪ Capacitor
▪ Inductor
▪ Relay
▪ …
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
39
Resistor
▪ Resistor: is a passive two-terminal electrical
component that implements electrical resistance as a
circuit element
▪ Resistivity is a fundamental property of a material that
measures how strongly it resists electric current.
R VR VR
R VR VR
Variable core
Air core
Iron core
Ferrite core
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
77
Exercises
1. Characteristics, functions and applications of
4 kinds of inductors?
E D C Dp
COM
A B C D E F G Dp
A B C D E F G Dp
E D C Dp
COM
CC: Common Cathode
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
Cathode chung
114
4-Digit Display
Gustav Kirchhoff
(1824 – 1887)
KỸ THUẬT ĐIỆN TỬ
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Firma convenzione
Năm học: 2022 - 2023
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content
Chapter 1: Introduction
▪ n>p
▪ p>n
▪ Unbiased
▪ Reverse Biased
▪ Forward Biased
▪ A voltage barrier is
generated.
– Ge: U = V ~ 0.3V
– Si: U = V ~ 0.6V
Equation of
Set UT = kT/q is the thermal voltage Diode characteristic
At 300 K: UT ~ 25.5 mV.
𝐼 = 𝐼𝑠 𝑒 𝑈/𝑈𝑇 − 1
Dark saturation current :
𝐦 = 𝟎. 𝟎𝟕𝟐 /°𝐂
𝐼𝑠 𝑡2 = 𝐼𝑠 (𝑡1 )𝑒 𝑚(𝑇2−𝑇1) 𝐈𝐬 𝟎 °𝐂 = 𝟏𝐞 − 𝟏𝟐;
▪ Reverse biased
▪ U remains
constant when
I change
▪ Working range
Dr. Dang Phuoc Vinh of ZenerFaculty
diodeof Mechanical Engineering
Avalanche breakdown? 37
Function?
V0 ?
V0 = 0, vs < VD0
V0 = (vs-VD0)R/(R+rD)
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
55
Half Wave Rectifier
V0 ?
D1
D2
D4
D3
V0 ?
D1
D2
D4
D3
𝐙𝟏
𝐙𝟐
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
Voltage Regulator IC
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Voltage Regular IC
1. IC provides fixed voltage
▪ Positive voltage regular – 78XX
▪ Negative voltage regular – 79XX
2. IC provides variable voltage
Voltage regulator IC
Input voltage: Ui ≤ 35 V
Ui > Uo + 3
Input voltage : Ui ≤ 35 V
Ui > Uo + 2 ÷ 3 Out
In
Ground
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
83
Positive voltage – 78XX
Input voltage:
Ui ≤ 35 V
Ui > Uo + 2 ÷ 3
Input voltage : Ui ≤ 35 V
Ui > U o + 3
𝐑𝟐
𝐑𝟏
KỸ THUẬT ĐIỆN TỬ
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Firma convenzione
Năm học: 2022 - 2023
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content
Chapter 1: Introduction
IE IC IE IC
- UCE + + UEC -
E E C
C
- - + +
VBE VBC VEB IB VCB
IB
- -
+ +
B B
IE = IB + IC IE = IB + IC
UCE = -VBC + VBE UEC = VEB - VCB
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
25
Specifications
• IE = IB + IC
• Ratio of the collector current to the 𝐼
= 𝐼𝐶 → IC = IE
emitter current 𝐸
• Current gain:
𝐼𝐶 IC = IB
𝛽= (𝛽 100 with low-power BJT)
𝐼𝐵
IE IC
= IC / (IE – IC) = / (1- ) E
- UCE +
C
= / ( + 1) - -
IB = (1 - )IE VBE IB VBC
+ +
IE = (1 + 𝛽)IB B
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
26
Specifications
50 A
β? β = IC / IB = 1 mA / 0.05 mA = 20
= IC / IE = 1 mA / 1.05 mA = 0.95238
?
= β / (β + 1) = 20/21 = 0.95238
IB
µA Q V UCE RC
RB
VB VCC
𝑰𝑩 = 𝟎 𝝁𝑨
𝑽𝑪𝑬 (𝑽)
VB = 3 V ; RB = 10 kΩ
VC = 5 V ; RC = 1 kΩ
VBE = 1 V ; VCE Sat = 0.1 V
β(hFE) = 100 𝐕𝐁
• Determine IB ; IC ; VCE
• Power consumption? E
𝐕𝐂 = 5V 𝑉𝐵 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸
𝑉𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸
RC = 1 kΩ
𝑉𝐵 − 𝑉𝐵𝐸 3 − 1
𝐼𝐵 = = = 0.2 mA
𝑅𝐵 10 kΩ
𝐕𝐁 = 3V
Wrong Assumption
𝐕𝐂 = 5V 𝑉𝐵 = 𝐼𝐵 𝑅𝐵 + 𝑉𝐵𝐸
𝑉𝐶 = 𝐼𝐶 𝑅𝐶 + 𝑉𝐶𝐸
RC = 1 kΩ Suppose that BJT works in the
Saturation Region
𝑉𝐶𝐸 = 𝑉𝐶𝐸(𝑆𝐴𝑇) = 0.1 𝑉
𝐕𝐁 = 3V
𝑉𝐵 − 𝑉𝐵𝐸 3 − 1
𝐼𝐵 = = = 0.2 mA
𝑅𝐵 10 kΩ
RB = 10 kΩ 𝑉𝐶 − 𝑉𝐶𝐸(𝑠𝑎𝑡) 5 − 0.1
𝐼𝐶(𝑆𝐴𝑇) = = = 4.9 mA
𝑅𝐶 1 kΩ
𝐼𝐶(𝑠𝑎𝑡) 4.9
E Re-check: 𝐼𝐵(𝑠𝑎𝑡) = = = 0.049 mA
𝛽 100
𝐼𝐵 > 𝐼𝐵(𝑠𝑎𝑡) Suitable Assumption
Vc 𝐼𝐵 = 0.2 𝑚𝐴 ; 𝐼𝐶 = 4.9 𝑚𝐴
𝑃𝐵𝐽𝑇 = 𝐼𝐵 𝑉𝐵𝐸 + 𝐼𝐶 𝑉𝐶𝐸
= 0.2 × 1 + 4.9 × 0.1 = 0.69 mW
4.9 mA
Power consumption on load:
𝑃𝑅𝐶 = 𝑅𝐶 𝐼𝐶2
= 1kΩ × 4.9mA 2 = 24.01 mW
Power consumption on system:
𝐕𝐁 𝑃 = 𝑃𝑅𝐵 +𝑃𝑅𝐶 +𝑃𝐵𝐽𝑇
= 𝑅𝐵 𝐼𝐵2 + 𝑅𝐶 𝐼𝐶2 + 𝐼𝐵 𝑉𝐵𝐸 + 𝐼𝐶 𝑉𝐶𝐸
0.2 mA
E = 25.1 mW
𝑃𝑅𝐶 24.01
Efficiency: 𝜂 = = = 95.00%
𝑃 25.1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
41
Example 2
BJT in the circuit as shown in figure is Vc
2SC1815 type with following specifications:
VB = 3 V ; RB = 100 kΩ
VC = 5 V ; RC = 1 kΩ
VBE = 1 V ; VCE Sat = 0.1 V
β(hFE) = 100 𝐕𝐁
• Determine IB ; IC ; VCE
• Power consumption? E
Vc 𝐼𝐵 = 0.02 𝑚𝐴 ; 𝐼𝐶 = 2 𝑚𝐴
𝑃𝐵𝐽𝑇 = 𝐼𝐵 𝑉𝐵𝐸 + 𝐼𝐶 𝑉𝐶𝐸
= 0.02 × 1 + 2 × 3 = 6.02 mW
2 mA
Power consumption on load:
𝑃𝑅𝐶 = 𝑅𝐶 𝐼𝐶2 = 1kΩ × 2mA 2 = 4 mW
circuit)
▪ Q point
VB = 5 V ; RB = 107.5 kΩ.
VC = 10 V ; RC = 1 kΩ.
Vγ = 0.6 V ; β = 100.
• Calculate IB ; IC ; UCE 𝐕𝐁
• Determine Q point?
E
UCE (V)
5.9 10
– Q Point
• Q locates in the middle of the DC load line → BJT works stable.
𝑉𝐶𝐶 − 𝑈𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + 𝑅𝐶 (1 + 𝛽)
▪ Q point
▪ IB decreases → IC decreases
• A’ → A
• Circuit has thermal stability
Một mạch tuyến tính hay phức tạp có thể thay thế dòng và điện áp nguồn
bằng một mạch tương đương có chứa một điện áp độc lập VTH và một điện
trở nối tiếp RTH.
VTH = 8 V
RTH = 766.67 Ω
𝑉𝐵 −𝑈𝐵𝐸
𝐼𝐵 =
𝑅𝐵 + 1 + 𝛽 𝑅𝐸
We can have:
𝑅𝐸
▪ 𝑉𝐶𝐶 = 𝑅𝐶 + 𝐼𝐶 + 𝑈𝐶𝐸
𝛼
𝛽
where α = 1+𝛽
▪ Q point
IC
Vùng bão
hòa
Vùng
khuếch đại
A
AB
B iB=0
E C
C E
B ra B ra
vào B ra
vào E vào C
Rn rBE=rp iB it
RC Rt
ur
O
uv
RB
en
rv iE Rr
Rv
RB = R1//R2 E
iE
Rn it
iB
RC Rt
ur
uv
RE
en
rv Rr
Rv
B
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
92
C-C Type Circuit
• RB1, RB2: for the BJT biasing. VCC
• RC: resistor of C terminal.
RB1 RC
• RE: resistor of E terminal.
• Rt: resistor of load.
Q
• en, Rn: value and inside C1
Rn
resistor of supply power. RB2 RE
C2
Rt
• C1, C2: input and output en
capacitor → blocking DC and
allowing AC signal.
Rn
rBE=rp iB
E
iE
uv
RB RC
en it
ur
rv R Rt
Rv E
Rr
RB = R1//R2
O
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
Applications
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Application: Amplifier
𝜷𝒕𝒐𝒕𝒂𝒍 = 𝜷𝟏 + 𝜷𝟐 +𝜷𝟏 𝜷𝟐
𝑰𝑪 = 𝜷𝑰𝑩
KỸ THUẬT ĐIỆN TỬ
(Cho sinh viên ngành Cơ điện tử)
Firma convenzione
Năm học: 2022 - 2023
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content
Chapter 1: Introduction
Applications
Aula Magna – Rettorato
Mercoledì 27 maggio 2015
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Content
▪ What is an OPAMP?
▪ Applications:
1. Comparator
2. Inverting & Non- Inverting Amplifier
3. Voltage Follower
4. Inverting & Non- Inverting summing Amplifier
5. Differential Amplifier
6. Differentiator Amplifier
7. Integrator Amplifier
8. Instrumentation Amplifier
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
5
OPAMP
▪ OPAMP (Operational Amplifier)
i-
Inverting input
▪ G : Gain of OPAMP.
i(+), i(-) : input ▪ Idea OPAMP: G = ∞
current of OP-AMP at
▪ 𝑅𝑜𝑢𝑡 : output resistance
inverting and non-
inverting input -15V ▪ Idea OPAMP: R out = 0.
+𝐕𝐜𝐜
−𝐕𝐜𝐜
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
17
Inverting amplifier
𝐼𝑖 = 0 𝐼𝑓
𝑈𝑖 = 0
𝐼𝑖𝑛 𝐼𝑖
X
𝑈𝑖
Virtual
Earth
X
𝐼1 𝐼2
𝑅1 = ∞
𝑅2 = 0
𝑉𝑜𝑢𝑡 = 𝑉𝑖𝑛
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
20
Inverting Summing Amplifier
𝐼1
𝐼2
𝐼𝑓
𝐼𝑛
𝐼2
𝐼𝑛
𝐼2
𝐼𝑔
𝐼𝐶
X
𝐼𝑅
X
𝑉𝑜𝑢𝑡2 𝑅 𝑉𝑋 𝑅
Dr. Dang Phuoc Vinh 6 of Mechanical Engineering
Faculty 7
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Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
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TRƯỜNG ĐẠI HỌC BÁCH KHOA
KHOA CƠ KHÍ
BỘ MÔN CƠ ĐIỆN TỬ
KỸ THUẬT ĐIỆN TỬ
(Cho sinh viên ngành Cơ điện tử)
Firma convenzione
Năm học: 2022 - 2023
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
MercoledìTS. Đặng Phước
27 maggio 2015 Vinh
Email: dpvinh@dut.udn.vn
2
Content
Chapter 1: Introduction
Fundamental of
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Digital Electronics
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Content
1. Basic of Digital Electronic
2. Algebraic Logic
BCD 8421
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
22
Binary to Hexadecimal
1101 0101 1100 1111 → D5CF
0b1101 0101 1100 1111
0xD5CF
A B C D E F G Dp
E D C Dp
COM
F G B
A B C D E F G Dp
E C
1 0 0 1 1 0 0
D
0b.0001.1001
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
25
7 segment LED
Logic Sum
0+0=0 0+1=1 1+0=1 1+1=1
x+0=x x+1=1 x+x=x x + xത = 1
Logic Product
0.0 = 0 0.1 = 0 1.0 = 0 1.1 = 1
x.0 = 0 x.1 = x x.x = x x.തx = 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
29
Laws of Boolean
Commutative (hoán vị) Absorptive (hấp thu)
x+y=y+x x + x.y = x
x.y = y.x x.(x+y) = x
A B Output
A.B = Y 0 0 0
0 1 0
Ex: Burglar alarm = AND
1 0 0
(alarm switch ; door).
1 1 1
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
A B Output
0 0 0
0 1 0
1 0 0
1 1 1
A B Output
A+B=Y 0 0 0
▪ OR gates can also have 0 1 1
more than two inputs
1 0 1
1 1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
41
NOT gate
▪ Just one input and one output
▪ Giving an output which is the inversion of the
input → inverse gate
▪ Giving a “1” output when input is “0” and vice
versa.
Input Output
1 0
0 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
43
NAND gate
▪ Can be considered as a combination of an AND
gate followed by a NOT gate
▪ Output is “0” only when input A and B are “1”
▪ Symbol: the AND symbol followed by a circle
A B Output
0 0 1
A.B=Y 0 1 1
1 0 1
1 1 0
A B Output
0 0 1
A+B=Y
0 1 0
1 0 0
1 1 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
47
XOR gate
▪ XOR stands for exclusive OR
▪ Output will be “1” when the inputs are different
▪ XOR operation is represented by the symbol
A B Output
0 0
ഥ 𝐁 + 𝐀𝐁
Y=A⊕B=𝐀 ഥ 0 1
1 0
1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
49
XNOR gate
▪ XNOR stands for exclusive NOR
▪ It is an XOR gate with its output inverted.
▪ XNOR operation is represented by the symbol (.)
A B Output
0 0
Y = A (·) B
= 𝐀+𝐁 ഥ . (𝐀
ഥ + 𝐁) 0 1
1 0
1 1
ഥ
𝐀
A ഥB
𝐀
B
𝐀 ഥ B+𝐀𝐁
ഥ
𝐀
ഥ
𝐁 ഥ
B 𝐀𝐁 A B Output
0 0
0 1
1 0
1 1
x.y.z
x.y.z
x.y.z
F
x.y.z
x.y.z
x.y.z
xy
00 01 11 10
zt
00
4-variable Karnaugh-map 01
11
10
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
61
Truth Table Expression
A B C S
0 0 0 0
0 0 1 0
0 1 0 1
ഥ 𝐂ത + 𝐀𝐁
𝐀𝐁𝐂ത + 𝐀𝐁
S= ഥ ഥ 𝐂 + ABC
0 1 1 0
1 0 0 1
1 0 1 1
Non-inverting variation → 1
1 1 0 0
Inverting variation → 0 1 1 1 1
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
62
Karnaugh - map
– Value of variations are expressed in blocks.
– Consecutive blocks have only one different variation.
Example: S = ABC + 𝐀 ഥ 𝐁𝐂ത + 𝐀𝐁 ഥ 𝐂ത
ഥ 𝐂 + 𝐀𝐁
A B C S
ഥ𝐁
AB 𝐀 ഥ ഥB
𝐀 AB ഥ
A𝐁 0 0 0 0
C 00 01 11 10 0 0 1 0
0 1 0 1 0 1 0 1
0
0 1 1 0
1 0 0 1 1
1 0 0 1
1 0 1 1
Not Consecutive Consecutive
1 1 0 0
Dr. Dang Phuoc Vinh Faculty of Mechanical Engineering
1 1 1 1
63
Rules
1. Groups may not include any cell containing a zero
ഥ 𝐂ത + 𝐀
𝐎𝐮𝐭 = 𝐀 ഥ 𝐃 + 𝐁𝐂ത + 𝐁𝐃
A
xy
00 01 11 10
zt A = z.t B = x. y.t
00 1 1 1 1 C = x.z.t D = x. y.t
01 1 F = A+ B +C + D
11 1 1 = z.t + x. y.t + x.z.t + x. y.t
10 1
Dr. Dang Phuoc Vinh
B C DMechanical Engineering
Faculty of
the END !
Firma convenzione
Politecnico di Milano e Veneranda Fabbrica
del Duomo di Milano
Aula Magna – Rettorato
Mercoledì 27 maggio 2015