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ADC/DAC loopback linearity testing by DAC output offsetting and scaling

Article  in  IEEE Transactions on Very Large Scale Integration (VLSI) Systems · October 2011
DOI: 10.1109/TVLSI.2010.2063443 · Source: DBLP

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011
ADC/DAC Loopback Linearity Testing by DAC
Output Offsetting and Scaling
Xuan-Lun Huang, Student Member, IEEE, and Jiun-Lang Huang, Member, IEEE
Abstract—Loopback testing is a powerful technique for testing
the analog-to-digital converter (ADC) and digital-to-analog con-
verter (DAC) pair embedded in a mixed-signal system-on-chip
(SoC). While attractive, its performance is generally limited by
the achievable test resolution and the potential fault masking
problem. In this work, a loopback linearity testing technique for
an ADC/DAC pair is presented; the key idea is to raise the effec-
tive ADC and DAC resolution by scaling the DAC output. First,
during ADC testing, we scale down the DAC output to achieve the
required test stimulus resolution and adjust the DAC output offset
to cover the ADC full-scale range. Then, for DAC testing, we raise
the effective ADC resolution by scaling up the DAC output. Both
simulation and measurement results are presented to validate the
proposed technique.
Index Terms—Analog-to-digital converter (ADC)/digital-to-
analog (DAC) testing, design-for-test (DfT), loopback testing,
mixed-signal testing, segmented current-steering DAC.
I. INTRODUCTION
W ITH the rapid evolution of semiconductor technolo-
gies, it is now common practice to integrate the
mixed-signal circuits with other digital cores into a single
system-on-chip (SoC) or system-in-package (SiP) [2], [3]. As
the interface between the analog world and the powerful digital
signal processing (DSP) systems, the analog-to-digital and
digital-to-analog data converters (ADCs and DACs) are the
most commonly used mixed-signal circuits in modern com-
munication and multimedia devices [4]–[6]. To catch up with
the fast data volume growth, the development of high-speed
and high-resolution data conversion techniques has never
stopped. While meeting the data bandwidth requirement, these
high-end converters also pose serious challenges to manufac-
turing testing because data converter testing mostly consists of
specification-based functional testing.
Since mixed-signal SoCs often contain both ADC and DAC,
the loopback testing methodology that directs the DAC output
to the ADC input (through some analog signal processing
Manuscript received March 04, 2010; revised May 23, 2010 and July 15,
2010; accepted July 18, 2010. Date of publication August 30, 2010; date of cur-
rent version August 10, 2011. This work was supported in part by the National
Science Council of Taiwan, under Grant NSC 98-2220-E-002-006. Preliminary
results of the proposed technique were published in the Proceedings of VLSI
Test Symposium, April, 2010.
The authors are with the Graduate Institute of Electronics Engineering
(GIEE) and the Department of Electrical Engineering, National Taiwan Univer-
sity, Taipei 10617, Taiwan and also with the Information and Communications
Research Laboratories, Industrial Technology Research Institute, Hsinchu
31040, Taiwan (e-mail: f93921028@ntu.edu.tw; jlhuang@cc.ee.ntu.edu.tw).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2010.2063443
1063-8210/$26.00 © 2010 IEEE
1765
path) so that they can test each other becomes a promising
solution to automatic test equipment (ATE) cost reduction.
While attractive, the loopback testing methodology is limited
by the achievable test resolution and the potential fault masking
problem. Over the years, several techniques have been devel-
oped to address these issues. In [7], Shin et al. presented a
loopback testing scheme that utilizes spectral predictors and a
simple analog filter on an external load board to estimate the
dynamic performance of data converters. Based on [7], Park
et al. developed a parallel loopback testing approach in [8].
These methods require intensive computation to derive the
dynamic performance parameters. For static linearity testing,
[9] proposed to first estimate the ADC linearity based on the
noise distribution. Then, the characterized ADC is employed
to test the DAC. Reference [10] proposed another noise-based
loopback testing scheme. It characterizes the DAC perfor-
mance with the spectral prediction technique [7], utilizes a
digital equalizer to compensate for the DAC nonlinearity, and
measures the ADC performance by the traditional histogram
method. To ensure test accuracy, these noise-based approaches
demand a large number of samples; this elongates the test
time. Another loopback linearity testing approach is proposed
in [11], Korhonen and Kostarnovaara employed the stimulus
error identification and removal (SEIR) technique [12], [13]
to characterize the static performance of the data converters.
A ramp signal and its offset version are first generated by the
DAC with a voltage shifter. These ramp signals are then used to
stimulate the ADC and their correlation can be used to derive
the nonlinearity errors. This work, however, is vulnerable to
noise and the offset voltage variation.
This work relates to the static linearity testing of ADC and
DAC in a loopback manner; the bottleneck is the insufficient
ADC or DAC resolution. [14], [15] allow testing ADC with low-
resolution current-steering DACs by utilizing the deterministic
dynamic element matching (DDEM) technique. To the contrary,
[16] utilized a low-resolution ADC with dithering to test high-
precision DACs, where the required dithering signal is gener-
ated by an additional DAC. These works are effective and help
reduce the ATE cost. However, they may incur unacceptable sil-
icon overhead.
In this paper, we propose a static ADC/DAC loopback
testing methodology for cases that utilize the segmented cur-
rent-steering DAC (SCS DAC). The key idea is to raise the
effective ADC and DAC resolution by properly scaling the
current-steering DAC output. During ADC testing, the SCS
DAC output is scaled down and offset by a set of dc values so
as to produce the ADC histogram testing stimulus. As for DAC
testing, the effective ADC resolution is improved by scaling up
1766 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011

the DAC output. Then, the ADC is utilized to test one current
source in the SCS DAC at a time. From the results, the DAC
input/output (I/O) transfer curve can be constructed assuming
that the current summation is ideal.
The contributions and advantages of the proposed loopback
testing methodology are as follows.
1) We propose to achieve the needed test resolution for static
ADC and DAC testing, including differential nonlinearity
(DNL) and integral nonlinearity (INL), by simply scaling
the DAC output. For SCS DAC, this can be easily realized
by adjusting the load resistance value.
2) The proposed technique is robust. The scaling factors and
the set of offset voltages need not be very accurate. Fig. 1. Six-bit segmented current-steering (SCS) DAC.
Both simulation and measurements on off-the-shelf ADC/DAC
show that the proposed technique achieves almost identical re-
sults to the conventional method. The limitation is that the DAC B. Linearity of DAC
must be of the segmented current-steering architecture. Let denote the DAC output voltage of code . One LSB,
The rest of this paper is organized as follows. In Section II, we which corresponds to the average voltage increment of the DAC,
briefly introduce the linearity specifications of data converters. is defined as
In Section III, the basic architecture and operation principle of
the SCS DAC is presented. In Section IV, we illustrate the pro-
posed technique in detail. In Section V, the impact of ADC/DAC (4)
nonlinearity is discussed. Simulation and experimental results
are given in Sections VI and VII, respectively. Finally, we con- where is the DAC resolution. DNL and INL of the DAC can
clude this paper in Section VIII. then be computed by the following equations:

(5)
II. LINEARITY OF DATA CONVERTERS
if
In this work, we use the endpoint line as the reference line (6)
if
and compute the endpoint DNL and INL [17]. For ADC testing,
the endpoint line connects the lowest and highest ADC transi-
tion voltages; for DAC testing, the endpoint line connects the
smallest and largest DAC output voltages. III. SEGMENTED CURRENT-STEERING DAC
The segmented current-steering (SCS) DAC is very popular
A. Linearity of ADC for high-performance applications. Internally, an -bit SCS
The ADC linearity is usually characterized by the linear his- DAC is divided into two segments: the unary-weighted segment
togram testing; a linear ramp of which the linearity is better than for the more significant bits and the binary-weighted seg-
the ADC by at least 3 bits is applied and the ADC output codes ment for the less significant bits.
are collected. Let be the number of occurrences of output The SCS DAC architecture combines the advantages of the
code . The average code hits, which corresponds to 1 LSB, is unary and binary-weighted architecture—the former relieves
defined as the output glitch problem; the latter reduces the circuit size.
Take the 6-bit SCS DAC in Fig. 1 for example. It has
and ; thus, it uses unary-weighted
(1) and and 4 binary-weighted cur-
rent sources that are related by
where denotes the ADC resolution. and
are invalid and thus excluded because their input ranges are not if
(7)
doubly bounded. DNL, the difference between the actual code otherwise.
width and the average one, can be computed by
While one can use to to directly control the binary-
weighted current sources to , a binary-to-thermometer de-
(2) coder is needed to generate the control signals to the unary-
weighted current sources ( , and ) from and . The
INL, the deviation of the actual code transition level from the total output current is directed to the load resister
ideal one, can be obtained by integrating DNL. to produce the output voltage .
It is worth noting that one can control the SCS DAC’s full
if scale range (FSR) by adjusting ; this forms the basis of the
(3)
if proposed ADC/DAC loopback testing technique.
HUANG AND HUANG: ADC/DAC LOOPBACK LINEARITY TESTING BY DAC OUTPUT OFFSETTING AND SCALING 1767

Fig. 3. Gain control block.

Fig. 2. Proposed ADC/DAC loopback testing architecture.

IV. PROPOSED ADC/DAC LOOPBACK TESTING TECHNIQUE

The proposed technique takes advantage of the fact that one
can adjust the SCS DAC’s load resistance to change its FSR.
When testing ADC, we use the SCS DAC to generate the ramp
stimulus and derive the ADC nonlinearity via the linear his-
togram approach. The proposed technique achieves the required
ramp resolution by scaling down the DAC FSR; this raises the
effective DAC resolution because there will be more DAC output Fig. 4. Offset control block.
voltages that fall inside each ADC code step. To compensate for
the reduced DAC FSR, a set of offset voltages are added to the
DAC generated ramps so as to cover the ADC FSR. As for DAC
testing, we use the ADC to test one current source at a time by
measuring the produced output voltage. To achieve the required
measurement resolution, the proposed technique scales up the
DAC output.
In the following, we will describe the hardware that supports
the proposed loopback methodology and the loopback testing Fig. 5. Covering ADC FSR with multiple segments.
flow. For ease of illustration, we make the following assump-
tions:
• ADC and DAC have the same FSR; this allows the down-scaled DAC outputs to cover the ADC’s
• ADC and DAC have the same number of bits. FSR. As shown in Fig. 5, without dc offset, the DAC generated
Note that, in general, one can apply the proposed technique to ramp only covers a small portion of the ADC FSR. By
other cases easily. using multiple ramps with different offset voltages, the ADC
FSR can be covered. Note that these dc offset voltages do not
A. Loopback Testing Architecture have to be very accurate as long as the ADC FSR is fully cov-
Fig. 2 depicts the proposed loopback testing architecture. The ered and there is sufficient overlap between adjacent segments
DAC under test is a current-output SCS DAC; it has a test en- to compensate for noise and offset voltage deviations. In Fig. 4,
able signal (TE) which allows turning on each current source the offset voltage is from the DAC and stored in the sample-and-
individually during DAC testing. The ADC under test, on the hold (S/H) unit. In practice, one may use an external dc source
other hand, can be of any architecture and needs no modifica- if readily available.
tion.
B. ADC Testing
The loopback path consists of the “gain control” and “offset
control” blocks. The gain control block is a simple resistor net- Fig. 6 depicts the proposed ADC testing flow. First, the gain
work as shown in Fig. 3, where ; it gener- control block (see Fig. 3) selects which is times smaller
ates scaled DAC outputs. During normal operation, is closed; than ; this scales down the DAC output by . Then, the
this directs the DAC output current to the normal load re- flow enters the partial histogram collection loop. In the th it-
sistor and produces output voltage . eration, the offset voltage is applied to the offset control
During ADC testing, is closed and is used to scale block. Then, we sweep the DAC input code and collect the cor-
down ; during DAC testing, is closed and is used responding ADC code hits, i.e., the number of times each code
to scale up . appears. Note that the DAC output only covers the range from
The offset control block (see Fig. 4) adds dc offset to the to , denoted by ; thus, the his-
DAC output. Using a set of properly selected dc offset values, togram obtained in iteration is a partial histogram, denoted by
1768 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011

Assuming that we use evenly spaced segments to

cover the ADC FSR, the overlap between adjacent ’s is

(8)

To compensate for the offset voltage deviations (with a max-

imum of ) and the noise (with a standard deviation of
), is selected to satisfy the following condition:

(9)

Clearly, must exceed to tolerate the offset

voltage deviations. The reason of adding the term
is according to the partial histogram truncation process which
removes codes from both ends of each partial histogram. Fi-
nally, the additional 1 LSB term ensures that one can derive the
full histogram by combining the truncated partial histograms.
4) Merging Truncated Partial Histogram: The full-code his-
Fig. 6. Proposed ADC loopback testing flow. togram is derived by continuously merging the trun-
cated partial histograms in which the noise affected code hits
have been removed. Note that the code hits corresponding to
, that characterizes the ADC behavior within input range the overlap between two consecutive partial histograms is de-
. The noise, if present, causes the ADC output code to de- termined by the latter one. Here is a simple example. Let
viate from its ideal value; this affects the accuracy of obtained denote the code hits of code in the partial histogram and
partial histograms, especially for the codes that are close to the denote that in the full-code histogram . After
segment boundaries. Furthermore, the offset voltages may de- all the partial histograms are collected, we first set
viate from their specified values. To tolerate these, the offset . If the truncated covers the ADC code hits from
voltages are properly selected so that adjacent segments overlap code 1 to 40, we have
sufficiently. To ensure test quality, in the “truncate ” stage,
the code hits that are more likely to be affected by noise are re- for to (10)
moved from the partial histogram . Finally, the partial his-
tograms are combined to obtain the full ADC histogram Then, the will be merged into . If the truncated
from which the ADC DNL and INL can be derived. covers the ADC code hits from code 36 to 75, we have
1) Choice of : The choice of determines the ADC test
for to (11)
resolution. Recall that we assume the ADC and DAC are both
-bit and have the same FSR (for ease of illustration). If one Note that to are updated by . This
uses the DAC to generate the test ramp without down-scaling, process iterates until all the partial histograms are merged into
i.e., , the average code hit would be merely one, which is ; once this is done, the ADC DNL and INL can be
apparent insufficient. Using the down-scaled DAC output, one derived.
improves the final average code hit by . In practice, should be
slightly larger than the desired average code hit when a perfect C. DAC Testing
ramp is applied; the reason is to compensate for the nonlinearity The proposed loopback testing technique utilizes the ADC to
associated with the DAC itself. test the DAC by measuring the output voltage produced by each
2) Truncating Partial Histograms: The presence of noise af- current source. Fig. 7 illustrates the DAC testing flow. First, the
fects the accuracy of partial histograms, especially for the codes gain control block selects which is times larger than
closer to the segment boundaries. Assume that the standard de- ; this scales up the DAC output by . Then, the flow en-
viation of noise is and let correspond to .( ters the current source testing loop. Each time, exactly one cur-
can be approximated by applying a dc voltage to the ADC and rent source is connected to . The corresponding scaled
analyzing the output code distribution after a sufficiently large output voltage is measured by the ADC and
number of samples.) Consider partial histogram and let stored. For an -bit SCS DAC that has unary-weighted
and be the maximum and minimum codes in more significant bits and binary-weighted less significant
that have non-zero code hits. The codes greater than bits, this loop repeats times. Once all the
or less than are removed from . current sources are measured, one can construct the full DAC
3) Choice of Offset Voltages: Apparently, ’s with I/O transfer curve (assuming that the summation is ideal) from
respect to the selected offset voltages must cover the ADC which the DAC DNL and INL can be derived.
FSR. In reality, there must be sufficient overlap between ad- 1) Choice of : Intuitively, by increasing , the relative
jacent ’s to tolerate imprecise offset voltages and noise. quantization error caused by the ADC becomes smaller; how-
HUANG AND HUANG: ADC/DAC LOOPBACK LINEARITY TESTING BY DAC OUTPUT OFFSETTING AND SCALING
Fig. 7. Proposed DAC loopback testing flow.
ever, is limited by the ADC FSR. When the largest current
source, i.e., a unary-weighted one, is tested, the resulting output
voltage must be within ADC FSR. According to (7), we have
(12)
Since the maximum DAC output covers the ADC FSR when
loaded with , we have
(13)
From (12) and (13) and , we have
(14)
Note that (14) also implies that the achievable test accuracy of
this DAC testing scheme is limited by the segmented current-
steering DAC architecture.
2) DAC Design for Testability: To realize the DAC test flow,
the binary-to-thermometer decoder is redesigned so that when
the TE (test enable) input is high, one can turn on the unary-
weighted current source under test by properly setting the
more significant bits.
V. PERFORMANCE ANALYSIS
While we can raise the effective ADC/DAC test resolution
by scaling down/up the DAC output, the achievable test accu-
racy is ultimately limited by the nonlinearity associated with
the ADC and DAC. Let be the DAC’s effective
number of bits. The effective ADC test resolution is approxi-
mately . If the DAC is highly nonlinear,
one can increase to maintain the required test accuracy at the
cost of elongated test time (because more segments are needed
to cover the ADC FSR). The analysis is similar for DAC testing.
However, since is upper bounded, the desired DAC test reso-
lution is not always attainable.
A. Impact of DAC Nonlinearity on ADC Testing
The ADC test accuracy is affected by the DAC nonlinearity.
Consider the example shown in Fig. 8, a DAC of which the max-
imum INL error equals LSB is depicted. The ADC code hit
1769
Fig. 8. DAC fault masking problem during ADC testing.
is to be measured in this example, and the circles denote
the ideal down-scaled DAC outputs. Ideally, there will be DAC
outputs within the code boundaries of , i.e.,
. The maximum estimation error occurs when the DAC out-
puts before/after ’s boundaries deviate the most from their
idea values. As illustrated by the triangles in Fig. 8, if these
DAC outputs fall out of the boundaries, will be reduced
to . Similarly, if the DAC outputs corresponding to the
squares in the figure fall into the code boundaries, will be
increased to . In both cases, the measured DNL error is
. By increasing , one can reduce the measurement error
and thus improve the test accuracy.
B. Impact of Analog Adder Nonlinearity on ADC Testing
The analog adder that performs the offsetting operations is
a negative feedback circuit based on the operational amplifier
(OPAMP). Up to now, we implicitly assume this adder is ideal.
In reality, this assumption fails if the OPAMP open-loop gain
is insufficient. In such a case, the closed-loop gain of the adder
varies with the input level (i.e., nonlinearity) and thus the code
hits obtained by each test segment will be erroneous. As a result,
to ensure the test quality, the adder must have higher linearity
than the ADC under test.
For on-chip implementation, the adder can be made of a
switched- capacitor based non-inverting amplifier. The gain
error of such an amplifier is approximately , where denotes
the OPAMP open-loop gain [18]. To test an -bit ADC, the adder
linearity should be at least bits. Thus, we have
(15)
From (15), the minimum requirement on in dB can be derived
as
(16)
For example, to test a 10-bit ADC, the OPAMP open-loop gain
should be greater than 84 dB to achieve the 13-bit adder linearity
requirement. Note that the adder linearity depends on the
desired test accuracy. Since the proposed ADC testing technique
focuses on the static performance, one can use a high-gain but
low-bandwidth OPAMP (which is relatively easy to design) to
realize the adder.
1770 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011

Fig. 9. ADC fault masking problem during DAC testing.

C. Impact of ADC Nonlinearity on DAC Testing

Fig. 9 shows how the ADC nonlinearity affects the DAC test Fig. 10. ADC testing simulation results. (LHS: ideal. RHS: proposed.)
accuracy. The current source to be measured is , and the DAC
outputs when loaded with and are and , re-
spectively. Suppose is a positive integer and is just equal
to the ideal transition level of the ADC code , the ideal
ADC output code for should be . If the ADC INL
error at this code is LSB, the actual ADC output code will
be . Normalized by , the measurement error is
. Apparently, one can reduce the measurement error
by increasing . Similar analysis can be applied for the noise on
the signal path; the noise-induced DAC measurement error can
also be reduced by a factor of through the proposed technique.

VI. SIMULATION RESULTS

We first perform numerical simulations to validate the pro-
posed technique. The FSR of the DAC output and the ADC
input are both 2 V. The ADC under test is a 10-bit one-bit/stage
pipelined ADC. In each stage, the capacitor mismatch is ran-
domly set to be within 1% and the comparator offset is randomly
assigned between 10 and 10 mV. The DAC under test is a
10-bit segmented current-steering DAC with and
; the deviation of each current source is randomly as-
signed and bounded by 7%. During testing, both scaling factors
and are set to 60.
A. Simulation Without Noise
During this simulation, “zero” noise is assumed to demon-
strate the maximum achievable test accuracy.
The ADC is first tested by an ideal 16-bit DAC with the tradi-
tional linear histogram testing. The measured INL and DNL are
shown in the left-hand side (LHS) plots of Fig. 10; the peak DNL
and INL are 2.71 and 2.24 LSB, respectively. Note that these re-
sults are considered as the ideal values. Then, the proposed ADC
loopback testing technique is applied. The estimated INL and
DNL are shown in the right-hand side (RHS) plots of Fig. 10; the
peak DNL and INL are 2.74 and 2.26 LSB, respectively. From
Fig. 10, it is easy to see that the DNL/INL values obtained by
the proposed technique are almost identical to the ideal values.
Finally, the DNL/INL estimation errors are shown in Fig. 11;
the errors are all less than 0.1 LSB.
Fig. 11. Simulated ADC test errors.
The DAC testing simulation results are shown in Fig. 12. On
the LHS of the figure are the actual DNL and INL plots of the
DAC; the peak DNL and INL are 0.95 and 3.35 LSB, respec-
tively. On the RHS of the figure are DNL and INL plots obtained
by the proposed technique; the peak DNL and INL are 0.94
and 3.34 LSB, respectively. The estimation errors are shown in
Fig. 13 and are all within 0.06 LSB of the actual values.
B. Simulation With Noise
Now, a Gaussian noise with standard deviation of 0.1 LSB is
injected into the signal path to assess the noise effect.
The ADC testing simulation results are shown in Fig. 14.
The LHS plots of the figure depict the actual ADC performance
measured without noise for comparison; the peak DNL and
INL are 2.71 and 2.24 LSB, respectively. On the RHS of
the figure are DNL and INL plots obtained by the proposed
technique; the estimated peak DNL and INL are 2.67 and
2.40 LSB, respectively. Although the peak DNL/INL are very
close to their actual values, the maximum estimation errors of
HUANG AND HUANG: ADC/DAC LOOPBACK LINEARITY TESTING BY DAC OUTPUT OFFSETTING AND SCALING
Fig. 12. DAC testing simulation results. (LHS: ideal. RHS: proposed.)
Fig. 13. Simulated DAC test errors.
Fig. 14. ADC testing simulation results considering noise. (LHS: ideal. RHS:
proposed.)
DNL and INL are significantly increased to 0.15 and 0.34
LSB as shown in Fig. 15. The noise induced error can be
1771
Fig. 15. Simulated ADC test errors considering noise.
Fig. 16. DAC testing simulation results considering noise. (LHS: ideal. RHS:
proposed.)
averaged out by taking more samples; however, this prolongs
the test time.
The DAC testing simulation results are shown in Fig. 16. The
LHS plots of the figure are the actual DAC performance; the
peak DNL and INL are 0.95 and 3.35 LSB, respectively. The
RHS plots of the figure are the estimated results obtained by
the proposed technique; the peak DNL and INL are 0.94 and
3.32 LSB, which are very close to their actual values. The es-
timation errors are illustrated in Fig. 17, they are all within
0.05 LSB. These results prove that the proposed DAC testing
technique is insensitive to noise as described in the previous
section.
C. Simulation With Various Scaling Factors
To evaluate how the scaling factors affect the test accuracy,
we sweep their values from 1 to 60, and record the corre-
sponding test errors as shown in Fig. 18. The LHS plots of the
figure depict the maximum absolute estimation errors of the
ADC testing, while the RHS plots of the figure depict those of
the DAC testing. As can be seen in this figure, the estimation
1772 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011
Fig. 17. Simulated DAC test errors considering noise.
Fig. 18. Maximum test errors with respect to different scaling factors. (LHS:
ADC. RHS: DAC.)
errors go down as the scaling factors increase. Furthermore,
when the scaling factors exceed 40, almost all the test errors
are within 0.1 LSB. This means that, by choosing appropriate
scaling factors, the variations in the gain control resistors only
cause negligible effect to the test accuracy; this demonstrates
the robustness of the proposed technique.
D. Simulation for ADC/DAC Nonlinearity Effect
The other term that dominates the achievable test accuracy is
the non-linearity of ADC and DAC. To assess its impact, we set
the scaling factors to 60, generate one thousand different ADCs/
DACs, measure their ENOB by 8192-point FFT (fast Fourier
transform), and record the corresponding test errors as shown
in Fig. 19. The LHS plots of the figure depict the maximum
absolute estimation errors of the ADC testing, while the RHS
plots of the figure depict those of the DAC testing. Obviously,
the test errors decrease as the ENOB of ADC/DAC increases;
this proves the correctness of the approximation described in
the previous section.
Fig. 19. Maximum test errors with respect to different ADC/DAC nonlinearity.
(LHS: ADC. RHS: DAC.)
Fig. 20. Simulation results of 1000 ADC/DAC pairs. (LHS: ADC. RHS: DAC.)
E. Simulation for 1000 ADC/DAC Pairs
Finally, to further validate our work, the proposed tech-
nique is applied to one thousand randomly perturbed 10-bit
ADC/DAC pairs. Fig. 20 shows the estimated peak DNLs/INLs
with respect to their actual values. The LHS plots of the figure
depict the ADC testing results; the estimated DNLs and INLs
match the actual values very well. On the other hand, the DAC
testing results are shown in RHS plots of the figure. In some
cases, the estimated DNLs deviate from their ideal values by al-
most 0.15 LSB. This is because the measurement errors in each
current source may be accumulated along the same polarity
while deriving the full DAC I/O transfer curve. Fortunately,
these errors tend to be canceled out during the INL calculation;
the measured DAC INLs match their actual values very well.
VII. EXPERIMENTAL RESULTS
Experiments on commercial ICs are also performed to fur-
ther validate the proposed technique. The ADC under test is a
HUANG AND HUANG: ADC/DAC LOOPBACK LINEARITY TESTING BY DAC OUTPUT OFFSETTING AND SCALING 1773

Fig. 21. ADC testing experimental results. (LHS: actual. RHS: proposed.)
Fig. 22. ADC testing errors.

10-bit pipelined ADC (ADS825 from TI). On the other hand, the
DAC under test is emulated using a 14-bit current-output DAC
(THS5671A from TI); it is a 10-bit SCS DAC with
and . The reasons to use an emulated DAC are as fol-
lows. First, we are unable to modify the binary-to-thermometer
decoder of commercial SCS DACs to realize the DAC test flow.
Secondly, this facilitates very flexible fault injection to the DAC.
In the experiments, each current source in the emulated DAC
is randomly perturbed by within 7% of its nominal value. The
ADC and DAC have the same FSR of 2 V and are both operated
at a sampling rate of 100 kHz.
The scaling factor is set to 25, and is set to 60; this is
achieved by setting and in Fig. 3 to 100 ,
4 , and 6 k , respectively. The offset control circuit is imple-
mented by an OPAMP-based (OPA228 from TI) analog adder,
and the required offset voltage is provided by NI DAQ (USB-
6259). The noise is measured by using the DAC to generate a dc Fig. 23. DAC testing experimental results. (LHS: actual. RHS: proposed.)
voltage and observe its distribution at the ADC input; the mea-
sured noise standard deviation is about 0.25 LSB.
B. DAC Testing Experimental Results
A. ADC Testing Experimental Results The actual performance of the emulated 10-bit DAC under
The ADC under test (ADC825) is first characterized by the test is first measured by NI DAQ which has a 16-bit resolu-
14-bit DAC (THS5671A) with the traditional linear histogram tion. Each DAC output is sampled “100” times to average out
testing. The LHS plots in Fig. 21 show the measured DNL and the noise effect. The LHS plots of Fig. 23 show the measured
INL; the peak DNL and INL values are 0.73 and 2.54 LSB, DNL and INL performance; the peak DNL and INL are 0.96
respectively. and 3.57 LSB, respectively.
The proposed loopback ADC testing technique is then ap- As the emulated 10-bit DAC has and ,
plied. Note that: 1) the 10-bit DAC is emulated using a 14-bit there are a total of emulated current sources.
one and is fault-injected and 2) the OPAMP we used in the The output voltage with respect to each of the emulated cur-
analog adder has a very high open-loop gain (160 dB) to en- rent sources (loaded by ) is digitized by the 10-bit ADC
sure the test quality. The measurement results are shown in RHS (ADS825), and each current source is only measured “once.”
plots of Fig. 21. The peak values of the estimated DNL and From the measured voltages, the DAC I/O transfer curve is con-
INL are 0.80 and 2.53 LSB, which are very close to the ac- structed to derive the DNL and INL; the results are shown in the
tual values. RHS plots of Fig. 23. The peak estimated DNL and INL values
The estimation errors are shown in Fig. 22; the maximum are 0.97 and 3.30 LSB, respectively.
DNL and INL measurement errors are 0.19 and 0.36 LSB, re- The DAC DNL/INL test errors of the proposed technique are
spectively. It is worth noting that each DAC output is sampled shown in Fig. 24; the peak DNL and INL errors are 0.16 and
50 times by the ADC in these experiments to average out the 0.32 LSB, respectively. These results demonstrate the insen-
noise effect. sitivity of the proposed DAC testing technique against the noise.
1774 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 10, OCTOBER 2011
Fig. 24. DAC testing errors.
VIII. CONCLUSION
This paper presents a simple yet efficient static loopback
testing technique for an ADC/DAC pair when the DAC is a
segmented current-steering one. The effective test resolution is
raised by properly scaling and offsetting the DAC output; both
the scaling factors and the set of offset voltages need not be
very accurate. Due to the simplicity, robustness, and low DfT
hardware requirement, the proposed technique is a promising
solution to SoCs with both ADC and DAC. Experimental results
based on commercial ICs show that very high test accuracy can
be achieved even in the presence of noise.
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Xuan-Lun Huang (S’08) received the B.S. degree in
electrical engineering from Chang Gung University,
Taiwan, in 2004, and the Ph.D. degree in electronics
engineering from National Taiwan University, Taipei,
Taiwan, in 2010.
In 2009, he joined the Industrial Technology
Research Institute, Hsinchu, Taiwan, where he is
currently a Research and Development Engineer
with the Information and Communications Research
Laboratories. His research interests include de-
sign-for-test (DfT) and built-in self-test (BIST) for
mixed-signal VLSI systems.
Jiun-Lang Huang (S’96–M’99) received the B.S.
degree in electrical engineering from National
Taiwan University, Taipei, Taiwan, in 1992, and the
M.S. and Ph.D. degrees in electrical and computer
engineering from the University of California at
Santa Barbara (UCSB), in 1995 and 1999, respec-
tively.
From 2000 to 2001, he served as an Assistant
Research Engineer with the Electrical and Computer
Engineering Department, UCSB. In 2001, he joined
National Taiwan University and is currently an
Associate Professor with the Graduate Institute of Electronics Engineering and
the Department of Electrical Engineering. His main research interests include
design-for-test (DfT) and built-in self-test (BIST) for mixed-signal systems,
and VLSI system verification.