Thermal Management and Device Failure Assessment of High-Power AIGaN/GaN

HFETs

M. Kuball“,” S . Rajasingam‘a’, A. Sarua“’, J.M. Hayes@’, M.J. Uren”, T. Martin”, R.S.

Balmer”’, B.T. Hughes”’ and K.P. Hilton”’

(a) H.H. Wills Physics Laboratory, University of Bristol, Bristol BS8 lTL, United Kingdom
(b) QinetiQ Ltd., St. Andrew’s Road, Malvern, Worcs WR14 3PS, United Kingdom

Self-heating effects limit the performance of high-power AlGaNlGaN HFETs. Knowledge

of the temperature in the active area of AIGaNIGaN HFETs is essential for optimizing device
design, performance and reliability, however, direct measurement of this temperature is not
readily achieved. Infrared techniques often employed to measure the temperature of an active
device require extensive calibration and have limited spatial resolution when compared with
the only micron-size sourcedrain opening in high-power AIGaN/GaN HFETs. Improved
temperature information can be obtained by micro-Raman spectroscopy allowing temperature
measurements with lpm spatial resolution, important for local device geometries in the
micron/sub-micron dimension range. This novel approach allows fast temperature
measurements with minimal influence on device performance. We illustrate the use of micro-
Raman spectroscopy for thermal management and device failure assessment by studying
effects of device design and substrate on temperature in active high-power AIGaN/GaN
HFETs. Temperature evolution up to device failure was investigated.
HFETs were fabricated from 30nm-Alo2 3 G,,N/1.2pm-GaN,
~ grown by MOVPE on
sapphire (0001) and insulating SIC (OOOI) substrates, using conventional mesa-isolated device
technology with TilAbTiilAu ohmic contacts and NUAu Schottky gates. Three types of device
were investigated (a) device on sapphire with 4pm sourcedrain gap, lpm gate, 2pm gate-
drain gap, (b) device on sapphire with IOpm source-drain gap, 4pm gate centered between
source and drain and (c) device on S i c with same device layout as (a). AI1 devices use a
2 0 0 wide,
~ center-fed gate.
Figure 1 shows temperature line scans of the sourcedrain opening of device “a” recorded
at V,,=2OV at different gate bias voltages. Increased power dissipation in the saturated region
of the devices is responsible for peak temperatures occurring in the drain-gate opening. The
device temperature decreases as expected as the gate voltage approaches pinch-off (Figure 2).
Results obtained for device “b”, operated at VDs=20Vand VGs=OV (with power dissipation of
0.65W. i.e., a power dissipation similar to device “a” at VGS=-IV),with its wider sourcedrain
opening are shown as dashed lines in Figure 1. We find device layout to have only minimal
influence on device temperature for the investigated single-finger devices.
The key parameter influencing device temperature is the thermal conductivity of the
substrate. Figure 3 shows the temperature in the source-gate and in the drain-gate opening for
devices “a” and “c”. The reduced device temperature in the S i c substrate device is obvious
due to the IO-times higher thermal conductivity of S i c (~~~~=3.3Wcm-’K-’,
~,,~~=0.35Wcm-’K-’).Discontinuities in device temperature as function of power
dissipation were observed, e.g., at =3W for device “c”, illustrating device degradation prior to
device failure. Device failure occurred for the SIC substrate device at a power dissipation
about 3-times higher than for the sapphire substrate device, illustrating the benefits of good
thermal management. Interestingly, we found device failure to always occur at device
junction temperature rises of 200-3Oo0C for all investigated device designs and types of
substrate, although AIGaN/GaN HFETs are expected to withstand much higher temperatures.
Contact degradation accelerated by self-heating of the devices appears to be one possible
mechanism for device failure in the investigated AIGaN/GaN HFETs.

”Corresponding author, phone: 4 4 117 928 8734,fax: +44 117 925 5624: email: Manin.Kuball@bristol.ac.uk

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 2 4 0 , . , . , . I

V, (device “a”)

200 device “b”

Position [pm] Power Iw]

Figure 1: Temperature line scans in source-drain Figure 2: Average temperature of device “a”
opening of device “a” at VDs=20V for different gate in source-drain opening at VDs=20V as
bias voltages VcS (full lines) and for device ‘b“ function of power dissipation. The inset shows
(dashed line) at VDs=20V. Vcs=0V (0.65W). power dissipation as function of gate bias.

‘ knee voltage
OO 20 40 60 80

HFET on sap. (“a”) 1 HFET on Sic (“c”)

120 source-gate source-gate

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 2 3 4

Power PN] Power [wl

Figure 3: Temperature in source-gate and drain-gate device opening as function of power dissipation for
AIGaN/GaN HFET on sapphire (device “a”) and on Sic (device “c”). Device failure occurred after
operating the device at the highest shown power dissipation level. A discontinuity in device temperature
as function of power dissipation prior to device failure is evident for device “c” (marked by arrow).
The inset shows power dissipation as function of applied drain bias voltage VDs (VGS=OV).

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