ACEBO MARIANNE JANE | COE601

Code:
module hdlmidtermtask (a,b,c,d,f);
input a,b,c,d;
output f;
wire madi1,madi2,jane1,jane2,jane3,roda1,roda2;
not (madi1,c);
not (jane1,a);
not (jane3,jane2);
not (roda2,roda1);
and (madi2,d,jane1,b);
and (roda1,c,b);
or (jane2,d,jane1);
or (f,madi2,jane3,roda2);
endmodule
 ACEBO MARIANNE JANE | COE601

Tested at Verilog JDoodle

Answer:

F = ~(~Z |Y)&~(X|~W|Y))