TASK 1

Write a Gatelevel code for Combinational Circuit 1.

CODE:
module CS_1(f,a,b,c,d,e);

//module for combinational circuit 1.

input a,b,c,d,e;
output f;
wire w1,w2,w3,w4,w5;
and g1(w1,a,~b);
and g2(w2,~a,b);
or g3(w3,c,~d);
or g4(w4,w1,w2);
and g5(w5,e,w3);
and g6(f,w4,w5);
endmodule

//wires to connect gates.

TIMMING DIAGRAM

TASK 2
Write a Gatelevel code for Combinational Circuit 2.

CODE:
module CS_2(f,a,b,c,d,e);

//module for combinational circuit 2.

input a,b,c,d,e;
output f;
wire [12:0]w;

//wires to connect gates.

nand g1(w[0],a,~b);
nand g2(w[1],~a,b);
nand g3(w[2],c,c);
nand g4(w[3],~d,~d);
nand g5(w[4],w[0],w[0]);
nand g6(w[5],w[1],w[1]);
nand g7(w[6],w[2],w[3]);
nand g8(w[7],w[4],w[4]);
nand g9(w[8],w[5],w[5]);
nand g10(w[9],w[6],e);
nand g11(w[10],w[7],w[8]);
nand g12(w[11],w[9],w[9]);
nand g13(w[12],w[11],w[10]);
nand g14(f,w[12],w[12]);
endmodule

TIMMING DIAGRAM

CONCLUSION:
By comparing both timming diagrams,
it is concluded that functionality of both combinational circuits is same.

COMPUTER ORGANIZATION
LAB # 02
COMBINATIONAL CIRCUITS IN VERILOG

Submitted To:
Engr. Tahir Mohammad
Submitted by:
Babar Rasheed
11-EE-185
Group: B2
Date of submission:
21/05/2013

Department Of Electrical Engineering

University Of Engineering & Technology,
Taxila