Chapter 3 Malvino Ans

3-1. In Fig. 3-25a, if A is low, then Y1 is high. If A is high, then F is high. The circuit acts
like a non-inverter.

3-2. In Fig. 3-25b, if both inputs are low, the output is high. If one input is low and the
other is high, the output is high. If both inputs are high, the output is low. The circuit acts
like a NAND gate.

3-3. In Fig. 3-26, if all X and Y inputs are high, then Z1 is high. If all inputs are high
except X1 and Z2, then Z3 is high. If X2 and Y0 are low and all other inputs are high,
then Z7 is high.

3-4. In Fig. 3-26, to get Z7 to be 1 and all other Z outputs to be 0, X0, X1, X2, Y1, Y2,
and Y3 must be high, and X3 and Y0 must be low.

3-5. In Fig. 3-27, if R = 0 and S = 1, then Q is 0 and Q̅ is 1.

3-6. In Fig. 3-27, if R = 1 and S = 0, then Q is 1 and Q̅ is 0.

3-7. To prove that Fig. 3-28a and b are equivalent, we can create a truth table for both
circuits and show that the outputs for all possible input combinations are the same.

3-8. In Fig. 3-28a, if all inputs are 0s, then the output is 1. If all inputs are 1s, then the
output is 0.

3-9. In Fig. 3-28b, if all inputs are 0s, then the output is 0. If all inputs are 1s, then the
output is 1.

3-10. A NOR gate with 6 inputs has 64 input words in its truth table. The only input word
that produces a 1 output is when all inputs are 0s.
3-11. In Fig. 3-28a, there are 16 input words in the truth table.

3-12. In Fig. 3-29, if all inputs are low, then the output is 0. If all inputs are high, then the
output is 1.

3-18. In Fig. 3-31, if R = 0 and S = 1, then Q is 1 and Q̅ is 0.

3-19. In Fig. 3-31, if R = 1 and S = 0, then Q is 0 and Q̅ is 1.

3-20. In Fig. 3-32a, if all inputs are 0s, then the output is 1. If all inputs are 1s, then the
output is 0.

3-21. In the truth table of Fig. 3-32a, there are 16 input words.

3-22. To prove that Fig. 3-32a and b are equivalent, we can create a truth table for both
circuits and show that the outputs for all possible input combinations are the same.

3-23. In Fig. 3-33, if all inputs are low, then the output is 1. If all inputs are high, then the
output is 0.
3-24. The truth table of Fig. 3-33 has 32 rows, each with 5 columns. Therefore, there
are 32 x 5 = 160 words in the truth table.

For each input condition:

a. Y = 1
b. Y = 0
c. Y = 0
d. Y = 1

3-25. In Fig. 3-34:

a. LP = 0
b. LP = 1
c. LP = 1
d. LP = 1

3-26. In Fig. 3-35:

a. LDA = 1
b. JMP = 0, JAM = 0, ADD = 1, LDA = 0, SUB = 0, OUT = 0
c. JAZ = 1, JMP = 0, JAM = 0, ADD = 0, LDA = 0, SUB = 0, OUT = 0
d. JAM = 1, LDA = 1, JMP = 0, JAZ = 0, ADD = 0, SUB = 0, OUT = 0
e. LDA = 1, JAM = 0, JMP = 0, JAZ = 0, ADD = 0, SUB = 0, OUT = 0
f. ADD = 1, JAM = 0, JMP = 0, JAZ = 0, LDA = 0, SUB = 0, OUT = 0
g. ADD = 1, T5 = 1, JAM = 0, JMP = 0, JAZ = 0, LDA = 0, SUB = 0, OUT = 0
h. ADD = 0, JMP = 0, JAM = 0, JAZ = 0, LDA = 0, SUB = 1, OUT = 0
i. SUB = 1, JAM = 1, LDA = 0, JMP = 0, JAZ = 0, ADD = 0, OUT = 0
j. SUB = 1, T5 = 1, JAM = 0, JMP = 0, JAZ = 0, LDA = 0, ADD = 0, OUT = 0
k. SUB = 1, JMP = 0, JAM = 0, JAZ = 0, LDA = 0, ADD = 0, T6 = 1, OUT = 0
l. OUT = 1, T4 = 1, JMP = 0, JAM = 0, JAZ = 0, LDA = 0, ADD = 0, SUB = 0

3-27. In Fig. 3-36:

a. Y4Y3Y2Y1Y0 = 11011
b. Y4Y3Y2Y1Y0 = 10010
c. Y4Y3Y2Y1Y0 = 11101
d. Y4Y3Y2Y1Y0 = 11000
3-28. An 8-input xor gate has 256 input words in its truth table.
3-29. To modify Fig. 3-19 to produce an 8-bit output word with even parity, one
additional gate needs to be added. The parity bit is calculated as the XOR of all the bits
in the 8-bit input word. So, an XOR gate needs to be added at the output of the 8-bit
register to calculate the parity bit. The output of the XOR gate will be 1 if the number of
1's in the 8-bit input word is odd, and 0 if the number of 1's is even. To make the output
word have even parity, the output of the XOR gate can be fed into an OR gate along
with the 8-bit input word. The output of the OR gate will be the 8-bit input word with an
additional parity bit that makes the total number of 1's in the word even.

3-30. In the controlled inverter of Fig. 3-21, the output word Y is given by Y = A if
INVERT = 0, and Y = A' if INVERT = 1, where A' is the complement of A.

a. A = 1100 1111 and INVERT = 0

Y = 1100 1111

b. A = 0101 0001 and INVERT = 1

Y = 1010 1110

c. A = 1110 1000 and INVERT = 1

Y = 0001 0111

d. A = 1010 0101 and INVERT = 0

Y = 1010 0101

3-31. The inputs A and B of Fig. 3-37 produce outputs of CARRY and SUM as follows:

a. A = 0 and B = 0
CARRY = 0, SUM = 0

b. A = 0 and B = 1
CARRY = 0, SUM = 1

c. A = 1 and B = 0
CARRY = 0, SUM = 1

d. A = 1 and B = 1
CARRY = 1, SUM = 0

3-32. In Fig. 3-37, the boolean equation for CARRY is CARRY = AB, and the boolean
equation for SUM is SUM = A ⊕ B, where ⊕ is the XOR operator.

3-33. The l's complement of a binary number is obtained by flipping all the bits (0s
become 1s and 1s become 0s).

a. The l's complement of 1100 0011 is 0011 1100.

b. The l's complement of 1010 1111 0011 1100 is 0101 0000 1100 0011.
c. The l's complement of 1110 0001 1010 0011 is 0001 1110 0101 1100.
d. The l's complement of 0000 1111 0010 1101 is 1111 0000 1101 0010
3-34. The output of a 16-input XNOR gate is 1 if all of its input bits are either all 0's or all
1's, and 0 otherwise. Therefore, the output for each of the input words is:

a. 1
b. 0
c. 0
d. 0

3-35. Substituting the given values of ABCD in the boolean equation Y = AB + CD + AC,
we get:

a. Y = 0 + 0 + 0 = 0
b. Y = 0 + 1 + 0 = 1
c. Y = 1 + 0 + 0 = 1
d. Y = 1 + 0 + 1 = 1