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    The document describes designing a 4-to-1 multiplexer (MUX) using behavioral modeling in Verilog HDL. A 4-to-1 MUX has 4 inputs, 1 output, and 2 control inputs to select one of the 4 inputs for the output. The design of the 4-to-1 MUX is modeled using a module with the inputs, output, and control signals. The output is assigned using a case statement that selects the appropriate input based on the values of the control signals. A test bench is also provided to simulate the 4-to-1 MUX design by applying different combinations of inputs and control signals over time and monitoring the output.

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    EEE413-lab06

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    The document describes designing a 4-to-1 multiplexer (MUX) using behavioral modeling in Verilog HDL. A 4-to-1 MUX has 4 inputs, 1 output, and 2 control inputs to select one of the 4 inputs for the output. The design of the 4-to-1 MUX is modeled using a module with the inputs, output, and control signals. The output is assigned using a case statement that selects the appropriate input based on the values of the control signals. A test bench is also provided to simulate the 4-to-1 MUX design by applying different combinations of inputs and control signals over time and monitoring the output.

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    4 views5 pages

    EEE413 Lab06

    Uploaded by

    nsu admission
    The document describes designing a 4-to-1 multiplexer (MUX) using behavioral modeling in Verilog HDL. A 4-to-1 MUX has 4 inputs, 1 output, and 2 control inputs to select one of the 4 inputs for the output. The design of the 4-to-1 MUX is modeled using a module with the inputs, output, and control signals. The output is assigned using a case statement that selects the appropriate input based on the values of the control signals. A test bench is also provided to simulate the 4-to-1 MUX design by applying different combinations of inputs and control signals over time and monitoring the output.

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    EEE413/ETE419/CSE413

    Verilog HDL: Modeling & Simulation


    Lab04: Design 4*1 Multiplexer Using Behavioral
    Modeling. Also Do the Synthesis in Xillinx
    A 4*1 MUX has 4 inputs (I0, I1, I2, I3) ,1 output(out) and 2
    control inputs(S0,S1).
    Out = (~S0&~S1&I0) | (~S0&S1&I1) |
    (S0&~S1&I2) |(S0&S1&I3)
    Main Module:
    module mux4to1 (out, i0, i1, i2, i3, s1, s0);
    output out;
    input i0, i1, i2, i3;
    input s1, s0;
    reg out;
    always @ ( s1 or s0 or i0 or i1 or i2 or i3)
    begin
    case ( {s1, s0})
    2’b00: out = i0;
    2’b01: out = i1;
    2’b10: out = i2;
    2’b11: out = i3;
    default: out = 1’b1;
    endcase
    end
    endmodule

    Test Bench:
    module top;
    wire Out;
    reg S0,S1,I0,I1,I2,I3;
    mux4to1 f1(Out,I0,I1,I2,I3,S1,S0);
    initial
    begin
    $monitor($time,“Out=%b,I0=%b,I1=%b,I2=
    %b, I3=%b,S1=%b, S0=%b”, Out, I0, I1, I2,
    I3, S1, S0);
    end
    initial
    begin
    I0=1’b1; I1=1’b0;I2=1’b1; I3=1’b0;
    end
    initial
    begin
    S1=1’b0 ; S0=1’b0 ;
    #5 S1=1’b0 ; S0=1’b1 ;
    #5 S1=1’b1 ; S0=1’b0 ;
    #5 S1=1’b1 ; S0=1’b1 ;
    #5 $stop;
    end
    endmodule

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