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SEMICONDUCTOR DEVICES
CHAPTER 3
𝒑𝒑⎼𝒏𝒏 JUNCTION
𝒑𝒑⎼𝒏𝒏 junction theory serves as the foundation of the physics
of semiconductor devices. 𝒑𝒑⎼𝒏𝒏 junction is used extensively in
electronic circuits, and it is also a key building block for most
semiconductor devices, especially for the bipolar transistor,
MOSFET, microwave devices, and photonic devices.
In this chapter we consider:
The basic semiconductor technology
The band diagram of a 𝒑𝒑⎼𝒏𝒏 junction at thermal equilibrium
The behavior of the junction depletion layer under voltage
biases
The current transport in a 𝒑𝒑⎼𝒏𝒏 junction and the influence of
the generation and recombination processes
The avalanche multiplication in a 𝒑𝒑⎼𝒏𝒏 junction and its
impact on the maximum reverse voltage
SILICON CRYSTAL GROWTH
𝟑𝟑𝟑𝟑𝟑𝟑℃
Si(MGS)+3HCl(gas) SiHCl3(gas)+H2(gas)
fractional distillation
SiHCl3(purified)
+𝐇𝐇𝟐𝟐
Si(solid)+3HCl(gas)
electronic-grade silicon
(EGS, ppb impurity, polycrystal)
Polycrystalline silica in a silicon crucible
CZOCHRALSKI CRYSTAL GROWTH
Figure below shows a Czochralski crystal puller
Ingot
Sliced by diamond
saw into wafers
← 𝑃𝑃𝑃𝑃
2. Apply a layer of photoresist(PR)
n-Si ←(p.442)
← ℎ𝑣𝑣
3. Expose PR through Mask A ← 𝐴𝐴
n-Si
Mask A
↙ 𝑃𝑃𝑃𝑃
5. Use HF etch to remove ← 𝑆𝑆𝑆𝑆𝑂𝑂
SiO22
n-Si
𝐒𝐒𝐒𝐒𝐎𝐎𝟐𝟐 in window
FABRICATION OF 𝒑𝒑⎼𝒏𝒏 JUNCTION(Cont.)
diffused or implanted p region
6. Remove PR and diffuse or implant ↓ ← 𝑆𝑆𝑆𝑆𝑂𝑂
SiO 22
boron through windows in SiO 𝟐𝟐 layer. ←(p.472)
n-Si
← 𝐴𝐴𝐴𝐴
7. Evaporate Al onto the surface ← 𝑆𝑆𝑆𝑆𝑂𝑂2
p n-Si
Mask B
𝑱𝑱𝒑𝒑 𝒒𝒒𝝁𝝁
𝑱𝑱𝒑𝒑 = = 𝒑𝒑𝒒𝒒𝝁𝝁
𝒑𝒑𝒑𝒑𝒑𝒑 𝒑𝒑𝒑𝒑 − 𝒒𝒒𝑫𝑫
− 𝒒𝒒𝑫𝑫 𝒅𝒅𝒅𝒅
𝒅𝒅𝒅𝒅 𝒅𝒅𝒅𝒅
𝒑𝒑 𝒑𝒑 𝒅𝒅𝒅𝒅 = 𝟎𝟎
𝑱𝑱𝒑𝒑 = 𝒒𝒒𝝁𝝁𝒑𝒑 𝒑𝒑𝓔𝓔 − 𝒒𝒒𝑫𝑫𝒑𝒑𝒅𝒅𝒅𝒅 (1)
= 𝒒𝒒𝝁𝝁𝒑𝒑 𝒑𝒑
𝒅𝒅𝒅𝒅
𝟏𝟏 𝒅𝒅𝑬𝑬𝒊𝒊
− 𝒌𝒌𝒌𝒌𝝁𝝁𝒑𝒑
𝒅𝒅𝒅𝒅
𝒅𝒅2 𝝍𝝍
∴ = 0, 𝑵𝑵𝑫𝑫 − 𝑵𝑵𝑨𝑨 + 𝒑𝒑 − 𝒏𝒏 = 0
∴ 𝒅𝒅𝒙𝒙2= 𝟎𝟎,
1 𝒌𝒌𝒌𝒌 𝑵𝑵𝐴𝐴
𝝍𝝍 ≡ −𝟏𝟏 𝑬𝑬𝒊𝒊 − 𝑬𝑬𝑭𝑭 = − 𝒌𝒌𝒌𝒌 𝒍𝒍𝒍𝒍
𝝍𝝍𝒑𝒑 ≡ − 𝒒𝒒 𝑬𝑬𝒊𝒊 − 𝑬𝑬𝑭𝑭 = − 𝒒𝒒
𝒑𝒑
𝒒𝒒 𝒒𝒒 𝒏𝒏𝒊𝒊
The total electrostatic potential difference between 𝒑𝒑-side and 𝒏𝒏-side neutral region:
𝒌𝒌𝒌𝒌 𝑵𝑵𝑨𝑨 𝑵𝑵𝑫𝑫
𝑽𝑽𝒃𝒃𝒃𝒃 = 𝝍𝝍𝒏𝒏 − 𝝍𝝍𝒑𝒑 = 𝒍𝒍𝒍𝒍 = built−in potential (12)
𝒒𝒒 𝒏𝒏𝒊𝒊 2
BUILT-IN POTENTIAL
Figure 4 shows the electrostatic potentials on the 𝒑𝒑-side and 𝒏𝒏-side of abrupt
junctions in Si and GaAs as a function of impurity concentration.
EXAMPLE 1
Calculate the built-in potential for a silicon 𝒑𝒑-𝒏𝒏 junction with 𝑵𝑵𝑨𝑨 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟑𝟑 and
𝑵𝑵𝑫𝑫 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜−𝟑𝟑 at 𝟑𝟑𝟑𝟑𝟑𝟑 𝐊𝐊
SOLUTION From Eq. 12 we obtain
𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
𝑽𝑽𝒃𝒃𝒃𝒃 = 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎 𝒍𝒍𝒍𝒍 = 𝟎𝟎. 𝟕𝟕𝟕𝟕𝟕𝟕 𝐕𝐕
𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗 𝟐𝟐
Also From Fig.4,
𝑽𝑽𝒃𝒃𝒃𝒃 = 𝝍𝝍𝒏𝒏 + 𝝍𝝍𝒑𝒑 = 𝟎𝟎. 𝟑𝟑𝟑𝟑 𝐕𝐕 + 𝟎𝟎. 𝟒𝟒𝟒𝟒 𝐕𝐕 = 𝟎𝟎. 𝟕𝟕𝟕𝟕 𝐕𝐕
DEPLETION REGION
Since the transition region (Fig.3c) is much smaller than the total
width of the depletion region , we can use the rectangular
approximation (Fig.3d).Equation 7 becomes
𝒅𝒅2 𝝍𝝍 𝒒𝒒
= 𝑵𝑵 − 𝑵𝑵𝑫𝑫 𝟏𝟏𝟏𝟏
𝒅𝒅𝒙𝒙2 𝝐𝝐𝒔𝒔 𝑨𝑨
DEPLETION REGION (Cont.)
To solve the above Poisson’s equation, we must know the impurity
distribution , i.e., 𝑵𝑵𝑨𝑨 𝒙𝒙 𝒂𝒂𝒂𝒂𝒂𝒂 𝑵𝑵𝑫𝑫 𝒙𝒙 . The most important distribution is the
abrupt junction , i.e., a 𝒑𝒑⎼𝒏𝒏 junction formed by shallow diffusion or low-
energy ion implantation . It can be approximated by an abrupt translation
of doping concentration between 𝒏𝒏-type and 𝒑𝒑-type regions .
𝑑𝑑ℇ 𝜌𝜌𝑠𝑠
𝓔𝓔(𝐕𝐕/𝒄𝒄𝒄𝒄) ∵ =
2. Electric field distribution 𝑊𝑊
𝑑𝑑𝑑𝑑 𝜖𝜖𝑠𝑠
𝑥𝑥
𝜌𝜌𝑠𝑠
ℇ=� 𝑑𝑑𝑑𝑑
𝐴𝐴𝐴𝐴𝐴𝐴𝐴𝐴 = 𝑉𝑉𝑏𝑏𝑏𝑏 𝜖𝜖𝑠𝑠
−ℰ𝑚𝑚
1
𝑉𝑉𝑏𝑏𝑏𝑏 = ℰ 𝑊𝑊
2 𝑚𝑚
𝝍𝝍(𝒙𝒙)
3. Potential distribution
𝑉𝑉𝑏𝑏𝑏𝑏
𝜓𝜓 = − � ℰ 𝑑𝑑𝑑𝑑
−𝑥𝑥𝑝𝑝 0 𝑥𝑥𝑛𝑛
𝑬𝑬(𝒆𝒆𝒆𝒆)
𝑵𝑵𝑨𝑨𝑵𝑵𝒙𝒙𝑨𝑨𝒑𝒑𝒙𝒙𝒑𝒑== 𝑵𝑵𝑫𝑫𝒙𝒙𝒙𝒙𝒏𝒏𝒏𝒏
𝑵𝑵𝑫𝑫 (15)
𝑾𝑾 ≡ 𝒙𝒙𝒑𝒑 + 𝒙𝒙𝒏𝒏 =total depletion width
(16)
𝒒𝒒𝑵𝑵𝑨𝑨 𝒒𝒒𝑵𝑵𝑨𝑨 𝒙𝒙 + 𝒙𝒙𝒑𝒑
𝓔𝓔 𝒙𝒙 = − � 𝒅𝒅𝒅𝒅 = − ,
𝒒𝒒𝑵𝑵𝑨𝑨 𝒙𝒙+𝒙𝒙𝒑𝒑
−𝒙𝒙𝒑𝒑 ≤ 𝒙𝒙 < 0
𝝐𝝐
𝓔𝓔 𝒙𝒙 = − ∫
𝒔𝒔
𝒒𝒒𝑵𝑵𝑨𝑨
𝒅𝒅𝒅𝒅 = − 𝝐𝝐𝒔𝒔 , −𝒙𝒙𝒑𝒑 ≤ 𝒙𝒙 < 𝟎𝟎
𝝐𝝐𝒔𝒔
𝒒𝒒𝑵𝑵𝑫𝑫 𝒒𝒒𝑵𝑵𝑫𝑫 𝒒𝒒𝑵𝑵𝑫𝑫 𝒒𝒒𝑵𝑵 𝒙𝒙 𝑫𝑫−𝒙𝒙−𝒙𝒙
𝒙𝒙𝒏𝒏𝒏𝒏
𝝐𝝐𝒔𝒔 (17)
𝓔𝓔 𝒙𝒙 = �𝓔𝓔 𝒙𝒙 =𝒅𝒅𝒅𝒅 ∫ 𝝐𝝐= 𝒅𝒅𝒅𝒅 = ,, 𝟎𝟎 < 𝒙𝒙𝟎𝟎≤<𝒙𝒙𝒏𝒏𝒙𝒙 ≤ 𝒙𝒙𝒏𝒏
𝝐𝝐𝒔𝒔 𝒔𝒔 𝝐𝝐𝒔𝒔 𝝐𝝐𝒔𝒔
𝒒𝒒𝑵𝑵 𝒙𝒙 𝒒𝒒𝑵𝑵𝑨𝑨 𝒙𝒙𝒑𝒑
𝓔𝓔𝒎𝒎 |𝒙𝒙=𝟎𝟎 = 𝑫𝑫 𝒏𝒏 =
𝒒𝒒𝑵𝑵𝑫𝑫 𝒙𝒙𝒏𝒏 𝝐𝝐𝒒𝒒𝑵𝑵 𝒔𝒔 𝑨𝑨 𝒙𝒙𝒑𝒑
(18)
𝓔𝓔𝒎𝒎 � = =
𝒙𝒙=𝟎𝟎 𝝐𝝐𝒔𝒔 𝝐𝝐𝒔𝒔
𝒙𝒙 𝟎𝟎 𝒙𝒙
𝑽𝑽𝒃𝒃𝒃𝒃 = − ∫−𝒙𝒙𝒏𝒏 𝓔𝓔 𝒙𝒙 𝒅𝒅𝒅𝒅 = − ∫−𝒙𝒙 𝓔𝓔 𝒙𝒙 𝒅𝒅𝒅𝒅 − ∫𝟎𝟎 𝒏𝒏 𝓔𝓔 𝒙𝒙 𝒅𝒅𝒅𝒅
𝒑𝒑 𝒑𝒑
𝒒𝒒𝑵𝑵
𝒒𝒒𝑵𝑵𝑩𝑩𝒘𝒘𝑾𝑾 𝟓𝟓. 𝟏𝟏 × 𝟏𝟏𝟎𝟎𝟒𝟒 𝐕𝐕/𝐜𝐜𝐜𝐜
𝓔𝓔𝒎𝒎𝓔𝓔𝒎𝒎≅≅ 𝝐𝝐𝑩𝑩 = 𝟓𝟓. 𝟏𝟏 × 𝟏𝟏𝟏𝟏𝟒𝟒 V/cm
𝝐𝝐𝒔𝒔
𝒔𝒔
DEPLETION-LAYER WIDTH
𝟎𝟎 𝑾𝑾
𝝆𝝆𝒔𝒔
𝑵𝑵𝑫𝑫
𝒙𝒙 (b)
𝟎𝟎 𝑾𝑾
𝑵𝑵𝑨𝑨
𝓔𝓔
𝟎𝟎
(c)
𝒙𝒙
𝒅𝒅𝒅𝒅
𝓔𝓔𝒎𝒎
𝒅𝒅𝓔𝓔𝒎𝒎
𝒅𝒅𝒅𝒅 𝝆𝝆𝒔𝒔
∵ = (𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐏𝐧𝐧′ 𝐬𝐬 𝐄𝐄𝐄𝐄. )
𝒅𝒅𝒅𝒅 𝝐𝝐𝒔𝒔
𝝆𝝆𝒔𝒔 𝒅𝒅𝒅𝒅 𝒅𝒅𝒅𝒅(𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬 𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚 𝐢𝐢𝐢𝐢 𝐅𝐅𝐅𝐅𝐅𝐅. 𝐛𝐛)
𝒅𝒅𝒅𝒅 = =
𝝐𝝐𝒔𝒔 𝝐𝝐𝒔𝒔
DEPLETION CAPACITANCE(Cont.)
From Fig c : 𝒒𝒒𝑵𝑵𝑫𝑫 𝑾𝑾 𝝐𝝐𝒔𝒔
𝓔𝓔𝒎𝒎 = 𝑾𝑾 = 𝓔𝓔
𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑫𝑫 𝒎𝒎
𝒒𝒒𝑵𝑵𝑫𝑫 𝝐𝝐𝒔𝒔
𝒅𝒅𝒅𝒅𝒎𝒎 = (𝒅𝒅𝒅𝒅) 𝒅𝒅𝒅𝒅 = (𝒅𝒅𝒅𝒅𝒎𝒎 )
𝝐𝝐𝒔𝒔 𝒒𝒒𝑵𝑵𝑫𝑫
(𝓔𝓔 +𝒅𝒅𝒅𝒅 )(𝒘𝒘+𝒅𝒅𝒅𝒅) 𝟏𝟏
∆𝑽𝑽== 𝓔𝓔𝒎𝒎𝒎𝒎+ 𝒅𝒅𝓔𝓔𝒎𝒎
∆𝑽𝑽
𝒎𝒎 )(𝑾𝑾 + 𝒅𝒅𝒅𝒅
− − 1 𝓔𝓔𝒎𝒎 𝑾𝑾
𝟐𝟐2 𝟐𝟐 2
𝑾𝑾 𝒅𝒅𝒅𝒅
𝑾𝑾 𝒅𝒅𝓔𝓔𝒎𝒎𝒎𝒎 + 𝓔𝓔
𝒅𝒅𝑾𝑾 +
𝓔𝓔𝒎𝒎 𝒎𝒎 𝒅𝒅𝒅𝒅
𝒅𝒅𝓔𝓔𝒎𝒎 𝒅𝒅𝑾𝑾
== + +
2 𝟐𝟐 2 𝟐𝟐 2
𝑾𝑾 (𝒅𝒅𝒅𝒅𝒎𝒎 )𝒎𝒎 𝓔𝓔𝒎𝒎 𝓔𝓔𝝐𝝐𝒎𝒎
𝑾𝑾𝒅𝒅𝓔𝓔 𝒔𝒔 𝝐𝝐𝒔𝒔)] = 𝑾𝑾 (𝒅𝒅𝒅𝒅𝒎𝒎) + 𝑾𝑾 𝑾𝑾𝒅𝒅𝓔𝓔
𝒅𝒅𝒅𝒅 𝒎𝒎 =𝑾𝑾
𝑾𝑾 𝒅𝒅𝒅𝒅 = 𝐖𝐖
𝒅𝒅𝒅𝒅 𝒅𝒅𝒅𝒅
== 𝟐𝟐
+ + [
𝟐𝟐 𝒒𝒒𝑵𝑵𝑫𝑫
(𝒅𝒅𝒅𝒅 𝒎𝒎 (𝒅𝒅𝓔𝓔𝒎𝒎
𝟐𝟐 ) = 𝟐𝟐 𝒎𝒎 + 𝑾𝑾𝝐𝝐𝒔𝒔𝒎𝒎𝒅𝒅𝒅𝒅=𝒎𝒎𝑾𝑾
𝒅𝒅𝓔𝓔𝒎𝒎𝒎𝒎 = 𝑾𝑾 𝒅𝒅𝓔𝓔
𝟐𝟐 𝟐𝟐 𝒒𝒒𝑵𝑵𝑫𝑫 𝟐𝟐 𝟐𝟐 𝝐𝝐𝒔𝒔
𝝐𝝐𝒔𝒔𝝐𝝐
𝜺𝜺𝒔𝒔 𝑪𝑪𝒋𝒋𝑪𝑪=
𝒋𝒋 =
𝒔𝒔
F/cm2
𝑾𝑾𝑾𝑾
𝑾𝑾
CAPACITANCE VOLTAGE CHARACTERISTIC
therefore
𝟏𝟏
𝝐𝝐𝒔𝒔 𝒒𝒒𝝐𝝐𝒔𝒔 𝑵𝑵𝑩𝑩 𝑪𝑪𝟐𝟐𝒋𝒋
𝑪𝑪𝒋𝒋 = = (𝟑𝟑𝟑𝟑) ●
𝑾𝑾 𝟐𝟐(𝑽𝑽𝒃𝒃𝒃𝒃 −𝑽𝑽) ●
𝟏𝟏
Slope ~
●
𝑵𝑵𝑩𝑩
●
𝟏𝟏 𝟐𝟐(𝑽𝑽𝒃𝒃𝒃𝒃 − 𝑽𝑽)
𝒐𝒐𝒐𝒐 = (𝟑𝟑𝟑𝟑)
𝑪𝑪𝟐𝟐𝒋𝒋 𝒒𝒒 𝝐𝝐𝒔𝒔𝒔𝒔𝑵𝑵𝑵𝑵𝑩𝑩𝑩𝑩
𝒒𝒒𝝐𝝐 0 𝑽𝑽𝒃𝒃𝒃𝒃 𝑽𝑽
CAPACITANCE VOLTAGE
CHARACTERISTIC (Cont.)
EXAMPLE 4
For a silicon one-sided abrupt junction with 𝑵𝑵𝑨𝑨 = 𝟐𝟐 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 and 𝑵𝑵𝑫𝑫 = 𝟖𝟖 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 .
Calculate the junction capacitance at zero bias and a reverse bias of 𝟒𝟒V(𝐓𝐓 = 𝟑𝟑𝟑𝟑𝟑𝟑K)
SOLUTION From Eqs.12, 27, and 34, we obtain at zero bias
𝟐𝟐 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 × 𝟖𝟖 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏
𝑽𝑽𝒃𝒃𝒃𝒃 = 𝟎𝟎. 𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝟎𝐥𝐥𝐥𝐥 = 𝟎𝟎. 𝟗𝟗𝟗𝟗𝟗𝟗 V
𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗 𝟐𝟐
𝝆𝝆𝒔𝒔
𝑾𝑾 𝒅𝒅𝒅𝒅
(b) 𝒒𝒒𝒒𝒒(𝑾𝑾)
𝒙𝒙
≈
𝒙𝒙
𝒅𝒅V
(c)
−ℰ
𝒅𝒅ℰ = 𝒅𝒅𝒅𝒅/𝝐𝝐𝒔𝒔
EVALUTION OF IMPURITY DISTRIBUTION
(CONT.)
For an arbitrary doping
𝒒𝒒𝒒𝒒 𝑾𝑾 𝒅𝒅𝒅𝒅
𝒅𝒅𝒅𝒅 = 𝑾𝑾
𝝐𝝐𝒔𝒔
𝟏𝟏
𝒒𝒒𝒒𝒒 𝑾𝑾 𝒅𝒅𝑾𝑾𝟐𝟐
= 𝑪𝑪𝟐𝟐𝒋𝒋
𝟐𝟐𝝐𝝐𝒔𝒔
2
𝝐𝝐𝒔𝒔
= 𝒒𝒒𝒒𝒒 𝑾𝑾 𝒅𝒅 / 2𝝐𝝐𝒔𝒔
𝑪𝑪𝒋𝒋
𝟏𝟏
Slope ~
𝝐𝝐𝒔𝒔 𝝐𝝐 𝟐𝟐 𝟏𝟏 𝑵𝑵(𝑾𝑾)
==𝒒𝒒𝒒𝒒
𝒒𝒒𝒒𝒒 𝑾𝑾
𝑾𝑾 𝒅𝒅 𝒅𝒅𝒔𝒔 /2𝝐𝝐
𝟐𝟐 𝑪𝑪𝒋𝒋 𝑪𝑪𝒋𝒋 𝟐𝟐 𝒔𝒔 𝑽𝑽
𝟐𝟐 𝟏𝟏
∴ 𝑵𝑵 𝑾𝑾 = W is obtained from Eq.33
𝒒𝒒𝝐𝝐𝒔𝒔 𝟏𝟏 (37)
𝒅𝒅 /𝒅𝒅𝒅𝒅
𝑪𝑪𝒋𝒋 𝟐𝟐
This is the C-V method of measuring the impurity profile, i.e., N(W) versus W.
CURRENT-VOLTAGE CHARACTERISTICS
Ideal characteristics
Four assumptions:
From Eq.12
𝒌𝒌𝒌𝒌 𝑵𝑵𝑨𝑨 𝑵𝑵𝑫𝑫 𝒌𝒌𝒌𝒌 𝒑𝒑𝒑𝒑𝒑𝒑 𝒏𝒏𝒏𝒏𝒏𝒏 𝒌𝒌𝒌𝒌 𝒏𝒏𝒏𝒏𝒏𝒏
∵ 𝑽𝑽𝒃𝒃𝒃𝒃 = 𝒍𝒍𝒍𝒍 = 𝒍𝒍𝒍𝒍 = 𝒍𝒍𝒍𝒍
𝒒𝒒 𝒏𝒏𝒊𝒊 𝟐𝟐 𝒒𝒒 𝒏𝒏𝒊𝒊 𝟐𝟐 𝒒𝒒 𝒏𝒏𝒑𝒑𝒑𝒑
𝒑𝒑𝒑𝒑𝒑𝒑 𝒏𝒏𝒑𝒑𝒑𝒑
𝑱𝑱𝒑𝒑 𝒙𝒙 − 𝒙𝒙𝒏𝒏 = 𝑱𝑱𝒑𝒑 𝒙𝒙𝒏𝒏 𝒆𝒆−(𝒙𝒙−𝒙𝒙𝒏𝒏 )/𝑳𝑳𝒑𝒑 𝐟𝐟𝐟𝐟𝐟𝐟 𝒙𝒙 > 𝒙𝒙𝒏𝒏 (𝟓𝟓𝟓𝟓𝟓𝟓)
𝒏𝒏𝒑𝒑 − 𝒏𝒏𝒑𝒑𝒑𝒑 = 𝒏𝒏𝒑𝒑𝒑𝒑 𝒆𝒆𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌 − 𝟏𝟏 𝒆𝒆 𝒙𝒙+𝒙𝒙𝒏𝒏 /𝑳𝑳𝒏𝒏 𝟓𝟓𝟓𝟓 𝑳𝑳𝒏𝒏 = 𝑫𝑫𝒏𝒏 𝝉𝝉𝒏𝒏
𝒙𝒙+𝒙𝒙𝒑𝒑 /𝑳𝑳𝒏𝒏
𝑱𝑱𝒏𝒏 𝒙𝒙 + 𝒙𝒙𝒑𝒑 = 𝑱𝑱𝒏𝒏 −𝒙𝒙𝒑𝒑 𝒆𝒆 (𝟓𝟓𝟓𝟓𝟓𝟓)
MINORITY CARRIERS AND CURRENT
Figure 15 shows the injected minority carrier distribution and electron and hole
currents. (a) Forward bias. (b) Reverse bias. The figure illustrates idealized currents.
In practical devices, the currents are not constant across the space charge layer.
Forward Reverse
Eq.𝟓𝟓𝟓𝟓
Eq.𝟓𝟓𝟓𝟓
Eq.𝟓𝟓𝟓𝟓
Eq.𝟓𝟓𝟓𝟓 Eq.𝟓𝟓𝟓𝟓𝟓𝟓
Eq.𝟓𝟓𝟓𝟓𝟓𝟓
IDEAL DIODE EQUATION
The Ideal Diode Equation is
2.3 𝑘𝑘𝑘𝑘�𝑞𝑞 = 60 mV
10
EXAMPLE 5
Calculate the ideal reverse saturation current in a Si 𝒑𝒑⎼𝒏𝒏 junction diode
with a cross-sectional area of 𝟐𝟐 × 𝟏𝟏𝟏𝟏−𝟒𝟒 𝐜𝐜𝐜𝐜𝟐𝟐 .The parameters of the diode
are
𝑵𝑵𝑨𝑨 = 𝟓𝟓 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 , 𝑵𝑵𝑫𝑫 = 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 , 𝒏𝒏𝒊𝒊 = 𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗 cm−𝟑𝟑
2
𝐜𝐜𝐦𝐦 𝟐𝟐 2
𝟐𝟐𝟐𝟐 𝐜𝐜𝐜𝐜 ⁄𝐬𝐬�𝐬𝐬 𝐜𝐜𝐦𝐦⁄𝐬𝐬� , 𝝉𝝉 = 𝝉𝝉 = 𝟓𝟓 × 𝟏𝟏𝟏𝟏−𝟕𝟕 𝐬𝐬.
𝟐𝟐
𝑫𝑫𝒏𝒏 = , 𝑫𝑫𝒑𝒑 = 𝟏𝟏𝟏𝟏 𝐜𝐜𝐜𝐜 𝐬𝐬 𝒑𝒑 𝒏𝒏
SOLUTION From Eq. 55a and 𝑳𝑳𝒑𝒑 = 𝑫𝑫𝒑𝒑 𝝉𝝉𝒑𝒑 , we can obtain
∴ 𝑬𝑬𝒕𝒕 near the intrinsic Fermi level can contribute significantly to the
generation rate.
G-R EFFECT(Cont.)
Reverse Current
𝐖𝐖 𝑾𝑾 𝐪𝐪𝐧𝐧𝐢𝐢 𝐖𝐖 𝒒𝒒𝒏𝒏𝒊𝒊 𝑾𝑾
𝐉𝐉𝒈𝒈𝒈𝒈𝒈𝒈 = ∫𝟎𝟎 𝐪𝐪𝐪𝐪𝐪𝐪𝐪𝐪 ≅ 𝐪𝐪𝐪𝐪𝐪𝐪 =
𝑱𝑱𝒈𝒈𝒈𝒈𝒈𝒈 = � 𝒒𝒒𝒒𝒒𝒒𝒒𝒒𝒒 ≅ 𝒒𝒒𝒒𝒒𝒒𝒒𝛕𝛕𝐠𝐠 =
𝟎𝟎 𝝉𝝉𝒈𝒈
If a semiconductor with large 𝒏𝒏𝒊𝒊 (e.g., Ge with 𝒏𝒏𝒊𝒊 = 𝟐𝟐. 𝟒𝟒 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 )
𝑱𝑱𝒅𝒅𝒅𝒅𝒅𝒅𝒅𝒅 ≫ 𝑱𝑱𝒈𝒈𝒈𝒈𝒈𝒈
∴ 𝑱𝑱𝑹𝑹 ~𝒏𝒏𝟐𝟐𝒊𝒊 can follow the ideal diode equation, 𝑱𝑱𝒔𝒔 will saturate.
If a semiconductor with small 𝒏𝒏𝒊𝒊 (e.g., Si with 𝒏𝒏𝒊𝒊 = 𝟗𝟗. 𝟔𝟔𝟔𝟔 × 𝟏𝟏𝟏𝟏𝟗𝟗 cm−𝟑𝟑 )
∴ 𝑱𝑱𝑹𝑹 ~𝒏𝒏𝒊𝒊 𝑾𝑾
The reverse current will not saturate, because W will increase with reverse bias.
EXAMPLE 6
Consider the Si 𝒑𝒑⎼𝒏𝒏 junction diode in Example 5 and assume 𝝉𝝉𝒈𝒈 = 𝝉𝝉𝒑𝒑 = 𝝉𝝉𝒏𝒏 , calculate
the generation current density for a reverse bias of 4V.
SOLUTION From Eq. 20, we obtain
𝒒𝒒𝒒𝒒
𝟐𝟐 𝒒𝒒𝒒𝒒 𝒌𝒌𝒌𝒌
𝒏𝒏 (𝒆𝒆 − 𝟏𝟏)
𝟐𝟐 𝒊𝒊 𝒌𝒌𝒌𝒌
𝑼𝑼 =
= 𝝈𝝈
𝝈𝝈𝒐𝒐𝑽𝑽
𝒗𝒗𝒕𝒕𝒕𝒕 𝑵𝑵𝒕𝒕 𝒊𝒊
𝒏𝒏 (𝒆𝒆 −𝟏𝟏) (62)
𝑼𝑼 𝒐𝒐 𝒕𝒕𝒕𝒕 𝑵𝑵𝒕𝒕 𝒏𝒏
𝒏𝒏𝒏𝒏𝒏𝒏+𝒑𝒑+𝒏𝒏 +𝟐𝟐𝒏𝒏
𝒑𝒑𝒏𝒏 + 𝟐𝟐𝒏𝒏𝒊𝒊
𝒊𝒊
𝒏𝒏𝒏𝒏 𝒑𝒑𝒏𝒏 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜 𝐟𝐟𝐟𝐟𝐟𝐟 𝐚𝐚 𝐠𝐠𝐠𝐠𝐠𝐠𝐠𝐠𝐠𝐠 𝑽𝑽, 𝐄𝐄𝐄𝐄. 𝟔𝟔𝟔𝟔 𝒏𝒏𝒏𝒏 𝒑𝒑𝒏𝒏 𝒏𝒏𝒏𝒏
𝒅𝒅𝒑𝒑𝒏𝒏 = −𝒅𝒅𝒏𝒏𝒏𝒏 = −𝒅𝒅∴ 𝒅𝒅 𝒏𝒏𝒏𝒏 + 𝒑𝒑=𝒏𝒏 −𝒅𝒅
= 𝟎𝟎 = 𝒅𝒅𝒑𝒑𝒏𝒏 = 𝒅𝒅𝒑𝒑
𝒑𝒑𝒏𝒏 𝒑𝒑𝒏𝒏 𝒑𝒑𝟐𝟐𝒏𝒏 𝒑𝒑𝒏𝒏 𝒏𝒏
𝒏𝒏𝒏𝒏𝒏𝒏𝒏𝒏
Thus, 𝟏𝟏𝟏𝟏== 𝒐𝒐𝒐𝒐 𝒏𝒏𝒏𝒏 = 𝒑𝒑𝒏𝒏 For maximum 𝐔𝐔
𝒑𝒑𝒑𝒑𝒏𝒏𝒏𝒏
G-R EFFECT (Cont.)
Since 𝒏𝒏𝒏𝒏 𝒑𝒑𝒏𝒏 = 𝒏𝒏𝟐𝟐𝒊𝒊 𝐞𝐞𝐞𝐞𝐞𝐞 𝒒𝒒𝒒𝒒⁄𝒌𝒌𝒌𝒌
𝒒𝒒𝒒𝒒
~𝐞𝐞𝐞𝐞𝐞𝐞 where 𝜼𝜼 is the ideality factor.
~𝐞𝐞𝐞𝐞𝐞𝐞 where 𝜼𝜼 is the ideality factor.
𝜼𝜼𝒌𝒌𝒌𝒌
G-R EFFECT(Cont.)
Figure 17 shows the comparison of the forward current-voltage
characteristics of Si and GaAs diodes at 300K. Dashed lines
indicate slopes of different ideality factor η.
𝒒𝒒𝒒𝒒𝒒𝒒𝒒𝒒
∴ 𝒑𝒑 𝒙𝒙 = 𝒙𝒙 = 𝒏𝒏 𝐞𝐞𝐞𝐞𝐞𝐞
∴𝒏𝒏 𝒑𝒑𝒏𝒏 𝒙𝒙 =𝒏𝒏 𝒙𝒙𝒏𝒏 =𝒊𝒊 𝒏𝒏𝒊𝒊 𝒆𝒆𝒆𝒆𝒆𝒆 as a boundary condition
𝟐𝟐𝟐𝟐𝟐𝟐 𝟐𝟐𝟐𝟐𝟐𝟐
Both IR drop and high injection effect will cause the forward current to increase
at a slower rate.
TEMPERATURE EFFECT
𝑰𝑰𝒅𝒅𝒅𝒅𝒅𝒅𝒅𝒅 𝒏𝒏𝒊𝒊 𝑳𝑳𝒑𝒑 𝝉𝝉𝒓𝒓 At lower temp 𝑰𝑰𝒈𝒈𝒈𝒈𝒈𝒈 dominates ~𝑾𝑾~ 𝑽𝑽𝑹𝑹
=
𝑰𝑰𝒈𝒈𝒈𝒈𝒈𝒈 𝑵𝑵𝑫𝑫 𝑾𝑾 𝝉𝝉𝒑𝒑 At higher temp 𝑰𝑰𝒅𝒅𝒅𝒅𝒅𝒅𝒅𝒅 dominates 𝑰𝑰𝑹𝑹 saturated
TEMPERATURE EFFECT(Cont.)
𝑰𝑰𝒅𝒅𝒅𝒅𝒅𝒅𝒅𝒅
𝑰𝑰𝒈𝒈𝒈𝒈𝒈𝒈 ~ 𝑽𝑽𝑹𝑹
Eq.𝟓𝟓𝟖𝟖
CHARGE STORAGE
Minority- carrier storage
From Fig. 15a and Eq. 51 , the stored charge in the neutral 𝒏𝒏 – region (holes)
∞∞ ∞ ∞
𝑸𝑸𝒑𝒑 = 𝒒𝒒 ∫𝒙𝒙 𝒑𝒑𝒏𝒏 − 𝒑𝒑𝒏𝒏𝒏𝒏 𝒅𝒅𝒅𝒅 = 𝒒𝒒 ∫𝒙𝒙 𝒑𝒑𝒏𝒏𝒏𝒏 𝒆𝒆𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌 − 𝟏𝟏 𝒆𝒆(𝒙𝒙−𝒙𝒙𝒏𝒏 )/𝑳𝑳−(𝒙𝒙−𝒙𝒙
𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌
𝒑𝒑 𝒅𝒅𝒅𝒅
𝒏𝒏 )/𝑳𝑳𝒑𝒑
𝑸𝑸𝒑𝒑 = 𝒒𝒒 �
𝒏𝒏 𝒑𝒑𝒏𝒏 − 𝒑𝒑𝒏𝒏𝒏𝒏 𝒅𝒅𝒅𝒅 = 𝒏𝒏𝒒𝒒 � 𝒑𝒑𝒏𝒏𝒏𝒏 𝒆𝒆 − 𝟏𝟏 𝒆𝒆 𝒅𝒅𝒅𝒅
𝒙𝒙𝒏𝒏 = 𝒒𝒒𝑳𝑳𝒑𝒑 𝒙𝒙𝒏𝒏
= 𝒒𝒒𝑳𝑳𝒑𝒑 𝒑𝒑𝒏𝒏𝒏𝒏 𝒆𝒆𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌 − 𝟏𝟏 (75)
𝒒𝒒𝑫𝑫
𝒒𝒒𝑫𝑫
𝒒𝒒𝑫𝑫 𝒑𝒑 𝒑𝒑
𝒑𝒑𝒏𝒏𝒏𝒏
𝒑𝒑𝒑𝒑𝒏𝒏𝒏𝒏
𝒑𝒑𝒏𝒏𝒏𝒏
From Eq. 52 and 75 𝑱𝑱𝒑𝒑𝑱𝑱𝒑𝒑 𝒙𝒙𝒙𝒙𝒏𝒏𝒏𝒏 =
= 𝑳𝑳𝒑𝒑𝑳𝑳𝒑𝒑𝑳𝑳
𝒆𝒆−𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌
𝒒𝒒𝒒𝒒/𝒌𝒌𝒌𝒌
𝒆𝒆 𝟏𝟏 − 𝟏𝟏 (52)
(52)
𝒑𝒑
𝑳𝑳𝑳𝑳𝟐𝟐𝒑𝒑𝟐𝟐 𝑫𝑫𝒑𝒑 𝝉𝝉𝑫𝑫
𝑱𝑱𝒑𝒑 𝝉𝝉𝒑𝒑𝒙𝒙 = 𝝉𝝉 𝑱𝑱𝒑𝒑 𝒙𝒙𝒏𝒏
𝒑𝒑
𝑸𝑸 = 𝒑𝒑𝑱𝑱 𝒙𝒙 = (76)
𝑸𝑸𝒑𝒑𝒑𝒑= 𝑫𝑫𝒑𝒑 𝒑𝒑𝑱𝑱𝒑𝒑 𝒏𝒏𝒙𝒙𝒏𝒏 =𝑫𝑫𝒑𝒑 𝒑𝒑 𝑱𝑱𝒏𝒏𝒑𝒑 𝒙𝒙𝒏𝒏 𝒑𝒑 = 𝝉𝝉𝒑𝒑 𝑱𝑱𝒑𝒑 𝒙𝒙𝒏𝒏
𝑫𝑫𝒑𝒑 𝑫𝑫𝒑𝒑
Therefore the stored charge in the neutral region = product of the current
and the minority carrier lifetime.
CHARGE STORAGE(Cont.)
EXAMPLE 7
For an ideal abrupt silicon 𝒑𝒑+⎼𝒏𝒏 junction with 𝑵𝑵𝑫𝑫 = 𝟖𝟖 × 𝟏𝟏𝟏𝟏𝟏𝟏𝟏𝟏 cm−𝟑𝟑 ,
calculate the stored minority carriers per unit area in the neutral 𝒏𝒏-
region when a forward bias of 1V is applied. The diffusion length of
the holes is 5μm.
𝝐𝝐𝝐𝝐𝒔𝒔𝒔𝒔
We have 𝑪𝑪𝒋𝒋 = 𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣 𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜 = 𝑨𝑨 𝑾𝑾 𝑨𝑨
𝑾𝑾
𝟐𝟐
𝒒𝒒𝒒𝒒𝟐𝟐𝑳𝑳𝑳𝑳 𝒒𝒒𝒒𝒒
𝒑𝒑
𝒑𝒑 𝒑𝒑𝒏𝒏𝒏𝒏 𝒒𝒒𝒒𝒒 +
𝑪𝑪𝒅𝒅 = 𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝𝐝 𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜𝐜 = 𝑨𝑨𝑨𝑨 𝒌𝒌𝒌𝒌𝒑𝒑 𝒏𝒏𝒏𝒏𝒆𝒆𝒌𝒌𝒌𝒌 𝒆𝒆𝒌𝒌𝒌𝒌 (for 𝒑𝒑 𝒏𝒏)
𝒌𝒌𝒌𝒌
due to electron penetration through the bandgap. For high dopings on both sides.
𝑬𝑬𝑬𝑬𝒈𝒈𝒈𝒈
Avalanche Multiplication: 𝑽𝑽𝑩𝑩 > 𝟔𝟔𝟔𝟔 𝒒𝒒 (For Si 𝑽𝑽𝑩𝑩 > 𝟕𝟕V)
𝒒𝒒
due to generation of electron-hole pairs under applied high field.
𝑬𝑬𝑬𝑬𝒈𝒈 𝑬𝑬𝑬𝑬𝒈𝒈
𝒈𝒈
𝟒𝟒𝟒𝟒 𝒒𝒒 < 𝑽𝑽𝑩𝑩 < 𝟔𝟔𝟔𝟔 𝒒𝒒
𝒈𝒈
Mixture of tunneling and avalanche:
𝒒𝒒 𝒒𝒒
Fig 22. shows the energy band diagrams under junction-breakdown
conditions.(a)Tunneling effect.(b)Avalanche multiplication.
JUNCTION BREAKDOWN
For avalanche multiplication, we define a multiplication factor
𝑰𝑰𝒏𝒏 (𝑾𝑾) (81)
𝑴𝑴𝒏𝒏 ≡
𝑰𝑰𝒏𝒏𝒏𝒏
𝑰𝑰𝒏𝒏𝒏𝒏 is the current incident at the left-hand side of the depletion region(𝒙𝒙 = 0)
𝑰𝑰𝒏𝒏 (𝑾𝑾) is the current at 𝒙𝒙 = w.
Total current 𝑰𝑰 = 𝑰𝑰𝒑𝒑 + 𝑰𝑰𝒏𝒏 ≠ 𝒇𝒇(𝒙𝒙)
𝒅𝒅𝑰𝑰𝒏𝒏
+ 𝑰𝑰𝒏𝒏 𝜶𝜶𝒑𝒑 − 𝜶𝜶𝒏𝒏 = 𝜶𝜶𝒑𝒑 𝑰𝑰 (82a)
𝒅𝒅𝒅𝒅
JUNCTION BREAKDOWN
If 𝜶𝜶 = 𝜶𝜶⍺
⍺n𝒏𝒏 = 𝒑𝒑 p= 𝜶𝜶
𝒅𝒅𝑰𝑰𝒏𝒏
= 𝜶𝜶𝜶𝜶
𝒅𝒅𝒅𝒅
𝒘𝒘 𝒘𝒘
𝒅𝒅𝑰𝑰𝒏𝒏
� = � 𝜶𝜶𝜶𝜶𝜶𝜶
𝟎𝟎 𝑰𝑰 𝟎𝟎
𝑰𝑰𝒏𝒏 𝒘𝒘 𝒘𝒘
� = � 𝜶𝜶𝜶𝜶𝜶𝜶
𝑰𝑰 𝟎𝟎 𝟎𝟎
(𝟎𝟎)) 𝒘𝒘
𝑰𝑰𝒏𝒏 𝑰𝑰𝒘𝒘𝒏𝒏 𝒘𝒘−−𝑰𝑰 𝑰𝑰𝒏𝒏𝒏𝒏(𝟎𝟎
== � 𝜶𝜶𝜶𝜶𝜶𝜶
𝑰𝑰 𝑰𝑰
𝟎𝟎 𝒘𝒘
𝟏𝟏
∵ 𝑰𝑰 = 𝑰𝑰𝒏𝒏 (𝒘𝒘) ∴ 𝟏𝟏 − = � 𝜶𝜶𝜶𝜶𝜶𝜶 Where 𝑴𝑴𝐧𝐧 = 𝑰𝑰⁄𝑰𝑰𝒏𝒏(𝟎𝟎)
𝑴𝑴𝒏𝒏 𝟎𝟎
The critical field ℰ𝒄𝒄 is the maximum electric field at breakdown (shown in
Fig.24)
once ℰ𝒄𝒄 is known, we can calculate the breakdown voltage ℰ
ℰ𝒄𝒄
For one-sided abrupt junction
𝜺𝜺 𝒘𝒘 𝜺𝜺𝓔𝓔𝒄𝒄𝝐𝝐𝝐𝝐𝒄𝒄𝒔𝒔𝒔𝒔𝝐𝝐𝜺𝜺𝜺𝜺𝒔𝒔𝒄𝒄𝓔𝓔
𝒘𝒘
𝜺𝜺𝓔𝓔𝒄𝒄𝒄𝒄𝒄𝒄𝒘𝒘 𝝐𝝐𝒔𝒔𝒔𝒔𝝐𝝐𝜺𝜺𝜺𝜺𝒔𝒔𝟐𝟐𝒄𝒄2𝒄𝒄𝓔𝓔𝟐𝟐𝒄𝒄
𝒄𝒄 𝒄𝒄 𝝐𝝐
𝑽𝑽𝑽𝑽𝑩𝑩𝑩𝑩 == == == (𝑵𝑵𝑩𝑩𝑵𝑵)𝑩𝑩−𝟏𝟏−𝟏𝟏 (85)
𝟐𝟐𝟐𝟐 𝟐𝟐𝟐𝟐𝒒𝒒𝑵𝑵
𝒒𝒒𝑵𝑵
𝑩𝑩 𝑩𝑩 𝟐𝟐𝟐𝟐𝟐𝟐𝒒𝒒
x
0 w
Onset of tunneling
AVALANCHE BREAKDOWN VOLTAGE
Example 8
Calculate the breakdown voltage for a Si one-side 𝒑𝒑+⎼𝒏𝒏 𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚 𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣𝐣 𝐰𝐰𝐰𝐰𝐰𝐰𝐰𝐰
𝑵𝑵𝑫𝑫 = 5×1016 𝐜𝐜𝐦𝐦−𝟑𝟑
SOLUTION
From Fig. 24,we see that the critical field at breakdown for a Si one-sided
abrupt junction is about 5.5×105 𝐕𝐕/𝐜𝐜𝐜𝐜. Then from Eq.85, we obtain
= 𝟏𝟏𝟏𝟏 V
BREAKDOWN VOLTAGE FOR PUNCH –
THROUGH DIODES
Figure 27 shows the breakdown voltage for 𝒑𝒑+-𝝅𝝅−𝒏𝒏+ and 𝒑𝒑+-𝝂𝝂−𝒏𝒏+ junctions.
𝑾𝑾 is the thickness of the lightly doped 𝒑𝒑-type(𝜋𝜋)or the lightly doped 𝒏𝒏-type(𝝂𝝂) 𝐫𝐫𝐫𝐫𝐫𝐫𝐫𝐫𝐫𝐫𝐫𝐫.
In Fig.25, it is assume that the semiconductor layer is thick enough to support the
reverse – biased depletion layer width 𝑾𝑾𝒎𝒎 at breakdown.
If 𝑾𝑾 is less than 𝑾𝑾𝒎𝒎 , the device will be punched through.
𝑽𝑽𝑽𝑽 ′ 𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬 𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚 𝐢𝐢𝐢𝐢 𝐭𝐭𝐭𝐭𝐭𝐭 𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢 𝓔𝓔 𝑾𝑾 ⁄𝟐𝟐 − 𝓔𝓔𝓔 𝑾𝑾𝒎𝒎 − 𝑾𝑾 ⁄𝟐𝟐
𝑩𝑩𝑩𝑩’ =𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬𝐬 𝐚𝐚𝐚𝐚𝐚𝐚𝐚𝐚 𝐢𝐢𝐢𝐢 𝐭𝐭𝐭𝐭𝐭𝐭 𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢𝐢= 𝒄𝒄 𝒎𝒎
= 𝓔𝓔𝒄𝒄𝒄𝒄 𝑾𝑾
𝑾𝑾𝒎𝒎 = 𝓔𝓔𝒄𝒄 𝑾𝑾𝒎𝒎 ⁄𝟐𝟐
𝑽𝑽𝑽𝑽
𝑩𝑩𝑩𝑩
𝓔𝓔
( 𝟐𝟐𝟐𝟐 )
𝒎𝒎
𝓔𝓔𝓔
𝓔𝓔′ 𝑾𝑾 − 𝑾𝑾
𝑾𝑾𝒎𝒎𝒎𝒎−𝑾𝑾
∵ 𝓔𝓔 = 𝑾𝑾𝑾𝑾𝒎𝒎
=
𝓔𝓔 𝒎𝒎 𝓔𝓔’
𝑾𝑾 𝑾𝑾
= 𝟐𝟐 −
𝑾𝑾𝒎𝒎 𝑾𝑾𝒎𝒎 (87)
PUNCH-THROUGH DIODES
EXAMPLE 9
For GaAs 𝒑𝒑+-𝒏𝒏 one sided abrupt junction with 𝑵𝑵𝑫𝑫 = 𝟖𝟖 × 𝟏𝟏𝟎𝟎𝟏𝟏𝟏𝟏 cm−𝟑𝟑 ,
calculate the depletion width at breakdown. If the 𝒏𝒏-type region of this
structure is reduced to 20𝐮𝐮𝐮𝐮, calculate the breakdown voltage.
PUNCH-THROUGH DIODES(Cont.)
Solution
From Fig. 25, we can find that the breakdown voltage(𝑽𝑽𝑩𝑩 ) is about 𝟓𝟓𝟓𝟓𝟓𝟓 𝐕𝐕,
which is much larger than the built-in voltage (𝑽𝑽𝒃𝒃𝒃𝒃 ). And from Eq. 27, we obtain
When the 𝒏𝒏-type region reduces to 20𝐮𝐮𝐮𝐮, punch-through will occur first. From
Eq. 87, we can obtain
𝑾𝑾 𝑾𝑾 𝟐𝟐𝟐𝟐 𝟐𝟐𝟐𝟐
𝑽𝑽′𝐁𝐁 = 𝑽𝑽𝑩𝑩 𝟐𝟐 − = 𝟓𝟓𝟓𝟓𝟓𝟓 × 𝟐𝟐 − = 𝟒𝟒𝟒𝟒𝟒𝟒 𝐕𝐕
𝑾𝑾𝒎𝒎 𝑾𝑾𝒎𝒎 𝟐𝟐𝟐𝟐. 𝟑𝟑 𝟐𝟐𝟐𝟐. 𝟑𝟑
JUNCTION CURVATURE EFFECT