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Ultrathin Body SOI MOSETs

VLSI Design Techniques Course Project
Ronak Jaiswal (B14EE013)
Jay Sheth (B14EE014)

scale gate length and reduce sub-threshold gate leakage current. SOI MOSFET .What is SOI?  SOI uses Silicon On Silicon insulator instead of Si substrate only  SOI is used to reduce parasitic device Bulk MOSFET capacitance which improves the performance  The choice of insulator can be varied depending on the requirement  UTB-SOI suppress Short Channel Effects.

sub-threshold swing. near ideal sub-threshold swing.Performance of SOI  90% lower junction capacitance. and kink effects: minimized by thinner silicon.  Lower junction leakage -> low switching energy of the transistor  Do not suffer from substrate reverse bias effects -> low-power devices. reduce device cross-talk.  Full dielectric isolation of the transistor  Reduced junction area  Impact ionization strongly balanced by thermal recombination.  Critical drawback as: floating body effects: body potential shifts –shift in 𝑉𝑡 . .  Better electrostatic control: reduce S-D leakage and SCE.

Improved power consumption characteristics .Types of SOI Devices  Two types of SOIs 1. Fully Depleted (FDSOI)  FDSOI is preferred over PDSOI because 1. Thinner size 2. Reduced leakage current 3. Partially Depleted (PDSOI) 2.

PDSOI vs FDSOI PDSOI FDSOI  Insulating BOX thickness is 100 to  Insulating BOX thickness is 5 to 200nm 50nm  Top silicon layer 50 to 90nm  Top silicon 5 to 20nm  Used in analog circuit  Low power applications  Easy to manufacture  Leakage and power consumption reduced drastically  Drawback: complex fabrication  Drawback: packaging scalability process .

FDSOI: Ultrathin Body SOI  PDSOI is the same in operation as bulk transistors except for the Floating Body Terminals Effects  In FDSOI case. threshold voltage. . the front and back channels are electro- statically coupled during device operation  This electrostatic coupling. including drain current. makes the front channel FD device parameters dependent on the back gate voltage. sub-threshold slope etc.

Parasitic Capacitances .

µ µ𝑛0 = 1+Ѳ𝑉0 𝐺𝑆𝑇 𝛽𝜃 Where 𝜃 = 𝑡𝑓𝑜𝑥 Carrier mobility as a function of 𝑉𝐶𝑆 µ𝑛0 µ𝑛 𝑦 = µ 𝑑𝑉 ′ 𝑦 1+ 𝑛0 𝑐𝑠 𝑣𝑠𝑎𝑡 𝑑𝑦 where 𝑉𝑐𝑠 𝑦 = 𝑉𝑐𝑠′ 𝑦 + 𝐼𝐷𝑆 𝑅𝑠 𝑣𝑠𝑎𝑡 is saturation velocity for electrons µ0 is carrier mobility of electrons at temperature 𝑇0 .Carrier Mobility Considerations Carrier mobility for a given 𝑉𝐺𝑆 .

5𝛾𝑠𝑢𝑏𝑠 (1 + ′ ) 𝐶𝑆𝑖 𝐷 = 𝐵2 − 𝛼 + 𝜙0 + 𝑉𝑆𝐵 and 𝑉𝑇 = 𝑉𝐹𝐵 +𝜙0 + 𝑞𝑁𝑐ℎ 𝑡𝑆𝑖ൗ𝐶 ′ 𝑓𝑜𝑥 ′ ′ 𝛾 ′ = 𝛾𝑠𝑢𝑏𝑠 𝐶𝑏𝑜𝑥 /𝐶𝑓𝑜𝑥 2 𝛼 = 𝑞𝑁𝑐ℎ 𝑡𝑠𝑖 /2𝜖𝑠 . Inversion Charge Considrations 𝑄𝑖′ = −𝐶 ′𝑓𝑜𝑥 𝑉𝐺𝑆𝑇 − 𝑉𝐶𝑆 ′ 𝑦 − 𝛾 ′ −𝐵 + 𝐷 + 𝑉𝐶𝑆 𝑦 ′ + 𝐶𝑓𝑜𝑥 𝐼𝐷𝑆 𝑅𝑆 ′ 𝐶𝑏𝑜𝑥 Where 𝐵 = 0.

Drain Current Considerations Using the drift-Diffusion. 𝑉 ′ ′ 𝐻[𝑉𝐺𝑆𝑇ƞ − 𝐷2 𝑆 ]𝑉𝐷′ 𝑆′ 𝐼𝐷𝑆 = µ 𝐿 + 𝑣 𝑛0 +𝐻𝑅𝑆 𝑉𝐷′ 𝑆′ 𝑠𝑎𝑡 ′ where 𝐻 = 𝑊µ𝑛0 𝐶𝑓𝑜𝑥 𝑉𝐺𝑆𝑇ƞ = 𝑉𝐺𝑆𝑇 − ƞ γ′ δ γ′ Ƞ= − ɸ𝑡 (1 + ) 2𝐵 2 𝐷 δ = ɸ0 − α + 𝑉𝑆𝐵 . equation for channel current Current equation can be obtained.

Drain Current … Solution of above equation is −𝑃1 − 𝑃12 − 4𝑃2 𝑃0 𝐼𝐷𝑆 = 2𝑃2 𝐻𝑅𝑇 (𝑅𝑆 −𝑅𝐷 ) 𝑅𝑇 µƞ0 where 𝑃2 = + 2 𝑣𝑠𝑎𝑡 𝑅𝐷 𝑉𝐷𝑆 𝑉𝐷𝑆 µƞ0 𝑃1 = −𝐻𝑅𝑇 𝑉𝐺𝑆𝑇ƞ − −𝐿− 𝑅𝑇 𝑣𝑠𝑎𝑡 𝑉𝐷𝑆 𝑃0 = 𝐻 𝑉𝐺𝑆𝑇ƞ − 𝑉𝐷𝑆 2 .

Drain Current … Using the equation of 𝐼𝐷𝑆 we can obtain 𝑉𝑑𝑠𝑎𝑡 −G1 − G12 − 4G2 G0 vdsat = 2G2 where G2 = 𝐻Γ 2 [2𝑢 + 𝐻(𝑅𝑆 − 𝑅𝐷 )]𝑅𝑇 G1 = 2𝐻𝑅𝑇 (Γ + 1) L − H𝑅𝑇 𝑉𝐺𝑆𝑇ƞ Γ G0 = (H𝑅𝑇 𝑉𝐺𝑆𝑇ƞ Γ − 𝐿)2 −(H𝑅𝑇 𝑉𝐺𝑆𝑇ƞ + 𝐿)2 µƞ0 𝑢+𝐻𝑅𝑠 with u = and Γ = 𝑣𝑠𝑎𝑡 𝑢−𝐻𝑅𝐷 Substituting the value of 𝑉𝑑𝑠𝑎𝑡 in the channel current equation we can obtain 𝐼𝑑𝑠𝑎𝑡 VGSTƞ −Vdsat Idsat = u −R H D .

1 V (Experimentally calculated) The coefficients get updated to following as equation of I𝐷𝑆 changes ′ 𝑊𝐶𝑓𝑜𝑥 𝑅𝑇 (𝑅𝑆 −𝑅𝐷 ) 𝑅𝑇 2𝐴L𝑒𝑓𝑓 𝑉𝐷𝑆 𝑃2 = 2 +𝑣 − µna 𝑠𝑎𝑡 ′ 𝑅𝐷 𝑉𝐷𝑆 L𝑒𝑓𝑓 𝑉 𝑃1 = −𝑊𝐶𝑓𝑜𝑥 𝑅𝑇 𝑉𝐺𝑆𝑇ƞ − − − 𝑣 𝐷𝑆 𝑅𝑇 µna 𝑠𝑎𝑡 ′ 𝑉𝐷𝑆 𝑃0 = 𝑊𝐶𝑓𝑜𝑥 𝑉𝐺𝑆𝑇ƞ − 𝑉𝐷𝑆 2 .22 cm Τ6 )𝑑𝑗 2 𝑡𝑜𝑥3 d𝑗 being drain junction depth V𝐸 ≃ 0.Channel Length Modulation Channel length modulation L𝑒𝑓𝑓 = 𝐿 − ΔL VDS −Vdsat where ΔL = Ɩa ln[ 1 + ] VE 1 1Τ 1Τ with Ɩa ≃ (0.

Improved transistor sub-threshold swing due to greatly improved gate control  Reduced parasitic capacitances from the absence of depletion capacitances.  Thin body thickness.Advantages of FDSOI (UTB SOI)  Small and well-controlled channel thickness. leading to improved speed (due to complete isolation of p and n wells)  Reduced antenna issues  No body or well taps are needed . high series resistance  Reduced floating body effects compared to PDSOI.

Advantages …  Reduced power consumption due to better isolation of body terminal reduces the leakage current  Higher performance at equivalent 𝑉𝑑𝑑 .  Reduced temperature dependency due to no doping  Variation of 𝑉𝑡 due to variation of body thickness overcomes all other factors in UTB-SOI devices  Improved channel mobility due to reduced transverse electric field . Can work at low 𝑉𝑑𝑑 .

gate current is worst at short-channel.  It has higher manufacturing process complexity due to the BOX layer  The buried oxide layer and concerns about differential stress in the topmost silicon layer. which contributes an estimated 10–15% increase to total manufacturing costs.Drawbacks of FDSOI (UTB SOI)  The primary barrier to SOI implementation is the drastic increase in substrate cost.  Reduces parasitic drain-to-body capacitance but drain field fringe increases DIBL and hence. .

lower dynamic and static power and better immunity to soft errors. .  In high performance radio frequency applications  Low Power Applications like laptops etc.  Used in photonics  In MEMS (Micro-Electro-Mechanical Systems) like Sensors etc.Applications  The buried oxide layer can be used in SRAM memory  High Performance microprocessors: due to higher performance.

Knoch. Deb et. R. 7. Phys.References 1.wikipedia. 2005. M. S. S.K. Electron Devices. & Dutta. J. Lett. M. Appl. J. Analytical model of threshold voltage and sub-threshold slope of SOI and SON MOSFET: A comparative study. A. . J. 2010. al (2010). Pandey. Semiconductors (2013) 47: 1224. S. 4. 87. 6. 300-309 3. Dec. Mantl. 1669-1674. S. Lenk. "Effective Schottky- barrier lowering in silicon-on-insulator Schottky-barrier metal–oxide–semiconductor field-effect transistors using dopant segregation". Jul. 2006. IEEE Trans. Zhang. vol. Vol. 263505-1-263505-3. pp. pp. https://en. T. 53. Zhao.1134/S1063782613090182 2. Appenzeller. 8. Appenzeller.. Zhang. 5. https://en. Knoch. no. J. 26. vol.wikipedia. Q. "On the performance of single-gated ultrathin body SOI Schottky-barrier MOSFETs". Journal of Electron Devices. pp.

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