Combinational Logic Circuit Design and Concurrent Coding in VHDL

"When" and "Select" Statements

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The VHDL statements when and select can be employed in concurrent VHDL codes.
These statements are not used in sequential, i.e., clocked, program units.

We can employ VHDL statements when and select for the implementation of
combinational circuits. These statements are employed for the conditional
implementation of the logic circuits.

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 The syntax of the when statement is as follows:

<signal object> <= <statement> when <condition> else

<statement> when <condition> else
…
<statement> when <condition> else
<statement>;

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The syntax of the select statement is as follows:

with <condition> select

<signal object> <= <statement> when <condition>,
<statement> when <condition>,
…
<statement> when others;

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Example-2.1: Implement the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 using logical
operators.
Solution-2.1: The Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 can be implemented using logical
operators as
f<=(not(x) and not(y)) or (not(y) and z)

A VHDL program that implements the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 can be

written as in PR 2.1.
entity f_function is
port( x, y, z: in bit;
f: out bit );
end entity;
PR 2.1 Program 2.1.
architecture logic_flow of f_function is

begin
f<=(not(x) and not(y)) or (not(y) and z);
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end architecture;
Example-2.2: The truth table of a Boolean function is given as

Table 2-1 Truth table of a Boolean function.

x y z f ( x, y , z )
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

Implement the Boolean function using when and select statements.

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Solution-2.2: With when statement, it can be implemented as

f<='1' when (x='0' and y='0' and z='0') else

'1' when (x='0' and y='0' and z='1') else
'1' when (x='1' and y='0' and z='1') else
'0';

With select statement, it can be implemented as

with (x&y&z) select

f<='1' when "000",
'1' when "001",
'1' when "101",
'0' when others;

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Example-2.3: Implement the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 using when statement.

Solution-2.3: First, let's construct the truth table of the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ +
𝑦′𝑧.

If the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 is inspected in details, we see that the function
takes the value of 1 for 𝑥 = 𝑦 = 0 or for 𝑦 = 0, 𝑧 = 1.

Considering this information, we can make the truth table of the given Boolean function as in
Table 2-2

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Table 2-2 Truth table of 𝑓 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧.
x y z f ( x, y , z )
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0

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Regarding the truth table, we can write VHDL program with when statement as in PR 2.2.
entity f_function is
port( x, y, z: in bit;
f: out bit );
end entity;

architecture logic_flow of f_function is

begin
f<='1' when (x='0' and y='0' and z='0') else
'1' when (x='0' and y='0' and z='1') else
'1' when (x='1' and y='0' and z='1') else
'0';
end architecture;
PR 2.2 Program 2.2. 10
 The program in PR 2.2 can also be written as in PR 2.3.

entity f_function is
port( xyz: in bit_vector(2 downto 0);
f: out bit );
end entity;

architecture logic_flow of f_function is

begin
f<='1' when (xyz(2)='0' and xyz(1)='0' and xyz(0)='0') else
'1' when (xyz(2)='0' and xyz(1)='0' and xyz(0)='1') else
'1' when (xyz(2)='1' and xyz(1)='0' and xyz(0)='1') else
'0';
end architecture;
PR 2.3 Program 2.3.
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 Example-2.4: We can implement the Boolean function 𝑓 𝑥, 𝑦, 𝑧 = 𝑥 ′ 𝑦 ′ + 𝑦′𝑧 using
select statement as in PR 2.4.
entity f_function is
port( x, y, z: in bit;
f: out bit );
end entity;

architecture logic_flow of f_function is

begin
with (x&y&z) select
f<='1' when "000",
'1' when "001",
'1' when "101",
'0' when others;
end architecture;
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PR 2.4 Program 2.4.
Example-2.5: Implement the function in equation below using VHDL

& &&&&𝑖𝑓&&&𝑥 = 1&𝑜𝑟&𝑥 = 2

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𝑓(𝑥) = &4&&&&𝑖𝑓&&&3 ≤ 𝑥 ≤ 6&&&&&&&&&
&0&&&&𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒.&&&&&&&&&&&&&

Solution-2.5: The real valued function given in the question can be implemented in VHDL as in
PR 2.5

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entity fx_function is
port( x: in integer;
y: out integer range 0 to 4);
end entity;

architecture logic_flow of fx_function is

begin
with x select
y <= 2 when 1 | 2,
4 when 3 to 6,
0 when others;
end architecture;

PR 2.5 Program 2.5.

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