5 4 3 2 1

Table of Contents Revisions

Rev Date Approved
2 Notes/Block Diagram Description

3 MICROCONTROLLER A Final Release 30 Mar 20

4 COMMUNICATION
5 GATE DRIVER 1. Update board name and block diagram.
6 POWER STAGE A1 2. Change document classification to Public 14 May 20

D D

C C

0&6;7(%.
02725&21752/'(9(/230(17%2$5'

B B

A A
Automotive Product Group
6501 William Cannon Drive West
Austin, TX 78735-8598
This document contains information proprietary to NXP and shall not be used for engineering design,
procurement or manufacture in whole or in part without the express written permission of NXP Semiconductors.

© NXP SEMICONDUCTORS Classification: Public

Designer: Drawing Title:
Raymond Tang
MCSXTE2BK142
Drawn by: Page Title:
Raymond Tang TITLE PAGE
Approved: Size Document Number Rev
Jesus Sanchez C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 1 of 6

5 4 3 2 1
 5 4 3 2 1

1. Unless Otherwise Specified: 4. Special signal usage:

All resistors are in ohms, 5%, 1/10 Watt
_B Denotes - Active-Low Signal
All capacitors are in uF, 20%, 50V
All voltages are DC <> or [] Denotes - Vectored Signals
All polarized capacitors are aluminum electrolytic
2. Interrupted lines coded with the same letter or letter 5. Interpret diagram in accordance with American
D combinations are electrically connected. National Standards Institute specifications, current D
revision, with the exception of logic block symbology.
3. Device type number is for reference only. The number
varies with the manufacturer.

C C

B B

A A

Classification: Public
Drawing Title:
MCSXTE2BK142
Page Title:
NOTES/ BLOCK DIAGRAM
Size Document Number Rev
C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 2 of 6

5 4 3 2 1
 5 4 3 2 1

6.0LFURFRQWUROOHU
J1 J2
5 R1 120.0 TRGMUX_OUT0 4 R3 120.0 FMT_RX
4 R4 120.0 TRGMUX_OUT1 3 R5 120.0 FMT_TX
D TRGMUX_OUT3 D
3 R2 120.0 2
2 R6 120.0 TRGMUX_OUT4 VDD VDDA 1
1 R7 120.0 TRGMUX_OUT5
C1
HDR 1X4 1uF GND
HDR 1X5 SILK = FMT
SILK = TRGMUX
75*08;287 C2 C4 C6 C7 C8 C9
VDD
)UHH0$67(577/
4.7uF 0.1uF 0.1uF 1nF 0.1uF 1nF

GND GND GNDA GNDA

41
7

9
U1

VDD1
VDD2

VDDA

VREFH
TRGMUX_OUT3 50
TRGMUX_OUT0 49 PTA0/FTM2_CH1/LPI2C0_SCLS/FXIO_D2/FTM2_QD_PHA/LPUART0_CTS/TRGMUX_OUT3/ADC0_SE0/CMP0_IN0
R8 0 48 PTA1/FTM1_CH1/LPI2C0_SDAS/FXIO_D3/FTM1_QD_PHA/LPUART0_RTS/TRGMUX_OUT0/ADC0_SE1/CMP0_IN1
P5 PWMA_HS_B PTA2/FTM3_CH0/LPI2C0_SDA/EWM_OUT_B/FXIO_D4/LPUART0_RX/ADC1_SE0
R9 0 47
P5 PWMA_LS JTAG_TMS/SWD_DIO PTA3/FTM3_CH1/LPI2C0_SCL/EWM_IN/FXIO_D5/LPUART0_TX/ADC1_SE1
64
RESET_b 63 PTA4/CMP0_OUT/EWM_OUT_B/JTAG_TMS/SWD_DIO
38 PTA5/TCLK1/RESET_B
P6 PHC_Bemf 37 PTA6/FTM0_FLT1/LPSPI1_PCS1/LPUART1_CTS/ADC0_SE2
JTAG_TDO P6 PHB_Bemf 58 PTA7/FTM0_FLT2/RTC_CLKIN/LPUART1_RTS/ADC0_SE3
R10 0
57 PTA10/FTM1_CH4/FXIO_D0/JTAG_TDO/NOETM_TRACE_SWO
56 PTA11/FTM1_CH5/FXIO_D1/CMP0_RRT
DNP P4 CAN1_RX 55 PTA12/FTM1_CH6/CAN1_RX/FTM2_QD_PHB
P4 CAN1_TX PTA13/FTM1_CH7/CAN1_TX/FTM2_QD_PHA
R11 0
P4 PWM_IN 34 2 TRGMUX_OUT1
P5 GD_CS_B 33 PTB0/LPUART0_RX/LPSPI0_PCS0/LPTMR0_ALT3/CAN0_RX/ADC0_SE4/ADC1_SE14 PTD0/FTM0_CH2/LPSPI1_SCK/FTM2_CH0/FXIO_D0/TRGMUX_OUT1 1 ENC_Z
PWM Duty measurement should
i assign to flextimer even channel
P5
P5
GD_MOSI
GD_SCLK
32 PTB1/LPUART0_TX/LPSPI0_SOUT/TCLK0/CAN0_TX/ADC0_SE5/ADC1_SE15
PTB2/FTM1_CH0/LPSPI0_SCK/FTM1_QD_PHB/TRGMUX_IN3/ADC0_SE6
PTD1/FTM0_CH3/LPSPI1_SIN/FTM2_CH1/FXIO_D1/TRGMUX_OUT2
PTD2/FTM3_CH4/LPSPI1_SOUT/FXIO_D4/FXIO_D6/TRGMUX_IN5/ADC1_SE2
46 R12 0
PWMC_HS_B P5
31 45 R13 0
P5 GD_MISO 19 PTB3/FTM1_CH1/LPSPI0_SIN/FTM1_QD_PHA/TRGMUX_IN2/ADC0_SE7 PTD3/FTM3_CH5/LPSPI1_PCS0/FXIO_D5/FXIO_D7/TRGMUX_IN4/NMI_B/ADC1_SE3 44 PWMC_LS P5
C10 P5 GD_EN 18 PTB4/FTM0_CH4/LPSPI0_SOUT/TRGMUX_IN1 PTD4/FTM0_FLT3/FTM3_FLT3/ADC1_SE6 24 Current_C P6
P5 GD_RST_B 12 PTB5/FTM0_CH5/LPSPI0_PCS1/LPSPI0_PCS0/CLKOUT/TRGMUX_IN0 PTD5/FTM2_CH3/LPTMR0_ALT2/FTM2_FLT1/TRGMUX_IN7 23 CAN_EN P4
CAN_STB P4
2

11 PTB6/LPI2C0_SDA/XTAL PTD6/FTM2_FLT2/CMP0_IN7 22
43 PTB7/LPI2C0_SCL/EXTAL PTD7/FTM2_FLT3/CMP0_IN6 15 HALL_B CAN_ERR P4
C Y1 D1 RED C
12PF P5 GD_INT 42 PTB12/FTM0_CH0/FTM3_FLT2/ADC1_SE7 PTD15/FTM0_CH0/LPSPI0_SCK 14 HALL_A
8MHZ R14 R15 680 VDD
P6 Current_B PTB13/FTM0_CH1/FTM3_FLT1/ADC1_SE8/ADC0_SE8 PTD16/FTM0_CH1/LPSPI0_SIN/CMP0_RRT C A
C11 1.0M
26
25 PTC0/FTM0_CH0/FTM1_CH6/ADC0_SE8 60 LED_R R16 680
P6 Current_A
1

FMT_RX 21 PTC1/FTM0_CH1/FTM1_CH7/ADC0_SE9 PTE0/LPSPI0_SCK/TCLK1/LPSPI1_SOUT/FTM1_FLT2 59 LED_G C A

FMT_TX 20 PTC2/FTM0_CH2/CAN0_RX/LPUART0_RX/ADC0_SE10/CMP0_IN5 PTE1/LPSPI0_SIN/LPI2C0_HREQ/LPSPI1_PCS0/FTM1_FLT1 54
12PF PTC3/FTM0_CH3/CAN0_TX/LPUART0_TX/ADC0_SE11/CMP0_IN4 PTE2/LPSPI0_SOUT/LPTMR0_ALT3/FTM3_CH6/LPUART1_CTS/ADC1_SE10 BusVoltage P6
JTAG_TCLK/SWD_CLK 62 13
GND JTAG_TDI 61 PTC4/FTM1_CH0/RTC_CLKOUT/EWM_IN/FTM1_QD_PHB/JTAG_TCLK/SWD_CLK/CMP0_IN2 PTE3/FTM0_FLT0/FTM2_FLT0/TRGMUX_IN6/CMP0_OUT 6 ENC_B D2 HSMG-C170
R17 0 52 PTC5/FTM2_CH0/RTC_CLKOUT/FTM2_QD_PHB/JTAG_TDI PTE4/FTM2_QD_PHB/FTM2_CH2/CAN0_RX/FXIO_D6/EWM_OUT_B 5 ENC_A
P5 PWMB_HS_B PTC6/LPUART1_RX/CAN1_RX/FTM3_CH2/FTM1_QD_PHB/ADC1_SE4 PTE5/TCLK2/FTM2_QD_PHA/FTM2_CH3/CAN0_TX/FXIO_D7/EWM_IN
R18 0 51 53
P5 PWMB_LS PTC7/LPUART1_TX/CAN1_TX/FTM3_CH3/FTM1_QD_PHA/ADC1_SE5 PTE6/LPSPI0_PCS2/FTM3_CH7/LPUART1_RTS/ADC1_SE11
36 39
P4 LIN_RX 35 PTC8/LPUART1_RX/FTM1_FLT0/LPUART0_CTS PTE7/FTM0_CH7/FTM3_FLT0 17 GD_OC P5
P4 LIN_TX 30 PTC9/LPUART1_TX/FTM1_FLT1/LPUART0_RTS PTE8/FTM0_CH6/CMP0_IN3 16 HALL_C LIN_SLP P4
P6 PHA_Bemf 29 PTC14/FTM1_CH2/TRGMUX_IN9/ADC0_SE12 PTE9/FTM0_CH7 4 TRGMUX_OUT4
P6 Tem_MOSFET 28 PTC15/FTM1_CH3/TRGMUX_IN8/ADC0_SE13 PTE10/CLKOUT/FTM2_CH4/FXIO_D4/TRGMUX_OUT4 3 TRGMUX_OUT5
P6 Analog IN 27 PTC16/FTM1_FLT2/ADC0_SE14 PTE11/LPTMR0_ALT1/FTM2_CH5/FXIO_D5/TRGMUX_OUT5

VSS1
VSS2
P5 DCBI PTC17/FTM1_FLT3/ADC0_SE15

FS32K142HAT0MLHT

10
40
0000
SJ1
1 2
0000
GND GNDA

B B
J3
VDD
5
4 JTAG_TMS/SWD_DIO VDD VDD
3 JTAG_TCLK/SWD_CLK
2
1 RESET_b
VDD
R19 R20 R21 R22 R23 R24
HDR 1X5 GND 4.7K 4.7K 4.7K SILK = HALL_A 4.7K 4.7K 4.7K
SILK = SWD TP1 TP2 TP3 SILK = ENC_A
R25 TP4 SILK = HALL_B TP5
J5 J6
10.0K TP6 TP7 SILK = ENC_B
VDD 5 R26 33 HALL_A TP8 5 R27 33 ENC_A TP9
J4 4 HALL_B 4 ENC_B
R28 33 SILK = HALL_C R29 33 SILK = ENC_Z
1 2 JTAG_TMS/SWD_DIO 3 R30 33 HALL_C 3 R31 33 ENC_Z
3 4 JTAG_TCLK/SWD_CLK 2 2
5 6 JTAG_TDO 1 C12 C13 C14 1 C15 C16 C17
7 8 R32 0 JTAG_TDI C18 C19 C20 C21 100PF 100PF 100PF
9 10 RESET_b 0.1uF 470PF 470PF 470PF 0.1uF
HDR 1X5 RA 2.2uF HDR 1X5 RA 2.2uF
SILK = HALL SILK = ENCODER
'(%8*,17(5)$&(
HDR 2X5
GND
SILK = JTAG
VDD GND GND VDD GND GND

+$//,17(5)$&( (1&2'(5,17(5)$&(

A A

Classification: Public
Drawing Title:
MCSXTE2BK142
Page Title:
S32K142 - Microcontroller
Size Document Number Rev
C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 3 of 6

5 4 3 2 1
 5 4 3 2 1

&RPPXQLFDWLRQ
D
/,1,17(5)$&( VIN
D

For 24V system, DNP J7, LIN disabled; Default disabled.

i For 12V system, Position J7, LIN enabled;
J7
TP10 1 R241 0
D3 2
DNP
Power_EN R33 0 C A INH_LIN DNP D16
VDD HDR1X2 R36 0 A C
PMEG10010ELR
DNP GF1A
R34
i

7
10.0K U2
R37 R239 R240 R241 is backup for PCAN LIN interface

INH

VBAT
R35 0 1 10.0K PCAN tool need the power supply
P3 LIN_RX RXD 2.0K 2.0K
3
R38 0 4 WAKE
P3 LIN_TX TXD TP11
L1 J8
R39 0 LIN1-SLP_N 2 6 1 2 4

GND
P3 LIN_SLP SLP LIN

2
3
R40 D4 2
TJA1021T/20/C 120OHM 1
10.0K PESD1IVN24-A

5
C22
220PF CON PLUG 4
SILK = LIN
VDD GND

1
GND

C C

&$1,17(5)$&(
VIN

R41 TP12
D5
1.0K
VDD A C R42 0 Power_EN
C25 Power_EN P6
C23 GND DNP
2.2uF C24 PMEG10010ELR
10nF 10nF

10
5

3
U3
GND

VIO

VCC

VBAT
TP13
C26 R44
R43 0 1 13 100pF 1.0K
P3 CAN1_TX TXD CANH J9
R45 0 6 11 GND R46 CAN_H 1
P3 CAN_EN EN SPLIT CAN_L 2
120
12 C27 R48 3
R47 0 14 CANL 4700 PF 1.0K 4
P3 CAN_STB STB

2
VIN 8 GND GND CON_1X4
9 ERR TP14
Local Wake Up Disable R49 100K
i Only Support Remote Wake Up
WAKE
INH
7 INH_CAN C28
SILK = CAN
100pF U4
4 PESD2IVN24-T

GND
RXD GND
R50 0
P3 CAN1_RX

3
TJA1043T

2
GND
B B
R51 0
P3 CAN_ERR
GND

3:0,1
VDD

R52
10.0K

TP15
1

R53 J10
R251 0 2 3 R54 0 PWM_CMD 1
P3 PWM_IN 2
1.0K
C

Q9
C30 2N7002 R55 C29 D6 HDR1X2
330pF 10.0K BZX384-C30 SILK = PWM
A DNP DNP 10nF A
A

GND
Classification: Public
Drawing Title:
MCSXTE2BK142
Page Title:
Communication
Size Document Number Rev
C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 4 of 6

5 4 3 2 1
 5 4 3 2 1

D
*'7+5((3+$6()(735('5,9(5 D

DCB_V_POS

Operation with the charge pump is recommended when C31

i minimum system voltage (DCB_V_POS) could be less than 14 V. A
D7
C PUMP_C A
D8
C VPWR 0.1uF
+ C102
47uF
VPWR must exceed this threshold in order for the 50V
charge pump and VDD regulator to startup and drive VPWR to > 8.0 V. BAS316 BAS316 Place 0.1UF cap at each power pin.
Once VPWR exceeds 8.0 V, the circuits continues to operate even C42 C34
C33 0.1uF 2.2uF i Route directly from each device power pin to local cap,
if system voltage (DCB_V_POS) drops below 6.0 V. 1uF then route/via to other caps/resistors.
50V 50V
C35 GND
50V
0.1uF
50V GND GND TP16

16
6
U13 TP19

VSUP
VPWR
[VPWR > (7.5V+2V)]

14 22 GD_VDD C36 C37

PUMP
PUMP [5V0 Typ.] VDD C40 C43 0.1uF 2.2uF
15 4 C38 C39 0.1uF 2.2uF 50V 50V
VLS
VPUMP [15V Typ.] VLS 0.1uF 2.2uF 50V 50V
9 40 VLS_CAP 50V 50V
C41 PGND VLS_CAP GND
1uF GND
TP23 TP24 50V GND
SILK = PC_HS SILK = PC_LS C101 2.2uF 50V
GND 1 PC_BOOT
20 PA_BOOT C44 0.1uF
P3 PWMC_HS_B 21 PA_HS 56 PHC_HSG
C C
P3 PWMC_LS PA_LS PA_HS_G 55 PHC_HSS PHC_HSG P6
PHASE A R57 4.7 PHC
8 PA_HS_S 54 PHC_LSG PHC P6
TP22
PHASEA PA_LS_G 53 PHC_I_POS PHC_LSG P6
TP20 TP21
PA_LS_S PHC_I_POS P6
SILK = PB_HS SILK = PB_LS C100 2.2uF 50V
52 PB_BOOT
23 PB_BOOT C45 0.1uF
P3 PWMB_HS_B 24 PB_HS 51 PHB_HSG
P3 PWMB_LS PB_LS PB_HS_G 50 PHB_HSS PHB_HSG P6
PHASE B R58 4.7 PHB
18 PB_HS_S 49 PHB_LSG PHB P6
PHASEB PB_LS_G 48 PHB_I_POS PHB_LSG P6
TP17 TP18 TP25
PB_LS_S PHB_I_POS P6
SILK = PA_HS SILK = PA_LS C99 2.2uF 50V
47 PA_BOOT
31 PC_BOOT C46 0.1uF
P3 PWMA_HS_B 30 PC_HS 46 PHA_HSG
P3 PWMA_LS PC_LS PC_HS_G PHA_HSS PHA_HSG P6
PHASE C 45 R59 4.7 PHA
19 PC_HS_S 44 PHA_LSG PHA P6
TP26
PHASEC PC_LS_G 43 PHA_I_POS PHA_LSG P6
R62 R61 R60 PC_LS_S PHA_I_POS P6
VDD
10.0K 10.0K 10.0K
VREF/2
DNP DNP DNP
26 R63
C

28 CS
D9 D10 27 SCLK 34 24K
GND GND GND R64
29 SI AMP_P I_AMP_P P6
PMEG2005EH R65 120.0 SOUT
TP27 10.0K SO [5V0] 33
25 AMP_N I_AMP_N P6
PMEG2005EH R66 1.0K INT
A

10 INT [5V0]
P3 GD_CS_B 11 EN1
C47 R67
P3 GD_SCLK EN2 24K
P3 GD_MOSI 12 470PF TP31
TP28
P3 GD_MISO RST [PD: 60kOhm DNP
TP29 Typ.]
TP30 2 32 AMP_OUT R68 120.0 DC BUS Current Sensing: DCBI
P3 GD_INT 3 NC_2 AMP_OUT DCBI P3 i ====================
TP32 5 NC_3
P3 GD_EN 7 NC_5 35 GD_OC_OUT C48 Gain (A) = 24K / 1K = 24
13 NC_7 [5V0] OC_OUT
VDD
82pF Vdcbi = (Idcb * 0.001 *24) + 2.5V
17 NC_13 36 OC_TH_IN Idcb = <-104 .. 104> [amps] Max
B P3 GD_RST_B 41 NC_17 OC_TH B
Vdcbi = <0 .. 5.0> [V]

C
NC_41

GND1

GND2
42 VDD GNDA

VSS
NC_42 D11

EP
GD3000 Pre-Driver accepts both 5.0 V & 3.3 V logic level inputs
i R69 PMEG2005EH

1
and 5.0 V logic level outputs are provided TP33
10.0K

37

38

39

57
MC33GD3000EP

A
2 R70 R71 3.0K
GD_OC P3
10K
SILK = OC_TH
GND C49

3
GND 0.1uF

GND

A A

Classification: Public
Drawing Title:
MCSXTE2BK142
Page Title:
GD3000 - THREE PHASE FET PRE-DRIVER
Size Document Number Rev
C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 5 of 6

5 4 3 2 1
 5 4 3 2 1

   
PMEG10010ELR
D12 VIN
L2 1uH U15
A C 1 2 VIN 14
13 VIN1 CBOOT
3
C106
i VPRE target 7.0V, 300mA
Vfb = (169K/(1.0M+169K))*7.0V = 1.0V VPRE
  i VDDA 5.0V, 20mA   i VDD 5.0V, 200mA
VIN2 0.47uF L5 TP52 TP34
4 1 D13 U16 U17
C52 C53 C103 C104 VPRE VDDA VPRE VDD
VCC SW1 2 R74 A C 1 8 SILK = VDDA 1 8
C51 0 SILK = VDD
1uF 12 SW2 Input Output Input Output
0.1uF 0.1uF 10UF 10UF
6 EN 9 100UH C107 2 7 2 7
R247 R250
7 SYNC FB 8 36PF HSMG-C170 Gnd Gnd3 Gnd Gnd3
1.0M R249 10.0K

PGND1
PGND2
RT PGOOD C115

AGND
GND 11 5 R76 C113 C112 10.0K 3 6 C114 3 6

TAB
SS/TRK BIAS TP35 Gnd1 Gnd2 0.68uF Gnd1 Gnd2 C118
GND C109 C110 C111 1.3K 0.1uF 10UF 10UF C116 C117 C119
4 5 4 5 0.68uF
C105 10UF 10UF 10UF SILK = VPRE 0.1uF 10UF 10UF
VIN 2.2uF R248 ON/OFF N/C ON/OFF N/C
LM46000AQPWPRQ1

17
16
15
10
D D
C108 169K MC33375D MC33375D
4.7uF
GND
R246
133K
GND GND GNDA GND GND
J11
P4 Power_EN
PHA 1_1 1_2 PHA

i Default Setting : EN pin disconnected with

R245 PHB 2_1 2_2 PHB
249K
Power_EN, default enabled.
Option Setting : EN Pin connect to CAN/LIN PHC 3_1 3_2 PHC
INH can achieve low power operation CON TB 3
SILK = MOTOR

3+$6(%5,'*(
GND
R82
24K
R83
24K
R84
24K
  
DCB_V_POS
L4
TP36
1 2 SILK = PHC_Bemf
BAT+ R85
PHC_Bemf P3
0.47uH 120.0

3
R88 U7

BZX84-A5V1
TP39 R86 TP38 R87 TP37 R89 2.2K C58
82pF

NC
2.2 OHM 2.2 OHM 2.2 OHM
A_HG 1 B_HG 1 C_HG 1
P5 PHA_HSG P5 PHB_HSG P5 PHC_HSG

2
Q4 Q2 Q3
R90 33 BUK762R4-60E R91 33 BUK762R4-60E R92 33 BUK762R4-60E

3
R93 C59 R94 C60 R95 C61
100K 1nF 100K 1nF 100K 1nF C64
C62 C63 3300PF GND TP40
R96 3300PF 3300PF SILK = PHB_Bemf
P5 PHA P5 PHB P5 PHC R97
100K
PHB_Bemf P3
120.0
U8

BZX84-A5V1
3
C R101 C
+ C93 R98 + C94 R99 R100 + 2.2K C69
82pF

NC
C66 0.1uF 2.2 OHM C68 0.1uF 2.2 OHM + 2.2 OHM C65 C96
2200uF TP42 1000UF TP43 C70 C95 TP41 1000UF 0.1uF

2
[10VDC - 36VDC] 1000UF 0.1uF
A_LG 1 B_LG 1 C_LG 1
P5 PHA_LSG P5 PHB_LSG P5 PHC_LSG
J12 Q5 Q7 Q6
22 2 2 21 R102 33 BUK762R4-60E R103 33 BUK762R4-60E R104 33 BUK762R4-60E GND

3
R105 C71 C74 R106 C72 C75 R107 C73 C76 TP44
12 1 1 11 100K 1nF 3300PF 100K 1nF 3300PF 100K 1nF 3300PF SILK = PHA_Bemf
R108
PHA_Bemf P3
CON TB 2 P5 PHA_I_POS P5 PHB_I_POS P5 PHC_I_POS 120.0
U9

BZX84-A5V1
3
SILK = DC INPUT R109
2.2K C77

 82pF

NC
R110 R111 R112
3

0.001 3W MAX 0.001 3W MAX 0.001 3W MAX

2
2 C78
D15
ZENER 15V 0.1uF 3W MAX
1

GND
R113
1

4 3 PH_NEG

0.001
BUK762R4-60E PMSM PHASE-C Current Sensing
BAT- Q8 GND
R114 R115
R116

24K
680 C79 470

PHC_I
TP45
47PF 6
- 7 R117
PMSM PHASE-B Current Sensing U10B Current_C P3
PHC_I_POS 5
R118 R119 C80
+ 120.0
R120 24K GND AD8656 C81
47PF R122 VREF/2 82pF
Layout Note: R121
B i ========== 680 470 VDDA
R123 VREF/2 B

Single GND in the Design. High Current GND 24K

680 470 GNDA
path to be separated in the Layout by making void. C82

i Phase Current sensing AOP : 20.867

8
47PF

PHB_I
============================ TP46
V+
2 Max Current (0 - to - Peak) 119.8A
-
   PHB_I_POS 3
U10A
1 R124
Current_B P3
+ 120.0
SILK = GND SILK = GND SILK = GND SILK = GNDA GND V- AD8656 C83
82pF
C84

4
TP47 TP48 TP49 TP53 VDDA
PMSM PHASE-A Current Sensing 47PF
GNDA
R125 R126 C85
R127 VREF/2
R128 R129 GNDA
R130 0.1uF
GND GND GND GNDA VREF/2
24K
680 C86 470
24K
680 470 TP50
PHA_I

47PF 6 GNDA
- 7 R131
U11B Current_A P3
5
PHA_I_POS C87
+ 120.0
GND AD8656 C88
47PF 82pF
R132 R133 VREF/2
R134
VREF/2 PMSM Bus Current Sensing
VDDA GNDA
24K Close to U1, GD3000
VDDA 680 470
R135 1K I_AMP_P
I_AMP_P P5
R137 1K I_AMP_N VDD
I_AMP_N P5
8

VREF/2
R136

3
V+ AD8656 VDDA
24K 2
- R73
A U11A 1 VREF/2 2 10K A
VREF_BIAS 3 TP51 DCB_V_POS R138
RT1
+ 10K
R139
SILK = VREF/2 BusVoltage P3
V- VDDA C50 t
R75 120.0 R77

1
R141 C89 Tem_MOSFET P3 Analog IN P3
4

3
0.1uF 24K R140 RC filter, Close to connector C90
24K 220PF 120.0 82pF 120.0
R78 2.2K U12
NC

C91 C92 Place 0.1UF cap at each power pin. 10.0K R79 C57
i Route directly from each device power pin to local cap, C56
NTC - RT1 should close to
BZX84-A5V1
10.0K Classification: Public
82pF i
1

0.1uF 2.2uF then route/via to other caps/resistors. 0.1uF

GNDA Drawing Title:
the critical heat area, for
GNDA example, near MOSFETs. MCSXTE2BK142
DC BUS Voltage sensing: DCBV GND Page Title:
GNDA GNDA i ============================ GND MOTOR CONTROL - POWER STAGE
5.0V @ 59.55V *(2.2K/(24K+2.2K)) Size Document Number Rev
C SCH-47236 PDF: SPF-47236 A1

Date: Thursday, May 14, 2020 Sheet 6 of 6

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