EE 2213

POWER ELECTRONICS
Field-Effect Transistor (FET)

Md. Khorshed Alom

Dept. of ECE, KUET

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 Field-Effect Transistor (FET)
➢ FET is a three terminal electronic device which uses an electric field to
control the current flow. Mainly used for amplification.
➢ The main current (between source and drain) of the FET is controlled
through the electric field effect caused as a result of voltages supplied
between source and gate. That’s why it is called field effect.
➢ BJT is current-controlled device
where FET is voltage controlled
device.
➢ The FET is a unipolar device
depending solely on either electron
(n-channel) or hole (p-channel)
conduction. Fig. 1: Current-controlled and Voltage-controlled Amplifiers

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 Comparison between the BJT and the FET

BJT
Current-controlled device. i.e. 𝐼𝐶 = 𝑓(𝐼𝐵 )
Bipolar device
Low input impedance for forward biasing.
A much high sensitivity to changes in the
applied signal.
Temperature sensitive
Size bigger compared to FET
FET
Voltage-controlled device. i.e. 𝐼𝐷 = 𝑓(𝑉𝐺𝑆 )
Unipolar device
The most important characteristics of the
FET is its high input impedance.
Low sensitivity for stable gain.
More temperature stable
Size smaller than BJT, useful in integrated-
circuit (IC) chips.

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 Types of Field Effect Transistors
❑ There are two basic Types of Field Effect Transistors.
1. Junction field-effect transistor (JFET)
2. Metal–oxide–semiconductor field-effect transistor (MOSFET)

JFET MOSFET

n-channel p-channel Depletion Enhancement

JFET JFET type type

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 Construction of JFET
➢ A JFET consists of a p-type or n-type silicon bar containing two pn junction
at the sides.
➢ The bar forms the channel. If the bar is of n-type, it is called n-channel JFET
and vice-versa.
➢ Two pn junctions forming diodes are
connected internally and forms a common
terminal called gate. Other terminals are
source and drain. Thus a JFET has 3
terminals.
➢ The gate to source p-n junction of a JFET is
always reverse biased and supply voltage
is given across the drain to source terminal. Fig. 2: Construction of JFET

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 Working Principle of JFET
❑ Case-1: 𝑉𝐺𝑆 = 0 V, 𝑉𝐷𝑆 some positive value
➢ 𝑉𝐷𝑆 is applied across the channel and 𝑉𝐺𝑆 = 0 V means gate and source are shorted.
➢ When 𝑉𝐷𝑆 = 0 V, similar distribution of depletion region.
➢ When 𝑉𝐷𝑆 increases (𝑉𝐷𝑆 > 0 ), the depletion layer becomes wider, causing the
resistance of channel increases.
➢ The depletion region is wider near
the top of both p-type materials.
➢ As 𝑉𝐷𝑆 is increased, 𝐼𝐷 also
increases by Ohm’s law.
➢ When 𝑉𝐷𝑆 approaches a level
referred to as 𝑉𝑃 , the depletion
region will widen, causing a
noticeable reduction in the channel
width. Fig. 3: JFET at 𝑉 = 0 V and 𝑉 > 0
𝐺𝑆 𝐷𝑆

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 Working Principle of JFET
➢ It appears that two depletion regions would touch, a condition referred to as pinch-off
will result.
➢ It suggests the current 𝐼𝐷 drops to 0 A but this is hardly the case. Actually 𝐼𝐷 maintains a
saturation level defined as 𝐼𝐷𝑆𝑆 .
➢ In reality a very small channel still exists, with a current of very high density.
➢ 𝐼𝐷𝑆𝑆 is the maximum drain current for a JFET and is defined by the conditions 𝑉𝐺𝑆 = 0 V
and 𝑉𝐷𝑆 > |𝑉𝑃 |.

Fig. 4: 𝐼𝐷 versus 𝑉𝐷𝑆 for 𝑉𝐺𝑆 = 0 V.

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 Working Principle of JFET
❑ Case-2: 𝑉𝐺𝑆 < 0
➢ The result of applying a negative bias to the gate is to reach the saturation level at
a lower level of 𝑉𝐷𝑆 .
➢ Eventually, when 𝑉𝐺𝑆 = −𝑉𝑃 , 𝐼𝐷 drops to 0 mA and the device has been turned off.
This level of 𝑉𝐺𝑆 is defined as 𝑉𝐺𝑆(𝑜𝑓𝑓) .

Fig. 6: n-Channel JFET characteristics with 𝐼𝐷𝑆𝑆 = 8 mA and 𝑉𝑃 = −4 V.

Fig. 5: Application of a negative voltage to the gate.

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 Some Important Terms of JFET
❑ Shorted-gate drain current (𝐼𝐷𝑆𝑆 ): It is the drain current with source short-
circuited to gate (i.e. 𝑉𝐺𝑆 = 0) and drain voltage equal to pinch off
voltage. It is sometimes called zero-bias current.

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 Some Important Terms of JFET
❑ Pinch off voltage (𝑉𝑃 ): It is the minimum drain-source voltage at which the
drain current becomes constant.
❑ Gate-source cut off voltage (𝑉𝐺𝑆(𝑜𝑓𝑓) ): It is the gate-source voltage where
the channel is completely cut-off and the drain current becomes zero.

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 Transfer Characteristics
➢ The relationship between 𝐼𝐷 and 𝑉𝐺𝑆 is defined by Shockley’s equation.

➢ The transfer characteristics defined by Shockley’s equation are unaffected

by the network in which the device is employed.
➢ Substituting 𝑉𝐺𝑆 = 0 in Shockley’s equation gives 𝐼𝐷 = 𝐼𝐷𝑆𝑆 .
➢ Substituting 𝑉𝐺𝑆 = 𝑉𝑃 gives 𝐼𝐷 = 0 mA.

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 Expression for Drain current
➢ A complex mathematical analysis yields the following expression for drain current.
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆 (𝑂𝑓𝑓)

Where, 𝐼𝐷 = Drain current at given 𝑉𝐺𝑆

𝐼𝐷𝑆𝑆 = Shorted-gate drain current
𝑉𝐺𝑆 = Gate-source voltage
𝑉𝐺𝑆 (𝑂𝑓𝑓) = Gate-source cut off voltage
➢ Pinch off voltage, 𝑉𝑃 = 𝑉𝐺𝑆 (𝑂𝑓𝑓)
➢ Note that 𝑉𝐺𝑆 (𝑂𝑓𝑓) will always have the same magnitude value as 𝑉𝑃 . For example, if
𝑉𝑃 = 6 V then 𝑉𝐺𝑆 (𝑂𝑓𝑓) = −6 V.

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 JFET Symbols

JFET symbols: (a) n-channel; (b) p-channel.

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Mathematical Problem

Self-Study
Example 19.1, 19.3, 19.5

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 JFET Biasing
❑ Biasing is the process of applying potential (DC) across any electronic
equipment in order to make it operate as we require (i.e. in our region
of interest). There are two basic types of JFET biasing.
1) Bias battery: JFET is biased by inserting a bias battery 𝑉𝐺𝐺 in the gate
circuit. This battery ensures that gate is always negative w.r.t. source.
2) Biasing circuit: The biasing circuit uses supply voltage 𝑉𝐷𝐷 to provide
the necessary bias. Two most commonly used methods are:
(a) Self-bias configuration
(b) Voltage-divider biasing

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 JFET Biasing by Bias Battery
➢ The battery voltage – 𝑉𝐺𝐺 ensures that gate-source junction remains reverse
biased. Since there is no gate current, there will be no voltage drop across
𝑅𝐺 (i.e. 𝑉𝑅𝐺 = 𝐼𝐺 𝑅𝐺 = 0 V).
∴ 𝑉𝐺𝑆 = − 𝑉𝐺𝐺
2
𝑉𝐺𝑆
➢ The value of drain current is, 𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − 𝑉
𝐺𝑆 (𝑂𝑓𝑓)

➢ The value of 𝑉𝐷𝑆 can be determined by applying +

Kirchhoff’s voltage law as follows: -
+𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 = 0
or, 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷

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 Self-Bias Configuration
➢ The resistor 𝑅𝑆 is the bias resistor. The d.c. component of drain current flowing
through 𝑅𝑆 produces the desired bias voltage.
Voltage across 𝑅𝑆 , 𝑉𝑆 = 𝐼𝐷 𝑅𝑆
➢ Since gate current is negligibly small, the gate terminal
is at d.c. ground i.e., 𝑉𝐺 = 0.
∴ 𝑉𝐺𝑆 = 𝑉𝐺 − 𝑉𝑆 = −𝐼𝐷 𝑅𝑆
➢ The level of 𝑉𝐷𝑆 can be found by applying Kirchhoff’s
voltage law to the output circuit.
+ 𝑉𝐷𝐷 − 𝑉𝐷 − 𝑉𝐷𝑆 −𝑉𝑆 = 0
or, 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝑉𝑆 − 𝑉𝐷
or, 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝑆 𝑅𝑆 − 𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 ) [As, 𝐼𝑆 = 𝐼𝐷 ]

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 Voltage-Divider Biasing
➢ The resistors 𝑅1 and 𝑅2 form a voltage divider across drain supply 𝑉𝐷𝐷 . The
voltage 𝑉2 (= 𝑉𝐺 ) across 𝑅2 provides the necessary bias.
𝑅2
Here, 𝑉2 = 𝑉𝐺 = 𝑉𝐷𝐷 × 𝑅
1 +𝑅2

Now, 𝑉2 − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0
or, 𝑉𝐺𝑆 = 𝑉2 − 𝐼𝐷 𝑅𝑆
𝑉2 −𝑉𝐺𝑆
or, 𝐼𝐷 = 𝑅𝑆
➢ The circuit is so designed that 𝐼𝐷 𝑅𝑆 is larger than
𝑉2 so that 𝑉𝐺𝑆 is negative.
And 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 )

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Mathematical Problem

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Mathematical Problem

❖ Example 19.12-19.21
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 Depletion-Type MOSFET
❑ Construction of Depletion-type MOSFET:
➢ A slab of p-type material is formed from a silicon base and
is referred to as the substrate. The substrate is internally
connected to the source terminal.
➢ The source and drain terminals are connected through
metallic contacts to n-doped regions linked by an n-channel.
➢ The gate is also connected to a metal contact surface but
remains insulated from the n-channel by a very thin silicon
dioxide (𝑆𝑖𝑂2 ) layer.
➢ There is no direct electrical connection between the gate
terminal and the channel of a MOSFET.
➢ The insulating layer of 𝑆𝑖𝑂2 provides the very desirable high
input impedance.
Fig: n-Channel depletion-type MOSFET.

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 Depletion-Type MOSFET
❖ The insulating layer between the gate and the channel
has resulted in another name for the device: insulated-
gate FET, or IGFET.
❑ Basic Operation and Characteristics
➢ When 𝑉𝐺𝑆 = 0 and a voltage 𝑉𝐷𝐷 is applied
across the drain-to-source terminals, the result is an
attraction of the free electrons of the n-channel for
the positive voltage at the drain.
➢ With 𝑉𝐺𝑆 = 0 , current flows through n-channel
similar to JFET and continues to be labeled 𝐼𝐷𝑆𝑆 .
Fig: n-Channel depletion-type MOSFET with
VGS = 0 V and applied voltage VDD .

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 Depletion-Type MOSFET
❑ Basic Operation and Characteristics
➢ The negative potential at the gate will tend to pressure
electrons toward the p-type substrate and attract holes
from the p-type substrate.
➢ A level of recombination between electrons and holes
will occur that will reduce the number of free electrons
in the n-channel available for conduction.
➢ The more negative the bias, the higher is the rate of
recombination.
➢ The resulting level of drain current is therefore reduced
with increasing negative bias for 𝑉𝐺𝑆 .
Fig: Reduction in free carriers in a channel due
to a negative potential at the gate terminal.

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 Depletion-Type MOSFET
➢ For positive values of 𝑉𝐺𝑆 , the positive gate will draw additional electrons from the p-
type substrate due to the reverse leakage current.
➢ As the gate-to-source voltage continues to increase in the positive direction, the drain
current will increase at a rapid rate.

Fig: Drain and transfer characteristics for an n-channel depletion-type MOSFET.

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 Enhancement-Type MOSFET
➢ The construction of an enhancement-type MOSFET is quite similar to that of
the depletion-type MOSFET, except for the absence of a channel between
the drain and source terminals.

Fig: n-Channel enhancement-type MOSFET

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 Enhancement-Type MOSFET
❑ Basic Operation and Characteristics:
➢ When 𝑉𝐺𝑆 = 0 V, effectively 𝐼𝐷 = 0 A.
➢ The positive potential 𝑉𝐺𝑆 at the gate will pressure the holes to
leave the edge area of the 𝑆𝑖𝑂2 layer and the electrons in the
p-substrate will be attracted to the positive gate and
accumulate in the region near the surface of the 𝑆𝑖𝑂2 layer.
➢ The level of 𝑉𝐺𝑆 that results in the significant increase in drain
current is called the threshold voltage and is given the symbol
𝑉𝑇 .
➢ Since the channel is nonexistent with 𝑉𝐺𝑆 = 0 V and “enhanced”
by the application of a positive gate-to-source voltage, this
type of MOSFET is called an enhancement-type MOSFET. Fig: Channel formation in the n-channel
enhancement-type MOSFET.

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 Enhancement-Type MOSFET
❑ Basic Operation and Characteristics:
➢ For values of 𝑉𝐺𝑆 less than the threshold level, the drain current of an
enhancement-type MOSFET is 0 mA.

Fig: Sketching the transfer characteristics for an n-channel enhancement-type

MOSFET from the drain characteristics.

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 MOSFET Symbols

(a) (b) (c) (d)

(a) n-channel depletion-type MOSFETs and (c) n-channel enhancement-type MOSFETs and
(b) p-channel depletion-type MOSFETs. (d) p-channel enhancement type MOSFETs.

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 References

[1] Robert L. Boylestad, Louis Nashelsky – “Electronic Devices and Circuit

Theory (11th Edition).”
[2] V. K. Mehta, Rohit Mehta− “Principles Of Electronics.”

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