Helwan University - Faculty of Engineering (Helwan)

Electronics and Communications Engineering Department

Electronics
Lec-8 Field Effect Transistors
Presented By:

Azza Mohamed Anis

 Field Effect Transistor (FET)
FET operates with one type of charge carriers (electrons or holes)
(FET is a unipolar device).

FET has three terminals called source (S), drain (D), and gate (G).

In FET, the voltage between two terminals controls the current through
the third terminal (FET is a voltage-controlled device).
 Field Effect Transistor (FET)

Metal Oxide Semiconductor FET Junction FET

(MOSFET) (JFET(

Depletion type Enhancement type p-channel n-channel

p-channel n-channel p-channel n-channel

The two main types of FETs are the metal oxide semiconductor field
effect transistor (MOSFET) and the junction field effect transistor
(JFET).
Advantages of FET over BJT
❑ The major feature of FET is its very high input resistance (because
input circuit is reverse biased).

❑ It has a high thermal stability (because its operation depends on flow

of majority carriers only).

❑ It is simpler to fabricate and occupies very small area.

❑ It can be connected as a resistor.

❑ FETs are less noisy and consume low power than BJTs.
 Advantages of FET over BJT

❑ FETs are the preferred device in low-voltage switching applications

because they are generally faster than BJTs when turned on and off.

❑ FETs are not widely used in amplifiers as BJTs except where very high
input resistances are required.

The main disadvantage of FET is its relatively low gain-bandwidth

product in comparison with that which can be obtained with BJT.
Junction Field Effect Transistor (JFET)

JFET is classified into two categories: n-channel JFET and p-channel

JFET.

n-channel p-channel
JFET JFET
N-Channel JFET
It consists of an n-type semiconductor region (called channel)
connected to a conductive terminals at its upper and lower
ends.

The drain is at the upper end and the source is at

the lower end.
Two p-type regions are diffused in the n-type material,
and both p-type regions are connected to the gate lead.

The p-regions are internally connected together.

n-channel
JFET
JFET Symbols

n-channel p-channel
N-Channel JFET Operation

JFET is always operated with the gate-source pn junction

reverse-biased.

The dc voltage VGG is applied to set the reverse-

bias voltage between the gate and the source.

The dc voltage VDD controls the drain-to-source

voltage (VDS) and the current from drain-to-source (ID).
When the gate-to-source voltage (𝑽𝑮𝑺 ) is zero and the drain-to-source
voltage (𝑽𝑫𝑺 ) is positive.
𝑰𝑫

At a small voltage between the drain Electrons

and the source, a small current will
flow through the channel from the
drain to the source.

𝑰𝑺
The drain current (𝑰𝑫 ) will increase with increasing the drain-to-source
voltage (𝑽𝑫𝑺 ), as shown in the graph between points A and B.

This region is called the ohmic region because 𝑽𝑫𝑺 and 𝑰𝑫 are related by
Ohm’s law.
 𝟎 𝟎

+ ++ +

𝟎 𝟎

As 𝑽𝑫𝑺 increases; the reverse voltage between gate and drain (𝑽𝑮𝑫 )
increases the depletion region and reduces cross-sectional area of
channel.
The value of 𝑽𝑫𝑺 at which the channel is pinched-off is called the
pinch-off voltage (𝑽𝑷 ).
At pinch-off the drain current (𝑰𝑫 ) reaches its maximum value.
The maximum value of drain current is 𝑰𝑫𝑺𝑺 (Drain to Source current
with gate Shorted 𝑽𝑮𝑺 = 𝟎) and is always specified on JFET datasheets.
Channel is pinched-off at point B.
A continued increase in 𝑽𝑫𝑺 above the pinch-off voltage produces an
almost constant drain current 𝑰𝑫𝑺𝑺 .

The curve enters the

constant current region
(from point B to point C).
Breakdown occurs at point C when 𝑰𝑫 begins to increase very rapidly
with any increase in 𝑽𝑫𝑺 .

Breakdown results in damage to

the device, so JFETs are always
operate below breakdown.
𝑽𝑮𝑺 Controls 𝑰𝑫
+𝑽𝑫𝑺
When the reverse voltage (𝑽𝑮𝑺 ) is increased.
The reverse-biasing of gate-to-source
−
junction produces a depletion region
extends into channel.
Thus, cross-sectional area of channel −
+
decreases (𝑨), channel-resistance increases
(𝑹), and drain current (𝑰𝑫 ) decreases.
𝑰𝑫 decreases as the magnitude of 𝑽𝑮𝑺 is increased to larger negative
values because of the narrowing of the channel.

+𝑽𝑫𝑺

+ −
For each increase in 𝑽𝑮𝑺 , JFET reaches pinch-off (maximum current)
at values of 𝑽𝑫𝑺 less than 𝑽𝑷 .
When 𝑽𝑮𝑺 has a large negative value, 𝑰𝑫 is reduced to zero.

The value of 𝑽𝑮𝑺 that

makes 𝑰𝑫 approximately
zero is cutoff voltage,
𝑽𝑮𝑺(𝒐𝒇𝒇) .
The cutoff effect results from the increasing of the depletion region to
a point where it completely closes the channel.
Note, 𝑽𝑮𝑺(𝒐𝒇𝒇) and 𝑽𝑷 are equal in magnitude but opposite in sign.
For example, if 𝑽𝑷 = +𝟓𝑽 then 𝑽𝑮𝑺(𝒐𝒇𝒇) = −𝟓𝑽, as shown in the Figure.
Finally, JFET must be operated for a range of 𝑽𝑮𝑺 between 𝟎𝑽 and
𝑽𝑮𝑺(𝒐𝒇𝒇) . For this range, 𝑰𝑫 will vary from 𝑰𝑫𝑺𝑺 to 𝟎𝑨.
A parabolic relationship between 𝑰𝑫 and 𝑽𝑮𝑺 :

𝟐
𝑽𝑮𝑺
𝑰𝑫 = 𝑰𝑫𝑺𝑺 𝟏 −
𝑽𝑮𝑺(𝒐𝒇𝒇)
JFET Operation Regions (Modes)

Modes Applications
Ohmic Voltage Controlled Resistor
Constant Current Amplifier
Cutoff Open Circuit ≡ Off Switch
Current and Voltage Analysis
The dc current (𝑰𝑫 ) and dc voltages (𝑽𝑮𝑺 & 𝑽𝑫𝑺 ) can be
identified by: 𝑰𝑫

Note, JFET operates with the reverse-biased gate-source

𝑰𝑮 +
junction (𝐼𝐺 ≅ 0).
𝑉𝐷𝑆
-
𝑉𝐺𝑆
∵ 𝐼𝑆 = 𝐼𝐺 + 𝐼𝐷
𝑰𝑺
∴ 𝐼𝑆 = 𝐼𝐷
Apply KVL in the gate-source circuit:

𝑉𝐺𝐺 − 𝐼𝐺 𝑅𝐺 − 𝑉𝐺𝑆 − 𝐼𝑠 𝑅𝑆 = 0 𝑰𝑫

Let 𝐼𝐺 = 0, then the drain current (𝐼𝐷 ) and the 𝑰𝑮 +

gate to source voltage (𝑉𝐺𝑆 ) are calculated by:
𝑉𝐷𝑆
-
𝑉𝐺𝐺 −𝑉𝐺𝑆
𝐼𝑆 =
𝑅𝑆
= 𝐼𝐷 𝑉𝐺𝑆

𝑉𝐺𝑆
2 𝑰𝑺
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)
Apply KVL in the drain-source circuit:

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝑠 𝑅𝑆 = 0 𝑰𝑫

+
The drain to source voltage (𝑉𝐷𝑆 ) is calculated by:
𝑉𝐷𝑆
-
𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 ) = 𝑉𝐷𝑆
𝑰𝑺 = 𝑰𝑫
From 𝑰𝑫 , 𝑽𝑫𝑺 characteristic curves:

𝑉𝐺𝑆(𝑜𝑓𝑓) = −3𝑉 𝑎𝑡 𝐼𝐷 ≅ 0𝑚𝐴

𝐼𝐷𝑆𝑆 = 5𝑚𝐴 𝑎𝑡 𝑉𝐺𝑆 = 0𝑉

Apply KVL in the gate-source circuit: 𝑽𝑫𝑫

− 𝐼𝐺 𝑅𝐺 − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0 𝑰𝑫 𝑹𝑫

Let 𝐼𝐺 = 0: − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0 𝑰𝑮

− 𝑉𝐺𝑆 − 𝐼𝐷 (1𝐾) = 0
𝑉𝐺𝑆
− 𝑉𝐺𝑆 = 𝐼𝐷 (1𝐾) 𝑹𝑮
𝑹𝑺 𝑰𝑺 = 𝑰𝑫
− 𝑉𝐺𝑆
𝐼𝐷 = = −10−3 ∗ 𝑉𝐺𝑆
1𝐾
 2
𝑉𝐺𝑆
∵ 𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)

2
𝑉𝐺𝑆
∴ 𝐼𝐷 = 5𝑚𝐴 1 −
(−3)
2
𝑉𝐺𝑆
𝐼𝐷 = 5𝑚𝐴 1 +
3
2
−3
𝑉𝐺𝑆
𝐼𝐷 = 5 ∗ 10 1+
3
 2
−3
𝑉𝐺𝑆
𝐹𝑟𝑜𝑚 𝐼𝐷 = 5 ∗ 10 1+ 𝑎𝑛𝑑 𝐼𝐷 = −10−3 ∗ 𝑉𝐺𝑆
3

2
𝑉𝐺𝑆
−10−3 ∗ 𝑉𝐺𝑆 = 5 ∗ 10−3 1+
3
2
𝑉𝐺𝑆
−𝑉𝐺𝑆 =5 1+
3
2
𝑉𝐺𝑆 2𝑉𝐺𝑆
−𝑉𝐺𝑆 =5 1+ +
9 3
 2
𝑉𝐺𝑆 2𝑉𝐺𝑆
−𝑉𝐺𝑆 =5 1+ +
9 3

2
5𝑉𝐺𝑆 10𝑉𝐺𝑆
−𝑉𝐺𝑆 =5+ +
9 3

2
5𝑉𝐺𝑆 13𝑉𝐺𝑆
0=5+ +
9 3
2
5𝑉𝐺𝑆 13𝑉𝐺𝑆
+ +5=0
9 3
 5 2 13 −𝑏 ± 𝑏 2 − 4 ∗ 𝑎 ∗ 𝑐
𝑉𝐺𝑆 + 𝑉𝐺𝑆 + 5 = 0 𝑉𝐺𝑆𝟏,𝟐 =
9 3 2∗𝑎

2
−13 13 5
± −4∗ ∗5
3 3 9
𝑉𝐺𝑆𝟏,𝟐 =
5
2∗
9

𝑉𝐺𝑆𝟏 = −1.408𝑉

𝑉𝐺𝑆2 = −6.392𝑉
𝑊ℎ𝑎𝑡 𝑖𝑠 𝑡ℎ𝑒 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑉𝐺𝑆 𝑡ℎ𝑎𝑡 𝑤𝑒 𝑤𝑖𝑙𝑙 𝑢𝑠𝑒?
𝑉𝐺𝑆𝟏 = −1.408𝑉 𝑜𝑟 𝑉𝐺𝑆2 = −6.392𝑉

From the parabolic relationship between 𝑰𝑫 and 𝑽𝑮𝑺 :

𝑆𝑜 𝑤𝑒 𝑤𝑖𝑙𝑙 𝑢𝑠𝑒
𝑽𝑮𝑺(𝒐𝒇𝒇) = −𝟑𝑽
𝑉𝐺𝑆𝟏 = −1.408𝑉 > 𝑉𝐺𝑆(𝑜𝑓𝑓)

𝑽𝑮𝑺𝟐 = −𝟔. 𝟑𝟗𝟐𝑽 𝑽𝑮𝑺𝟏 = −𝟏. 𝟒𝟎𝟖𝑽

𝑉𝐺𝑆 = −1.408𝑉

∵ 𝐼𝐷 = −10−3 ∗ 𝑉𝐺𝑆

∴ 𝐼𝐷 = −10−3 ∗ (−1.408)

𝐼𝐷 = 1.408𝑚𝐴
 Apply KVL in the drain-source circuit: +𝑽𝑫𝑫

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆 = 0 𝑹𝑫
𝑰𝑫
The drain to source voltage (𝑉𝐷𝑆 ) is calculated by:
+

𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝐷 + 𝑅𝑆 ) = 𝑉𝐷𝑆 𝑽𝑫𝑺

-

𝑹𝑮
24 − (1.408𝑚𝐴)(4𝐾 + 1𝐾) = 𝑉𝐷𝑆 𝑹𝑺 𝑰𝑺 = 𝑰𝑫

𝑉𝐷𝑆 = 7.04𝑉
From 𝑰𝑫 , 𝑽𝑫𝑺 characteristic curves:

𝑉𝐺𝑆(𝑜𝑓𝑓) = −3𝑉 𝑎𝑡 𝐼𝐷 ≅ 0𝑚𝐴

𝐼𝐷𝑆𝑆 = 5𝑚𝐴 𝑎𝑡 𝑉𝐺𝑆 = 0𝑉

Apply KVL in the gate-source circuit: 𝑽𝑫𝑫

− 𝐼𝐺 𝑅𝐺 − 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0 𝑰𝑫 𝑹𝑫

Let 𝐼𝐺 = 0:
𝑰𝑮

− 𝑉𝐺𝑆 − 𝐼𝐷 𝑅𝑆 = 0
𝑉𝐺𝑆
− 𝑉𝐺𝑆 − 2.5𝑚𝐴 𝑅𝑆 = 0 𝑹𝑮
𝑹𝑺 𝑰𝑺 = 𝑰𝑫

− 2.5𝑚𝐴 𝑅𝑆 = 𝑉𝐺𝑆
 2
𝑉𝐺𝑆
∵ 𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)
2
𝑉𝐺𝑆
2.5𝑚𝐴 = 5𝑚𝐴 1 −
(−3)
2
2.5 𝑉𝐺𝑆
= 1+
5 3

2.5 𝑉𝐺𝑆
=1+
5 3
 2.5 𝑉𝐺𝑆
=1+
5 3

2.5 𝑉𝐺𝑆
−1=
5 3

2.5
3* − 1 = 𝑉𝐺𝑆
5

𝑉𝐺𝑆 = − 0.8787V
𝑈𝑠𝑒 𝑉𝐺𝑆 = − 0.8787𝑉 𝑎𝑛𝑑 𝑉𝐺𝑆 = − 2.5𝑚𝐴 𝑅𝑆

− 0.8787 = − 2.5 ∗ 10−3 𝑅𝑆

0.8787
−3
= 𝑅𝑆
2.5 ∗ 10

𝑅𝑆 = 0.3515𝐾
Apply KVL in the drain-source circuit: +𝑽𝑫𝑫

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷 𝑅𝑆 = 0 𝑹𝑫
𝑰𝑫

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 + 𝑅𝑆 − 𝑉𝐷𝑆 = 0 +
𝑽𝑫𝑺
30 − (2.5𝑚𝐴) 𝑅𝐷 + 𝑅𝑆 − 17.5 = 0 -

30 − 17.5 = (2.5𝑚𝐴) 𝑅𝐷 + 𝑅𝑆 𝑹𝑮
𝑹𝑺 𝑰𝑺 = 𝑰𝑫
30−17.5
= 𝑅𝐷 + 𝑅𝑆 = 5𝐾
2.5𝑚𝐴
∵ 𝑅𝑆 = 0.3515𝐾 𝑎𝑛𝑑 𝑅𝐷 + 𝑅𝑆 = 5𝐾

∴ 𝑅𝐷 + 0.3515𝐾 = 5𝐾

𝑅𝐷 = 5𝐾 − 0.3515𝐾

𝑅𝐷 = 4.6485K
(a) For the given JFET, 𝑉𝐺𝑆(𝑜𝑓𝑓) = – 4 V and 𝐼𝐷𝑆𝑆 = 12 mA.
Determine the minimum value of 𝑉𝐷𝐷 required to put the device in
the constant-current region of operation.
+
Solution:
𝑽𝑫𝑺
-

Constant-Current Region
From the KVL in the drain-source circuit:

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 = 0
𝑰𝑫
𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆 +
𝑽𝑫𝑺
The minimum value of 𝑉𝐷𝐷 is calculated at
-
the minimum value of 𝑉𝐷𝑆 = 𝑉𝑃 = 4𝑉,

𝑉𝐷𝐷(min) = 𝐼𝐷 𝑅𝐷 + 𝑉𝐷𝑆(min)

𝑉𝐷𝐷(min) = 12𝑚𝐴 560Ω + 4 = 10.72𝑉

(b) If 𝑉𝐷𝐷 is increased to 15 V, what is 𝐼𝐷 and 𝑉𝐷𝑆 ?

Solution:
𝐼𝐷 remains constant at 12 mA.

Constant-Current Region
 From the KVL in the drain-source circuit:

𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝑆 = 0
𝑰𝑫
𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝐷 +
𝑽𝑫𝑺
-
𝑉𝐷𝑆 = 15 − 12𝑚𝐴 560Ω = 8.28𝑉
If a JFET has values of 𝑉𝐺𝑆(𝑜𝑓𝑓) = – 8 V and 𝐼𝐷𝑆𝑆 = 9 mA.
Determine the drain current (𝐼𝐷 ) for 𝑉𝐺𝑆 = 0 V, – 1 V, and – 4 V.

Solution:

For 𝑉𝐺𝑆 = 0𝑉, 𝐼𝐷 = 𝐼𝐷𝑆𝑆 = 9𝑚𝐴

For 𝑉𝐺𝑆 = −1𝑉, 𝐼𝐷 𝑖𝑠 𝑐𝑎𝑙𝑐𝑢𝑙𝑎𝑡𝑒𝑑 𝑏𝑦:

2 2
𝑉𝐺𝑆 (−1)
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − = 9𝑚𝐴 1 − = 6.89𝑚𝐴
𝑉𝐺𝑆(𝑜𝑓𝑓) (−8)
For 𝑉𝐺𝑆 = −4𝑉

2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)

2
(−4)
𝐼𝐷 = 9𝑚𝐴 1 − = 2.25𝑚𝐴
(−8)