A B C D E

1 1

LCFC Confidential
Y540 M/B Schematics Document
2 2

Coffee Lake H-Processor with DDR4 + NV N18E-G1 GPU

2019-03-22
3
REV:2.0 3

4 4

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2018/08/02 Deciphered Date 2018/08/02 Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 1 of 77
A B C D E
 A B C D E

LCFC confidential
File Name:FY515
Board Number:NM-C221
PN:DAZ1DG00101
nVidia N18E-G1
HDMI Conn.
1
Page 44 PCI-Express 16X Gen3 Memory BUS (DDR4 non-ECC) 1

Channel B DDR4-SO-DIMM x1
mDP Conn. GDDR6*6 6GB
Intel CPU Page 12,13

eDP x4 Lane Coffee Lake H 45W 1.2V DDR4 2666 MT/s

Page 43 Page 33~38 UP TO 16G x 1
Memory BUS (DDR4 non-ECC)
BGA-1440 Channel A
DDI x4 Lane eDP Conn
eDP x4 Lane MUX eDP x4 Lane 42mm*28mm DDR4-SO-DIMM x1
FHD : 15" Page 12,13
PS8331B 1.2V DDR4 2666 MT/s
Page 39 Page 57 Page 5~13
sw
UP TO 16G x 1
DMI *4
USB Type-C
PD Controller USB 3.1 1x USB Right
USB Type-C
Conn. RTS5455-GR SUB-Board
Page 42
USB2.0 1x
USB3.1 Port4 USB20 Port3
USB 3.0 1x 5Gbps

Intel PCH USB Left(AOU port x1)

Page 41 HDD Conn. SATA Gen3 USB3.1 2x
2 2
USB3.1 Port1 USB2.0 Port1
Page 46 SATA Port4 USB2.0 2x
PCIe 4x Gen3
Cannon Lake H USB Back port x1
SSD M.2 Conn. USB3.1 Port2 USB2.0 Port2
/Optane Memory
SATA Gen3
Page 45 PCIe Port 9-12 USB2.0 1x
EC IT8176 int. keyboard
FCBGA
LAN Realtek PCIe 1x 26mm*24mm
RJ45 Conn.
RTL8111H-CG
Page 52 PCIe Port14
USB 2.0 1x M.2 Card (WLAN&BT)
PCIe 1x PCIe Port13 USB2.0 Port10
Int. Camera & Mic USB2.0 1x
CNVio
M.2 CRF Module
Page 39 USB2.0 Port6 Page 45

HD Audio
SPI BUS SPI ROM
IIC Page 14~22
16MB
3 Page 18 3

LPC
SPK Conn. Codec
Page 48 ALC3287
Page 48
EC TPM
ITE IT8226-LQFP128 SLB9670VQ2.0 Sub-board
Page 49
Page 50
HP&Mic Combo Conn. USB3.1 x1 DB
Page 48

Touch Pad Battery Thermal Sensor Thermal Sensor CPU FAN

TP button DB
NCT7718W F75303M GPU FAN
Page 50 Page 62 Page 55 Page 55 Page 55

PWR BT DB

KB DB
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Block Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 2 of 77

A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VCCIO
VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
1
VCCSTG 1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
+3VALW
VCCCPUCORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH +1.2V VCCGFXCORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS_AON
+1.8VGS
State BOM Structure Control Table
NVVDD
+1.0VGS
BOM Structure BTO Item BOM Structure BTO Item
@ Not stuff MIRROR@ MIRROR
FBVDDQ 15@ 15'' Stuff N18EG0@N18EG1@ GPU part
17@ 17'' stuff NOMIRROR@ 17'' stuff
7000P@ 7000P stuff NPI@ SPI VCC diode stuff
S0 O O O O O 7502M@ 7502 stuff OPT@ For NV GPU part
8111GUL@ LAN Chip 8111GUL part OPTANE@ Optane memory support part
8111H@ LAN Chip 8111H part RT8816_NS@ RT8816 not stuff
S3 O O O O X AG@ Anti-ghost TPM@ For support TPM sku part
2 AOAC@ AOAC support part UP1666_@ UP1666 stuff 2

BL@ BL UP1666_NS@ UP1666 not stuff

S3
Battery only O O O O X CD@ Cost down part UP9632_@ UP9632 part stuff
CNVI@ CNVi support part USB@ USB2.0 port1 for USB Port
DCI@ DCI X76@ VRAM
Debug@ USB2.0 port 1for Debug
S5 S4/AC Only O O O X X EMC@ EMC part
EMC_8111H@ LAN 8111H EMC Part
S5 S4 EMC_NS@ EMC not stuff
Battery only O X X X X GC6@ GC6
GYSNC@ GSYNC support part
S5 S4 HDMI@ HDMI
AC & Battery X X X X X i5@i7@i9@ CPU Part
don't exist ME@ ME part(connector, hole)
M6GX6@S6GX6@ VRAM part

3 3

USB2.0 Port table USB3.0 Port table SATA Port table PCIE Port table
Port Function Port Function Port Function Port Function
1 Back USB3.0 1 Back USB3.0 0A M.2 SSD Gen3 1:8 NA
2 Left USB3.0 2 Type-C Port 0B NA 9 M.2 SSD/Optane
3 Right USB3.0 3 Left USB3.0 1A NA 10 M.2 SSD/Optane
4 Type-C Port 4 Right USB3.0 1B NA 11 M.2 SSD/Optane
5 NA 5 NA 2 NA 12 M.2 SSD/Optane
6 Camera 6 NA 3 NA 13 WLAN Gen1
7:8 NA 4 HDD Gen3 14 LAN Gen1
9 AG
5 NA 15:24 NA
4 4
10:13 NA
14 BT

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Notes List

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 3 of 77
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 5 4 3 2 1

+3VALW
PD Controller AG Controller
RTS5455 IT8176
2.2K
U4 U22
D D

EC_SMB_CK0
EC_SMB_DA0

+3VALW_R
Change IC
Battery BQ24780SRUYR
2.2K
JBATT1 PU201

EC
EC_SMB_CK1
EC_SMB_DA1

C C
+1.8VS_AON +3VALW_PCH
UE1
IT8226E
2.2K 2.2K
VGA( UV1 ) PCH( UH1 )
+3VS Thermal sensor
VGA_SMB_CK2 SML1CLK Thermal sensor NVDD controller Vcore controller
VGA_SMB_DA2 SML1DATA F75303M NCT7718W NCP81611 MP2979A
+1.8VS_AON +3VS U1 (reserved) U134 PU7501 PU2901
2.2K
Dual MOS Control Dual MOS Control

EC_SMB_CK2
EC_SMB_DA2

B B

SMBUS Control Table

SOURCE VGA BATT IT8226E SODIMM WLAN Thermal PCH TP Charger RGB KB USB-C HiFi Audio Anti-ghost
WiMAX Sensor Module Backlight PD

EC_SMB_CK0 IT8226E
X X X X X X X X X X V X V
EC_SMB_DA0 +3VALW
+5VS +3VALW_AG

EC_SMB_CK1 IT8226E
X V V X X X X X V X X X X
EC_SMB_DA1 +3VALW_R +3VALW_R +3VALW_R +3VALW_R

EC_SMB_CK2 IT8226E V X V X X V V X X X X X X
+3VS
EC_SMB_DA2 +3VS +1.8VS_AON +3VS Reserve +3VALW_PCH

PCH_SMBCLK
PCH
X X X V X X X V X X X X X
PCH_SMBDATA +3VALW_PCH +3VS +3VS
PCH_RGBKB_SCL
X X X X X X X X X X V X X X
PCH_RGBKB_SDA +LDO_3V3
EC_SMB_CK0 IT8226E
+3VALW
X X X X X X X X X X V X X
EC_SMB_DA0 +5VS

A A

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address PCH I2C 2 Bus address
Device Address Device Address
Device Address Device Address
DDR DIMMA 1010 000X b RGB Backlight Need to update
Smart Battery 0X16 Thermal Sensor F75303M 1001_100x b
DDR DIMMB 1010 010X b
Charger 0001 0010 b VGA 0x9E (default)
TP Module Need to update
PCH Need to update
Wlan Reserved
Thermal Sensor NCT7718W 1001100xb

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Blank4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 4 of 77
5 4 3 2 1
 5 4 3 2 1

24 PCIE_CRX_GTX_N[0..15]

24 PCIE_CRX_GTX_P[0..15]

PCIE_CTX_C_GRX_N[0..15] 24

PCIE_CTX_C_GRX_P[0..15] 24
D D

UC1C
PCIE_CRX_GTX_P15 E25 B25 PCIE_CTX_GRX_P15 OPT@ CC32 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P15
PCIE_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PCIE_CTX_GRX_N15 OPT@ CC16 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N15
PEG_RXN_0 PEG_TXN_0
PCIE_CRX_GTX_P14 E24 B24 PCIE_CTX_GRX_P14 OPT@ CC31 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P14
PCIE_CRX_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PCIE_CTX_GRX_N14 OPT@ CC15 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N14
PEG_RXN_1 PEG_TXN_1
PCIE_CRX_GTX_P13 E23 B23 PCIE_CTX_GRX_P13 OPT@ CC30 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P13
PCIE_CRX_GTX_N13 D23 PEG_RXP_2 PEG_TXP_2 A23 PCIE_CTX_GRX_N13 OPT@ CC14 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N13
PEG_RXN_2 PEG_TXN_2
PCIE_CRX_GTX_P12 E22 B22 PCIE_CTX_GRX_P12 OPT@ CC29 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P12
PCIE_CRX_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PCIE_CTX_GRX_N12 OPT@ CC13 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3
PCIE_CRX_GTX_P11 E21 B21 PCIE_CTX_GRX_P11 OPT@ CC28 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P11
PCIE_CRX_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PCIE_CTX_GRX_N11 OPT@ CC12 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N11
PEG_RXN_4 PEG_TXN_4
PCIE_CRX_GTX_P10 E20 B20 PCIE_CTX_GRX_P10 OPT@ CC27 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P10
PCIE_CRX_GTX_N10 F20 PEG_RXP_5 PEG_TXP_5 C20 PCIE_CTX_GRX_N10 OPT@ CC11 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N10
PEG_RXN_5 PEG_TXN_5
PCIE_CRX_GTX_P9 E19 B19 PCIE_CTX_GRX_P9 OPT@ CC26 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P9
PCIE_CRX_GTX_N9 D19 PEG_RXP_6 PEG_TXP_6 A19 PCIE_CTX_GRX_N9 OPT@ CC10 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N9
PEG_RXN_6 PEG_TXN_6
PCIE_CRX_GTX_P8 E18 B18 PCIE_CTX_GRX_P8 OPT@ CC25 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P8
PCIE_CRX_GTX_N8 F18 PEG_RXP_7 PEG_TXP_7 C18 PCIE_CTX_GRX_N8 OPT@ CC9 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N8
C PEG_RXN_7 PEG_TXN_7 C
PCIE_CRX_GTX_P7 D17 A17 PCIE_CTX_GRX_P7 OPT@ CC24 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PCIE_CRX_GTX_P6 F16 C16 PCIE_CTX_GRX_P6 OPT@ CC23 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 E16 PEG_RXP_9 PEG_TXP_9 B16 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N6
PEG_RXN_9 PEG_TXN_9
PCIE_CRX_GTX_P5 D15 A15 PCIE_CTX_GRX_P5 OPT@ CC22 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 E15 PEG_RXP_10 PEG_TXP_10 B15 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N5
PEG_RXN_10 PEG_TXN_10
PCIE_CRX_GTX_P4 F14 C14 PCIE_CTX_GRX_P4 OPT@ CC21 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 E14 PEG_RXP_11 PEG_TXP_11 B14 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N4
PEG_RXN_11 PEG_TXN_11
PCIE_CRX_GTX_P3 D13 A13 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 E13 PEG_RXP_12 PEG_TXP_12 B13 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N3
PEG_RXN_12 PEG_TXN_12
PCIE_CRX_GTX_P2 F12 C12 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 E12 PEG_RXP_13 PEG_TXP_13 B12 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N2
PEG_RXN_13 PEG_TXN_13
PCIE_CRX_GTX_P1 D11 A11 PCIE_CTX_GRX_P1 OPT@ CC18 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 E11 PEG_RXP_14 PEG_TXP_14 B11 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N1
PEG_RXN_14 PEG_TXN_14
PCIE_CRX_GTX_P0 F10 C10 PCIE_CTX_GRX_P0 OPT@ CC17 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0
VCCIO PCIE_CRX_GTX_N0 E10 PEG_RXP_15 PEG_TXP_15 B10 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N0
PEG_RXN_15 PEG_TXN_15

RC1 2 1 24.9_0402_1% PEG_COMP G2

PEG_RCOMP
Note:
Place R_comp inside CPU cavity
Trace width=12 mils ,Spacing=15mil
DMI_CRX_PTX_P0 D8 B8 DMI_CTX_PRX_P0
B
Max length= 400 mils. 19 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 E8 DMI_RXP_0 DMI_TXP_0 A8 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 19 B
19 DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 19
DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1
19 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 F6 DMI_RXP_1 DMI_TXP_1 B6 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 19
19 DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 19
DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2
19 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 E5 DMI_RXP_2 DMI_TXP_2 A5 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 19
19 DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 19
DMI_CRX_PTX_P3 J8 D4 DMI_CTX_PRX_P3
19 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J9 DMI_RXP_3 3 OF 13DMI_TXP_3 B4 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 19
19 DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 19
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (1/7) DMI,PEG

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 5 of 77
5 4 3 2 1
 5 4 3 2 1

UC1E

17
17
PCH_CPU_BCLK
PCH_CPU_BCLK#
RC28
RC29
1
1
2 0_0402_5%
2 0_0402_5%
CPU_BCLK
CPU_BCLK#
B31
A32 BCLKP
BCLKN
CFG_0
CFG_1
BN25
BN27
BN26
CFG0
CFG1 @
CFG2
PAD 1
TC89
CFG STRAPS for CPU
CPU_PCIBCLK CFG_2
VCCST 17 PCH_CPU_PCIBCLK
RC15 1 2 0_0402_5% D35
PCI_BCLKP CFG_3
BN28 CFG3
CFG3 56 Stall reset sequence after PCU PLL lock until de-asserted
RC13 1 2 0_0402_5% CPU_PCIBCLK# C36 BR20 CFG4
17 PCH_CPU_PCIBCLK# PCI_BCLKN CFG_4 BM20 CFG5  1 Default Normal eration
17 PCH_CPU_NSSC_CLK
RC17 1
1
2 0_0402_5%
2 0_0402_5%
CPU_NSSC_CLK
CPU_NSSC_CLK#
E31
D31 CLK24P
CFG_5
CFG_6
BT20
BP20
CFG6
CFG7
* No stall
RC16
17 PCH_CPU_NSSC_CLK# CLK24N CFG_7 BR23 CFG8 @ PAD 1 CFG0
TC77

1
CFG_8
1 CFG_9
BR22 CFG9 @ PAD 1
TC78  0 Stall
C10225 RC66 RC76 V1 0 BT23 CFG10 @ PAD 1
56.2_0402_1% CFG_10 TC79
0.1U_0201_6.3V7-K 100_0402_1% BT22 CFG11 @ PAD 1
CFG_11 BM19 1 TC80
2
@
CFG_12
CFG12 @ PAD
TC81 Reserved configuration lane
BR19 CFG13 @ PAD 1
TC82

2
D CFG_13 BP19 CFG14 @ PAD 1 D
1 2 VR_SVID_ALRT#_R BH31 CFG_14 BT19 1 TC83
RC65 220_0402_5% CFG15 @ PAD
69 SVID_ALERT# VR_SVID_CLK VIDALERT# CFG_15 TC84
69 SVID_CLK
RC3 1 2 0_0402_5%
VR_SVID_DAT
BH32
VIDSCK CFG1 N/A
RC14 1 2 0_0402_5% BH29 BN23 @ PAD 1
69 SVID_DATA H_PROCHOT#_R VIDSOUT CFG_17 TC85
49,69 H_PROCHOT# RC9 1 2 499_0402_1% BR30 BP23 @ PAD 1
PROCHOT# CFG_16 TC86
BP22 @ PAD 1
1 2 1K_0201_5% 1 2 DDR_PG_CTRL BT13 CFG_19 BN22 1 TC87
VCCSTG RC7 CC178 .1U_0402_10V6-K @ PAD
DDR_VTT_CNTL CFG_18 TC88
@ PCI ress Static 1 Lane Numbering Reversal

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BR27 @ PAD 1
BPM#_0 TC27
BT27 @ PAD 1
BPM#_1 BM31 1 TC28
@ PAD

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VCCST_PWRGD H13 BPM#_2 BT30 @ PAD 1
TC29 CFG2
VCCST_PWRGD BPM#_3 TC42

16 H_CPUPWRGD
RC32 1 2 1/20W_22_5%_0201 CPUPWRGOOD_R
BUF_CPU_RST#
BT31
PROCPWRGD
*
RC22 1 2 1/20W_22_5%_0201 BP35 BT28
14 CPU_PLTRST# H_PM_SYNC BM34 RESET# PROC_TDO BL32 PROC_TDO 56
14 H_PM_SYNC H_PM_DOWN_R PM_SYNC PROC_TDI PROC_TDI 56 Reserved configuration lane
RC33 1 2 20_0402_5% BP31 BP28
14 H_PM_DOWN EC_PECI BT34 PM_DOWN PROC_TMS BR28 PROC_TMS 56
14,49 EC_PECI H_THRMTRIP# PECI PROC_TCK PROC_TCK 56
J31
14 H_THRMTRIP# THERMTRIP# BP30 N/A
VCCST RC11 1 2 1K_0402_5% BR33 PROC_TRST# BL30 PROC_TRST# 56 CFG3
SKTOCC# PROC_PREQ# PROC_PREQ# 56
BN1 BP27
PROC_SELECT# PROC_PRDY# PROC_PRDY# 56
RC174 1 @ 2 10K_0402_5% H_CATERR# BM30
CATERR# BT25
CFG_RCOMP eDP enable
AT13

100P_0402_50V8J

100P_0402_50V8J
ZVM#

2
.1U_0402_10V6-K
1 1 1 AW13
MSM#
 1

CC177
Disabled

CC175

CC176
AU13 RC175
AY13 RSVD1 49.9_0402_1%
2 2 2@ RSVD2 CFG4  0 nabled
*

1
5 OF 13 close to CPU

+3VALW
COFFEELAKE-H-CPU_BGA1440 PCI ress Bifurcation
+3VS @
C  00 1 8 PCI ress C
UC1M
CFG[6:5]
2

 01 reserved
RC177 RC178
+1.2V 100K_0402_5% 100K_0402_5% E2
RSVD_TP5 VCCST  10 8 PCI ress
@ 1 PAD @ E3
TC111 IST_TRIG
E1
* 11 1 1 PCI ress
1

D1 RSVD_TP4
1

SM_PG_CTRL RSVD_TP3
SM_PG_CTRL 65

1
RC18 BR1 BK28 P G Training
1K_0402_5% BT2 RSVD_TP1 RSVD11 BJ28 RC57
RSVD_TP2 RSVD10 51_0402_5%
*
1

C BN35 @  1 default P G Train immediately

2

2 QC1 RSVD15
following R S T# deassertion

2
B MMBT3904WH_SOT323-3 J24
RSVD28
H24 CFG7  0 P G Wait for BI S for training
3

BN33 RSVD27
DDR_PG_CTRL BL34 RSVD14 PROC_PREQ#
RSVD13
N29 Reserved configuration lane
R14 RSVD30
VCCSTG
2

AE29 RSVD31
RSVD33
RC179
10K_0402_5%
AA14
AP29 RSVD32 CFG[19:8] N/A
@ delete R short V0 AP14 RSVD5
RSVD4

2
A36
1

VSS_A36 R10455
A37 51_0402_1%
Debug Pin VSS_A37 @
Logic Buffer CPU_TRIGIN H23
22 CPU_TRIGIN

1
PCH_TRIGIN RC4 1 2 30_0402_5% CPU_TRIGOUT J23 PROC_TRIGIN
22 PCH_TRIGIN PROC_TRIGOUT
1 F30
CC174 RSVD24 PROC_TDO
.1U_0402_10V6-K
@ E30
2 RSVD23

B B
B30 BL31
C30 RSVD7 RSVD12 AJ8
RSVD21 RSVD3 G13
RSVD25
G3 VCCIO
J3 RSVD26 C38
RSVD29 RSVD22 C1
RSVD20 BR2
BR35 RSVD17 BP1
BR31 RSVD19 RSVD16 B38
+3VS +3VALW VCCST BH30 RSVD18 RSVD8 B2
RSVD9 RSVD6
13 OF 13
1

COFFEELAKE-H-CPU_BGA1440
RC75 @
2

1
1K_0402_5%
R292 R291 RC139 RC140 RC141 RC142 RC143 RC144
10K_0402_5% 10K_0402_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
2

@ @ @ @ @ @ @
1

2
RC50 1 2 60.4_0402_1% VCCST_PWRGD
CFG3
CFG1 CFG7
CFG6
1

CC179 CFG5
330P_0402_50V8J CFG4
1

Q1 D Q2 D CFG2
2

CPUCORE_ON 2 2 CFG0
49,69 CPUCORE_ON G G
1

1
L2N7002KWT1G_SOT323-3 S 1 S L2N7002KWT1G_SOT323-3 RC185 RC146
3

CC33 1K_0201_5% 1K_0201_5% RC56 RC53 RC54 RC52 RC51 RC55

0.022U_0402_16V7-K @ @ 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5% 1K_0201_5%
@ @ @ @ @
2

2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (2/7) PM, XDP, CLK, CFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 2.0

Date: Friday, March 22, 2019 Sheet 6 of 77

5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63] 12
UC1A
DDRA_DQ0 DDRB_DQ[0..63] 13
AG1 BR6 UC1B
12 DDRA_CLK0 AG2 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_0/DDR0_DQ_0 BT6 DDRA_DQ1 AM9 BT11 DDRB_DQ0
12 DDRA_CLK0# DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_1/DDR0_DQ_1 DDRA_DQ2 13 DDRB_CLK0 DDR1_CKP_0/DDR1_CKP_0 DDR1_DQ_0/DDR0_DQ_16 DDRB_DQ1
AK2 BP3 AN9 BR11
12 DDRA_CLK1 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_2/DDR0_DQ_2 DDRA_DQ3 13 DDRB_CLK0# DDR1_CKN_0/DDR1_CKN_0 DDR1_DQ_1/DDR0_DQ_17 DDRB_DQ2
AK1 BR3 AM7 BT9
12 DDRA_CLK1# AL3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_3/DDR0_DQ_3 BN5 DDRA_DQ4 13 DDRB_CLK1 AM8 DDR1_CKP_1/DDR1_CKP_1 DDR1_DQ_2/DDR0_DQ_18 BR8 DDRB_DQ3
NC/DDR0_CKP_2 DDR0_DQ_4/DDR0_DQ_4 DDRA_DQ5 13 DDRB_CLK1# DDR1_CKN_1/DDR1_CKN_1 DDR1_DQ_3/DDR0_DQ_19 DDRB_DQ4
AK3 BP6 AM11 BP11
AL2 NC/DDR0_CKN_2 DDR0_DQ_5/DDR0_DQ_5 BP2 DDRA_DQ6 AM10 NC/DDR1_CKP_2 DDR1_DQ_4/DDR0_DQ_20 BN11 DDRB_DQ5
AL1 NC/DDR0_CKP_3 DDR0_DQ_6/DDR0_DQ_6 BN3 DDRA_DQ7 AJ10 NC/DDR1_CKN_2 DDR1_DQ_5/DDR0_DQ_21 BP8 DDRB_DQ6
D NC/DDR0_CKN_3 DDR0_DQ_7/DDR0_DQ_7 BL4 DDRA_DQ8 AJ11 NC/DDR1_CKP_3 DDR1_DQ_6/DDR0_DQ_22 BN8 DDRB_DQ7 D
AT1 DDR0_DQ_8/DDR0_DQ_8 BL5 DDRA_DQ9 NC/DDR1_CKN_3 DDR1_DQ_7/DDR0_DQ_23 BL12 DDRB_DQ8
12 DDRA_CKE0 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_9/DDR0_DQ_9 DDRA_DQ10 DDR1_DQ_8/DDR0_DQ_24 DDRB_DQ9
AT2 BL2 AT8 BL11
12 DDRA_CKE1 AT3 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_10/DDR0_DQ_10 BM1 DDRA_DQ11 13 DDRB_CKE0 AT10 DDR1_CKE_0/DDR1_CKE_0 DDR1_DQ_9/DDR0_DQ_25 BL8 DDRB_DQ10
DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_11/DDR0_DQ_11 DDRA_DQ12 13 DDRB_CKE1 DDR1_CKE_1/DDR1_CKE_1 DDR1_DQ_10/DDR0_DQ_26 DDRB_DQ11
AT5 BK4 AT7 BJ8
DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_12/DDR0_DQ_12 BK5 DDRA_DQ13 AT11 DDR1_CKE_2/DDR1_CKE_2 DDR1_DQ_11/DDR0_DQ_27 BJ11 DDRB_DQ12
AD5 DDR0_DQ_13/DDR0_DQ_13 BK1 DDRA_DQ14 DDR1_CKE_3/DDR1_CKE_3 DDR1_DQ_12/DDR0_DQ_28 BJ10 DDRB_DQ13
12 DDRA_CS0# DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_14/DDR0_DQ_14 DDRA_DQ15 DDR1_DQ_13/DDR0_DQ_29 DDRB_DQ14
AE2 BK2 AF11 BL7
12 DDRA_CS1# AD2 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_15/DDR0_DQ_15 BG4 DDRA_DQ16 13 DDRB_CS0# AE7 DDR1_CS#_0/DDR1_CS#_0 DDR1_DQ_14/DDR0_DQ_30 BJ7 DDRB_DQ15
NC/DDR0_CS#_2 DDR0_DQ_16/DDR0_DQ_32 DDRA_DQ17 13 DDRB_CS1# DDR1_CS#_1/DDR1_CS#_1 DDR1_DQ_15/DDR0_DQ_31 DDRB_DQ16
AE5 BG5 AF10 BG11
NC/DDR0_CS#_3 DDR0_DQ_17/DDR0_DQ_33 BF4 DDRA_DQ18 AE10 NC/DDR1_CS#_2 DDR1_DQ_16/DDR0_DQ_48 BG10 DDRB_DQ17
DDRA_ODT0 AD3 DDR0_DQ_18/DDR0_DQ_34 BF5 DDRA_DQ19 NC/DDR1_CS#_3 DDR1_DQ_17/DDR0_DQ_49 BG8 DDRB_DQ18
12 DDRA_ODT0 DDRA_ODT1 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_19/DDR0_DQ_35 DDRA_DQ20 DDRB_ODT0 DDR1_DQ_18/DDR0_DQ_50 DDRB_DQ19
AE4 BG2 AF7 BF8
12 DDRA_ODT1 AE1 NC/DDR0_ODT_1 DDR0_DQ_20/DDR0_DQ_36 BG1 DDRA_DQ21 13 DDRB_ODT0 DDRB_ODT1 AE8 DDR1_ODT_0/DDR1_ODT_0 DDR1_DQ_19/DDR0_DQ_51 BF11 DDRB_DQ20
NC/DDR0_ODT_2 DDR0_DQ_21/DDR0_DQ_37 DDRA_DQ22 13 DDRB_ODT1 NC/DDR1_ODT_1 DDR1_DQ_20/DDR0_DQ_52 DDRB_DQ21
AD4 BF1 AE9 BF10
NC/DDR0_ODT_3 DDR0_DQ_22/DDR0_DQ_38 BF2 DDRA_DQ23 AE11 NC/DDR1_ODT_2 DDR1_DQ_21/DDR0_DQ_53 BG7 DDRB_DQ22
AH5 DDR0_DQ_23/DDR0_DQ_39 BD2 DDRA_DQ24 NC/DDR1_ODT_3 DDR1_DQ_22/DDR0_DQ_54 BF7 DDRB_DQ23
12 DDRA_BA0 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_24/DDR0_DQ_40 DDRA_DQ25 DDR1_DQ_23/DDR0_DQ_55 DDRB_DQ24
AH1 BD1 AH10 BB11
12 DDRA_BA1 AU1 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_25/DDR0_DQ_41 BC4 DDRA_DQ26 13 DDRB_MA16_RAS# AH11 DDR1_CAB_3/DDR1_MA_16 DDR1_DQ_24/DDR0_DQ_56 BC11 DDRB_DQ25
12 DDRA_BG0 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_26/DDR0_DQ_42 DDRA_DQ27 13 DDRB_MA14_WE# DDR1_CAB_2/DDR1_MA_14 DDR1_DQ_25/DDR0_DQ_57 DDRB_DQ26
BC5 AF8 BB8
DDR0_DQ_27/DDR0_DQ_43 DDRA_DQ28 13 DDRB_MA15_CAS# DDR1_CAB_1/DDR1_MA_15 DDR1_DQ_26/DDR0_DQ_58 DDRB_DQ27
AH4 BD5 BC8
12 DDRA_MA16_RAS# AG4 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_28/DDR0_DQ_44 BD4 DDRA_DQ29 AH8 DDR1_DQ_27/DDR0_DQ_59 BC10 DDRB_DQ28
12 DDRA_MA14_WE# DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_29/DDR0_DQ_45 DDRA_DQ30 13 DDRB_BA0 DDR1_CAB_4/DDR1_BA_0 DDR1_DQ_28/DDR0_DQ_60 DDRB_DQ29
AD1 BC1 AH9 BB10
12 DDRA_MA15_CAS# DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_30/DDR0_DQ_46 BC2 DDRA_DQ31 13 DDRB_BA1 AR9 DDR1_CAB_6/DDR1_BA_1 DDR1_DQ_29/DDR0_DQ_61 BC7 DDRB_DQ30
12 DDRA_MA[0..9] DDRA_MA0 DDR0_DQ_31/DDR0_DQ_47 DDRA_DQ32 13 DDRB_BG0 DDR1_CAA_5/DDR1_BG_0 DDR1_DQ_30/DDR0_DQ_62 DDRB_DQ31
AH3 AB1 BB7
DDRA_MA1 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_32/DDR1_DQ_0 DDRA_DQ33 13 DDRB_MA[0..9] DDRB_MA0 DDR1_DQ_31/DDR0_DQ_63 DDRB_DQ32
AP4 AB2 AJ9 AA11
DDRA_MA2 AN4 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_33/DDR1_DQ_1 AA4 DDRA_DQ34 DDRB_MA1 AK6 DDR1_CAB_9/DDR1_MA_0 DDR1_DQ_32/DDR1_DQ_16 AA10 DDRB_DQ33
DDRA_MA3 AP5 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_34/DDR1_DQ_2 AA5 DDRA_DQ35 DDRB_MA2 AK5 DDR1_CAB_8/DDR1_MA_1 DDR1_DQ_33/DDR1_DQ_17 AC11 DDRB_DQ34
DDRA_MA4 AP2 NC/DDR0_MA_3 DDR0_DQ_35/DDR1_DQ_3 AB5 DDRA_DQ36 DDRB_MA3 AL5 DDR1_CAB_5/DDR1_MA_2 DDR1_DQ_34/DDR1_DQ_18 AC10 DDRB_DQ35
DDRA_MA5 AP1 NC/DDR0_MA_4 DDR0_DQ_36/DDR1_DQ_4 AB4 DDRA_DQ37 DDRB_MA4 AL6 NC/DDR1_MA_3 DDR1_DQ_35/DDR1_DQ_19 AA7 DDRB_DQ36
DDRA_MA6 AP3 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_37/DDR1_DQ_5 AA2 DDRA_DQ38 DDRB_MA5 AM6 NC/DDR1_MA_4 DDR1_DQ_36/DDR1_DQ_20 AA8 DDRB_DQ37
DDRA_MA7 AN1 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_38/DDR1_DQ_6 AA1 DDRA_DQ39 DDRB_MA6 AN7 DDR1_CAA_0/DDR1_MA_5 DDR1_DQ_37/DDR1_DQ_21 AC8 DDRB_DQ38
DDRA_MA8 AN3 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_39/DDR1_DQ_7 V5 DDRA_DQ40 DDRB_MA7 AN10 DDR1_CAA_2/DDR1_MA_6 DDR1_DQ_38/DDR1_DQ_22 AC7 DDRB_DQ39
DDRA_MA9 AT4 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_40/DDR1_DQ_8 V2 DDRA_DQ41 DDR1_CAA_4/DDR1_MA_7 DDR1_DQ_39/DDR1_DQ_23
DDRA_MA10_AP AH2 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_41/DDR1_DQ_9 U1 DDRA_DQ42 DDRB_MA8 AN8 W8 DDRB_DQ40
12 DDRA_MA10_AP DDRA_MA11 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_42/DDR1_DQ_10 DDRA_DQ43 DDRB_MA9 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_40/DDR1_DQ_24 DDRB_DQ41
AN2 U2 AR11 W7
12 DDRA_MA11 DDRA_MA12 AU4 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_43/DDR1_DQ_11 V1 DDRA_DQ44 DDRB_MA10_AP AH7 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_41/DDR1_DQ_25 V10 DDRB_DQ42
12 DDRA_MA12 DDRA_MA13 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_44/DDR1_DQ_12 DDRA_DQ45 13 DDRB_MA10_AP DDRB_MA11 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_42/DDR1_DQ_26 DDRB_DQ43
C AE3 V4 AN11 V11 C
12 DDRA_MA13 DDRA_BG1 AU2 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_45/DDR1_DQ_13 U5 DDRA_DQ46 13 DDRB_MA11 DDRB_MA12 AR10 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_43/DDR1_DQ_27 W11 DDRB_DQ44
12 DDRA_BG1 DDRA_ACT# DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_46/DDR1_DQ_14 DDRA_DQ47 13 DDRB_MA12 DDRB_MA13 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_44/DDR1_DQ_28 DDRB_DQ45
AU3 U4 AF9 W10
12 DDRA_ACT# DDR0_CAA_8/DDR0_ACT# DDR0_DQ_47/DDR1_DQ_15 DDRA_DQ48 13 DDRB_MA13 DDRB_BG1 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_45/DDR1_DQ_29 DDRB_DQ46
R2 AR7 V7
DDRA_PARITY AG3 DDR0_DQ_48/DDR1_DQ_32 P5 DDRA_DQ49 13 DDRB_BG1 DDRB_ACT# AT9 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_46/DDR1_DQ_30 V8 DDRB_DQ47
12 DDRA_PARITY DDRA_ALERT# NC/DDR0_PAR DDR0_DQ_49/DDR1_DQ_33 DDRA_DQ50 13 DDRB_ACT# DDR1_CAA_8/DDR1_ACT# DDR1_DQ_47/DDR1_DQ_31 DDRB_DQ48
AU5 R4 R11
12 DDRA_ALERT# NC/DDR0_ALERT# DDR0_DQ_50/DDR1_DQ_34 P4 DDRA_DQ51 DDRB_PARITY AJ7 DDR1_DQ_48/DDR1_DQ_48 P11 DDRB_DQ49
DDR0_DQ_51/DDR1_DQ_35 DDRA_DQ52 13 DDRB_PARITY DDRB_ALERT# NC/DDR1_PAR DDR1_DQ_49/DDR1_DQ_49 DDRB_DQ50
R5 AR8 P7
12 DDRA_DQS#[0..7] DDRA_DQS#0 DDR0_DQ_52/DDR1_DQ_36 DDRA_DQ53 13 DDRB_ALERT# NC/DDR1_ALERT# DDR1_DQ_50/DDR1_DQ_50 DDRB_DQ51
BR5 P2 R8
DDRA_DQS#1 BL3 DDR0_DQSN_0/DDR0_DQSN_0DDR0_DQ_53/DDR1_DQ_37 R1 DDRA_DQ54 DDR1_DQ_51/DDR1_DQ_51 R10 DDRB_DQ52
DDRA_DQS#2 DDR0_DQSN_1/DDR0_DQSN_1DDR0_DQ_54/DDR1_DQ_38 DDRA_DQ55 13 DDRB_DQS#[0..7] DDRB_DQS#0 DDR1_DQ_52/DDR1_DQ_52 DDRB_DQ53
BG3 P1 BN9 P10
DDRA_DQS#3 BD3 DDR0_DQSN_2/DDR0_DQSN_4DDR0_DQ_55/DDR1_DQ_39 M4 DDRA_DQ56 DDRB_DQS#1 BL9 DDR1_DQSN_0/DDR0_DQSN_2DDR1_DQ_53/DDR1_DQ_53 R7 DDRB_DQ54
DDRA_DQS#4 AA3 DDR0_DQSN_3/DDR0_DQSN_5DDR0_DQ_56/DDR1_DQ_40 M1 DDRA_DQ57 DDRB_DQS#2 BG9 DDR1_DQSN_1/DDR0_DQSN_3DDR1_DQ_54/DDR1_DQ_54 P8 DDRB_DQ55
DDRA_DQS#5 U3 DDR0_DQSN_4/DDR1_DQSN_0DDR0_DQ_57/DDR1_DQ_41 L4 DDRA_DQ58 DDRB_DQS#3 BC9 DDR1_DQSN_2/DDR0_DQSN_6DDR1_DQ_55/DDR1_DQ_55 L11 DDRB_DQ56
DDRA_DQS#6 P3 DDR0_DQSN_5/DDR1_DQSN_1DDR0_DQ_58/DDR1_DQ_42 L2 DDRA_DQ59 DDRB_DQS#4 AC9 DDR1_DQSN_3/DDR0_DQSN_7DDR1_DQ_56/DDR1_DQ_56 M11 DDRB_DQ57
DDRA_DQS#7 L3 DDR0_DQSN_6/DDR1_DQSN_4DDR0_DQ_59/DDR1_DQ_43 M5 DDRA_DQ60 DDRB_DQS#5 W9 DDR1_DQSN_4/DDR1_DQSN_2DDR1_DQ_57/DDR1_DQ_57 L7 DDRB_DQ58
DDR0_DQSN_7/DDR1_DQSN_5DDR0_DQ_60/DDR1_DQ_44 M2 DDRA_DQ61 DDRB_DQS#6 R9 DDR1_DQSN_5/DDR1_DQSN_3DDR1_DQ_58/DDR1_DQ_58 M8 DDRB_DQ59
12 DDRA_DQS[0..7] DDRA_DQS0 DDR0_DQ_61/DDR1_DQ_45 DDRA_DQ62 DDRB_DQS#7 DDR1_DQSN_6/DDR1_DQSN_6DDR1_DQ_59/DDR1_DQ_59 DDRB_DQ60
BP5 L5 M9 L10
DDRA_DQS1 BK3 DDR0_DQSP_0/DDR0_DQSP_0DDR0_DQ_62/DDR1_DQ_46 L1 DDRA_DQ63 DDR1_DQSN_7/DDR1_DQSN_7DDR1_DQ_60/DDR1_DQ_60 M10 DDRB_DQ61
DDRA_DQS2 BF3 DDR0_DQSP_1/DDR0_DQSP_1DDR0_DQ_63/DDR1_DQ_47 13 DDRB_DQS[0..7] DDRB_DQS0 BP9 DDR1_DQ_61/DDR1_DQ_61 M7 DDRB_DQ62
DDRA_DQS3 BC3 DDR0_DQSP_2/DDR0_DQSP_4 BA2 DDRB_DQS1 BJ9 DDR1_DQSP_0/DDR0_DQSP_2DDR1_DQ_62/DDR1_DQ_62 L8 DDRB_DQ63
DDRA_DQS4 AB3 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 BA1 DDRB_DQS2 BF9 DDR1_DQSP_1/DDR0_DQSP_3DDR1_DQ_63/DDR1_DQ_63
DDRA_DQS5 V3 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 AY4 DDRB_DQS3 BB9 DDR1_DQSP_2/DDR0_DQSP_6 AW11
DDRA_DQS6 R3 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 AY5 DDRB_DQS4 AA9 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_0 AY11
DDRA_DQS7 M3 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 BA5 DDRB_DQS5 V9 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_1 AY8
DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 BA4 DDRB_DQS6 P9 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_2 AW8
AY3 DDR CHANNEL A NC/DDR0_ECC_5 AY1 DDRB_DQS7 L9 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_3 AY10
BA3 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 AY2 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_4 AW10
1 OF 13
DDR0_DQSN_8/DDR0_DQSN_8 NC/DDR0_ECC_7 AW9 NC/DDR1_ECC_5 AY7
COFFEELAKE-H-CPU_BGA1440 AY9 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_6 AW7
DDR1_DQSN_8/DDR1_DQSN_8 NC/DDR1_ECC_7
@

+V_DDR_REFA_R BN13 G1 SM_RCOMP0

+V_DDR_REF_R BP13 DDR_VREF_CA DDR CHANNEL B DDR_RCOMP_0 H1 SM_RCOMP1
+V_DDR_REFB_R BR13 DDR0_VREF_DQ DDR_RCOMP_1 J2 SM_RCOMP2
2 OF 13
B DDR1_VREF_DQ DDR_RCOMP_2 B

COFFEELAKE-H-CPU_BGA1440
@

RC147 1 @ 2 0_0402_5% +V_DDR_REFA_R

+VREF_CA_DIMMA_R
PAD @ TC109 1 +VREF_DQ_DIMM_R RC36 1 2 0_0402_5% +V_DDR_REF_R
RC37 1 @ 2 0_0402_5% +V_DDR_REFB_R
+VREF_DQ_DIMMB_R
@
CAD Note:
Trace width= 20 mil, Spcing=20 mils
DDR_VR F_CA : Connected to VR F_CA on DIMM CH-A
DDR0_VR F_DQ : NC
DDR1_VR F_DQ : Connected to VR F_CA on DIMM CH-B

DDR4 COMPENSATION SIGNALS

SM_RCOMP0 RC5 1 2 121_0402_1%

SM_RCOMP1 RC6 1 2 75_0402_1%

SM_RCOMP2 RC8 1 2 100_0402_1%

CAD Note:
A
Trace width=12~15 mil, Spcing=20 mils A
Max trace length= 500 mil

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (3/7) DDRVI

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 7 of 77

5 4 3 2 1
 5 4 3 2 1

UC1D

D K36 D29 CPU_EDP_TX0+ D

DDI1_TXP_0 EDP_TXP_0 CPU_EDP_TX0- CPU_EDP_TX0+ 57
K37 E29
DDI1_TXN_0 EDP_TXN_0 CPU_EDP_TX1+ CPU_EDP_TX0- 57
J35 F28
DDI1_TXP_1 EDP_TXP_1 CPU_EDP_TX1- CPU_EDP_TX1+ 57
J34 E28
DDI1_TXN_1 EDP_TXN_1 CPU_EDP_TX2+ CPU_EDP_TX1- 57
H37 A29
DDI1_TXP_2 EDP_TXP_2 CPU_EDP_TX2- CPU_EDP_TX2+ 57
H36 B29
DDI1_TXN_2 EDP_TXN_2 CPU_EDP_TX3+ CPU_EDP_TX2- 57
J37 C28
DDI1_TXP_3 EDP_TXP_3 CPU_EDP_TX3- CPU_EDP_TX3+ 57
J38 B28
DDI1_TXN_3 EDP_TXN_3 CPU_EDP_TX3- 57
D27 C26 CPU_EDP_AUX
DDI1_AUXP EDP_AUXP CPU_EDP_AUX# CPU_EDP_AUX 57
E27 B26
DDI1_AUXN EDP_AUXN CPU_EDP_AUX# 57
H34
H33 DDI2_TXP_0
F37 DDI2_TXN_0 A33 VCCIO
G38 DDI2_TXP_1 EDP_DISP_UTIL
F34 DDI2_TXN_1
F35 DDI2_TXP_2 D37 EDP_COMP 2 1
E37 DDI2_TXN_2 DISP_RCOMP 24.9_0402_1% RC49
DDI2_TXP_3
E36
DDI2_TXN_3 COMPENSATION FOR DDI interface
F26
E26 DDI2_AUXP CAD Note:Trace width=20 mils ,Spacing=25mil,
DDI2_AUXN
Max length=100 mils.
C34
D34 DDI3_TXP_0
B36 DDI3_TXN_0
B34 DDI3_TXP_1
C F33 DDI3_TXN_1 C
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27 PROC_AUDIO_CLK_CPU
PROC_AUDIO_CLK PROC_AUDIO_CLK_CPU 16
A27 G25 PROC_AUDIO_SDO_CPU PROC_AUDIO_SDO_CPU 16
B27 DDI3_AUXP PROC_AUDIO_SDI G29 PROC_AUDIO_SDI_CPU_R RC180 1 2 20_0402_5%
DDI3_AUXN PROC_AUDIO_SDO PROC_AUDIO_SDI_CPU 16
4 of 13
Place near CPU
COFFEELAKE-H-CPU_BGA1440
@

1
RH762
33_0402_5%
@

2
1
CH264
10P_0402_50V8J
2@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (4/7) eDP, DDI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 8 of 77
5 4 3 2 1
 5 4 3 2 1

VCCGFXCORE VCCGFXCORE
VCCCPUCORE VCCCPUCORE VCCCPUCORE
UC1J VCCCPUCORE UC1K
UC1I AT14 BD35
AA13 AH13 K14 W35 AT31 VCCGT1 VCCGT80 BD36
AA31 VCC1 VCC64 AH14 L13 VCC125 VCC188 W36 AT32 VCCGT2 VCCGT81 BE31
AA32 VCC2 VCC65 AH29 L14 VCC126 VCC189 W37 AT33 VCCGT3 VCCGT82 BE32
AA33 VCC3 VCC66 AH30 N13 VCC127 VCC190 W38 AT34 VCCGT4 VCCGT83 BE33
AA34 VCC4 VCC67 AH31 N14 VCC128 VCC191 Y29 AT35 VCCGT5 VCCGT84 BE34
AA35 VCC5 VCC68 AH32 N30 VCC129 VCC192 Y30 AT36 VCCGT6 VCCGT85 BE35
AA36 VCC6 VCC69 AJ14 N31 VCC130 VCC193 Y31 AT37 VCCGT7 VCCGT86 BE36
AA37 VCC7 VCC70 AJ29 N32 VCC131 VCC194 Y32 AT38 VCCGT8 VCCGT87 BE37
AA38 VCC8 VCC71 AJ30 N35 VCC132 VCC195 Y33 AU14 VCCGT9 VCCGT88 BE38
AB29 VCC9 VCC72 AJ31 N36 VCC133 VCC196 Y34 AU29 VCCGT10 VCCGT89 BF13 CRB lace to CPU
AB30 VCC10 VCC73 AJ32 N37 VCC134 VCC197 Y35 AU30 VCCGT11 VCCGT90 BF14
AB31 VCC11 VCC74 AJ33 N38 VCC135 VCC198 Y36 AU31 VCCGT12 VCCGT91 BF29 VCCGFXCORE
AB32
AB35
VCC12
VCC13
VCC75
VCC76
AJ34
AJ35
P13
P14
VCC136
VCC137
VCC199 AU32
AU35
VCCGT13
VCCGT14
VCCGT92
VCCGT93
BF30
BF31
VCCGT_SENSE

1
AB36 VCC14 VCC77 AJ36 P29 VCC138 AU36 VCCGT15 VCCGT94 BF32 RC60
AB37 VCC15 VCC78 AK31 P30 VCC139 AU37 VCCGT16 VCCGT95 BF35 100_0402_1%
AB38 VCC16 VCC79 AK32 P31 VCC140 AU38 VCCGT17 VCCGT96 BF36
AC13 VCC17 VCC80 AK33 P32 VCC141 AV29 VCCGT18 VCCGT97 BF37
D AC14 VCC18 VCC81 AK34 P33 VCC142 AV30 VCCGT19 VCCGT98 BF38 D

2
AC29 VCC19 VCC82 AK35 P34 VCC143 AV31 VCCGT20 VCCGT99 BG29 VCCGT_SENSE_R
VCC20 VCC83 VCC144 VCCGT21 VCCGT100 69 VCCGT_SENSE
AC30 AK36 P35 AV32 BG30
AC31 VCC21 VCC84 AK37 P36 VCC145 AV33 VCCGT22 VCCGT101 BG31 VSSGT_SENSE_R
AC32 VCC22 VCC85 AK38 R13 VCC146 AV34 VCCGT23 VCCGT102 BG32 69 VSSGT_SENSE
VCC23 VCC86 VCC147 VCCGT24 VCCGT103

1
AC33 AL13 R31 AV35 BG33
AC34 VCC24 VCC87 AL29 R32 VCC148 AV36 VCCGT25 VCCGT104 BG34
AC35 VCC25 VCC88 AL30 R33 VCC149 AW14 VCCGT26 VCCGT105 BG35 RC63
AC36 VCC26 VCC89 AL31 R34 VCC150 AW31 VCCGT27 VCCGT106 BG36 100_0402_1%
AD13 VCC27 VCC90 AL32 R35 VCC151 AW32 VCCGT28 VCCGT107 BH33

2
AD14 VCC28 VCC91 AL35 R36 VCC152 AW33 VCCGT29 VCCGT108 BH34
AD31 VCC29 VCC92 AL36 R37 VCC153 AW34 VCCGT30 VCCGT109 BH35 Modify request by PWR 1 /
AD32 VCC30 VCC93 AL37 R38 VCC154 AW35 VCCGT31 VCCGT110 BH36
AD33 VCC31 VCC94 AL38 T29 VCC155 AW36 VCCGT32 VCCGT111 BH37
AD34 VCC32 VCC95 AM13 T30 VCC156 AW37 VCCGT33 VCCGT112 BH38
AD35 VCC33 VCC96 AM14 T31 VCC157 AW38 VCCGT34 VCCGT113 BJ16
AD36 VCC34 VCC97 AM29 T32 VCC158 AY29 VCCGT35 VCCGT114 BJ17
AD37 VCC35 VCC98 AM30 T35 VCC159 AY30 VCCGT36 VCCGT115 BJ19
AD38 VCC36 VCC99 AM31 T36 VCC160 AY31 VCCGT37 VCCGT116 BJ20
AE13 VCC37 VCC100 AM32 T37 VCC161 AY32 VCCGT38 VCCGT117 BJ21
AE14 VCC38 VCC101 AM33 T38 VCC162 AY35 VCCGT39 VCCGT118 BJ23
AE30 VCC39 VCC102 AM34 U29 VCC163 AY36 VCCGT40 VCCGT119 BJ24
AE31 VCC40 VCC103 AM35 U30 VCC164 AY37 VCCGT41 VCCGT120 BJ26
AE32 VCC41 VCC104 AM36 U31 VCC165 AY38 VCCGT42 VCCGT121 BJ27
AE35 VCC42 VCC105 AN13 U32 VCC166 BA13 VCCGT43 VCCGT122 BJ37 CRB lace to CPU
AE36 VCC43 VCC106 AN14 U33 VCC167 BA14 VCCGT44 VCCGT123 BJ38
AE37 VCC44 VCC107 AN31 U34 VCC168 BA29 VCCGT45 VCCGT124 BK16 VCCCPUCORE
AE38 VCC45 VCC108 AN32 U35 VCC169 BA30 VCCGT46 VCCGT125 BK17
AF29
AF30
VCC46
VCC47
VCC48
VCC109
VCC110
VCC111
AN33
AN34
U36
V13
VCC170
VCC171
VCC172
BA31
BA32
VCCGT47
VCCGT48
VCCGT49
VCCGT126
VCCGT127
VCCGT128
BK19
BK20
VCC_SENSE

1
AF31 AN35 V14 BA33 BK21 RC59
AF32 VCC49 VCC112 AN36 V31 VCC173 BA34 VCCGT50 VCCGT129 BK23 100_0402_1%
AF33 VCC50 VCC113 AN37 V32 VCC174 BA35 VCCGT51 VCCGT130 BK24
AF34 VCC51 VCC114 AN38 V33 VCC175 BA36 VCCGT52 VCCGT131 BK26
AF35 VCC52 VCC115 AP13 V34 VCC176 BB13 VCCGT53 VCCGT132 BK27
CAD Note: RC38 SHOULD BE PLACED CLOSE TO CPU

2
AF36 VCC53 VCC116 AP30 V35 VCC177 BB14 VCCGT54 VCCGT133 BL15
AF37 VCC54 VCC117 AP31 V36 VCC178 BB31 VCCGT55 VCCGT134 BL16
AF38 VCC55 VCC118 AP32 V37 VCC179 BB32 VCCGT56 VCCGT135 BL17 VCCCORE_SENSE VCCSENSE_R
VCC56 VCC119 VCC180 VCCGT57 VCCGT136 69 VCCCORE_SENSE
AG14 AP35 V38 BB33 BL23
AG31 VCC57 VCC120 AP36 W13 VCC181 BB34 VCCGT58 VCCGT137 BL24
AG32 VCC58 VCC121 AP37 W14 VCC182 BB35 VCCGT59 VCCGT138 BL25
AG33 VCC59 VCC122 AP38 W29 VCC183 BB36 VCCGT60 VCCGT139 BL26
CAD Note: RC39 SHOULD BE PLACED CLOSE TO CPU
AG34 VCC60 VCC123 K13 W30 VCC184 BB37 VCCGT61 VCCGT140 BL27
AG35 VCC61 VCC124 W31 VCC185 BB38 VCCGT62 VCCGT141 BL28 VSSCORE_SENSE VSSSENSE_R
VCC62 VCC186 VCCGT63 VCCGT142 69 VSSCORE_SENSE
AG36 W32 BC29 BL36
VCC63 VCC187 10 OF 13 BC30 VCCGT64 VCCGT143 BL37

1
COFFEELAKE-H-CPU_BGA1440 BC31 VCCGT65 VCCGT144 BM15
BC32 VCCGT66 VCCGT145 BM16

@
AG37 VCCSENSE_R BC35 VCCGT67 VCCGT146 BM17 RC62
VCC_SENSE AG38 VSSSENSE_R BC36 VCCGT68 VCCGT147 BM36 100_0402_1%
C 9 OF 13 VSS_SENSE BC37 VCCGT69 VCCGT148 BM37 C

2
COFFEELAKE-H-CPU_BGA1440 BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
@

BD14 VCCGT72 VCCGT151 BN17

BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37 Modify request by PWR 1 /
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
BR15 VCCGT160 VCCGT165 BT16
BR16 VCCGT161 VCCGT166 BT17
BR17 VCCGT162 VCCGT167 BT37
VCCGT163 VCCGT168

AH37 VSSGT_SENSE_R
VSSGT_SENSE AH38 VCCGT_SENSE_R
VCCGT_SENSE
11 OF 13
COFFEELAKE-H-CPU_BGA1440

@
VCCGFXCORE
10uF 10pcs CD 2pcs

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1

CC98

CC108

CC107

CC110

CC106

CC105

CC104

CC102

CC103

CC117
@ @
B 2 2 2 2 2 2 2 2 2 2 B

VCCCPUCORE
10uF 21pcs CD 2pcs
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1uF 12pcs CD 2pcs

CC62

CC80

CC79

CC82

CC78

CC77

CC76

CC74

CC75

CC81

CC83

CC91

CC88

CC92

CC89

CC86

CC87

CC84

CC85

CC94

CC93

CD75 CD76
33P_0201_50V8-J 33P_0201_50V8-J
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RF_NS@ 2 RF_NS@

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD@

CD77 CD78
CD@

CH158

CH159

CH160

CH162

CH161

CH164

CH163

CH165

CH167

CH166

CH169

CH168
33P_0402_50V8J
CD@

CD@

CD@

CD@

CD@

CD@

33P_0402_50V8J
@ @ RF_NS@ RF_NS@
2 2 2 2 2 2 2 2 2 2 2 2 2 2
V1 0
Near CPU

Near CPU
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH93

CH94

CH96

CH97

CH98

CH99

CH100

CH101

CH102

CH103

CH104

CH105

CH106

CH107

CH108

CH109

CH111

CH112

CH113

CH114

CH115

CH116

CH117

CH118

CH119

CH120

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@

@
1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CH121

CH124

CH125

CH126

CH128

CH129

CH130

CH131

CH132

CH133

CH134

CH135

CH136

CH137

CH138

CH140

CH139

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@

A A

CD@ CD@ CD@ CD@ CD@ CD@ CD@

1uF 43pcs CD 2pcs

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (5/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 9 of 77
5 4 3 2 1
 5 4 3 2 1

VCCSA

VCCSA +1.2V
10uF 7pcs
UC1L

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
J30 AA6
K29 VCCSA1 VDDQ1 AE12
VCCSA2 VDDQ2 1 1 1 1 1 1 1 1 1
K30 AF5 CD79 CD80
VCCSA3 VDDQ3

CC136

CC141

CC140

CC142

CC139

CC138

CC137
K31 AF6 33P_0402_50V8J 33P_0402_50V8J
K32 VCCSA4 VDDQ4 AG5 RF_NS@ RF_NS@
K33 VCCSA5 VDDQ5 AG9 +1.2V 2 2 2 2 2 2 2 2 2
K34 VCCSA6 VDDQ6 AJ12
K35 VCCSA7 VDDQ7 AL11
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
VCCSA12 VDDQ12 1
D
L37
L38
M29
VCCSA13
VCCSA14
VDDQ13
VDDQ14
AT12
AW6
AY6
CC172
10U_0603_6.3V6M Near CPU D

VCCSA15 VDDQ15 2

1U_0402_6.3V6K
M30 J5 1
M31 VCCSA16 VDDQ16 J6 Close to Y12 Pin
VCCSA17 VDDQ17
1uF 1pcs

CH223
M32 K12
M33 VCCSA18 VDDQ18 K6
M34 VCCSA19 VDDQ19 L12 2
M35 VCCSA20 VDDQ20 L6
M36 VCCSA21 VDDQ21 R6
VCCIO VCCSA22 VDDQ22 T6
VDDQ23 W6
VDDQ24 Y12
AG12 VDDQ25
G15 VCCIO1 +1.2V
G17 VCCIO2
G19 VCCIO3 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13
VCCIO5 VCCPLL_OC2 VCCST
10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 H15 G11 1 1
H16 VCCIO6 VCCPLL_OC3
VCCIO7
CC147

CC148

CC149

CC150

CH252
H17 H30
H19 VCCIO8 VCCST VCCSTG
2 2 2 VCCIO9 2 2

1U_0402_6.3V6K
H20 H29 1
H21 VCCIO10 VCCSTG2
VCCIO11

1U_0402_6.3V6K

1U_0402_6.3V6K

CH242
H26 G30 1 1
H27 VCCIO12 VCCSTG1 VCCST
VCCIO13 2

CH249

CH250
J15 H28
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2 2 2
J19 VCCIO16 @
J20 VCCIO17 M38 VCCSA_SENSE_R
J21 VCCIO18 VCCSA_SENSE M37 VSSSA_SENSE_R V1 0
J26 VCCIO19 VSSSA_SENSE
J27 VCCIO20 H14 VCCIO_SENSE_R
VCCIO21 VCCIO_SENSE J14 VSSIO_SENSE_R
VSSIO_SENSE
12 OF 13
1 1U_0402_6.3V6K 1
VCCIO COFFEELAKE-H-CPU_BGA1440 CH251 CC180
C @ 47U_0805_6.3V6-M C
2 2 @

Follow PDG Rev1.0

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

1 1 1
CC182

CC183

CC184

@ @ @
2 2 2
+1.2V
10uF 11pcs CD 1pcs
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1
CC51

CC52

CC53

CC54

CC55

CC56

CC57

CC58

CC59

CC60
2 2 2 2 2 2 2 2 2 2

CD@
CC63
22U_0603_6.3V6-M

22U_0603_6.3V6-M
CC64
22U_0603_6.3V6-M

CC65
22U_0603_6.3V6-M

CC66

1 1 1 1

2 2 2 2
22uF 4pcs
B B

CRB lace to CPU CRB lace to CPU

VCCSA VCCIO
VCCSA_SENSE VCCIO_SENSE
1

RC151 RC155
100_0402_1% 100_0402_1%

@
2

VCCSA_SENSE_R RC154 1 2 VCCIO_SENSE_R

69 VCCSA_SENSE 68 VCC_IO_SEN
0_0402_5%
VSSSA_SENSE_R RC152 1 2 VSSIO_SENSE_R
69 VSSSA_SENSE 68 VSS_IO_SEN
0_0402_5%
1

RC149 RC153
100_0402_1% 100_0402_1%
2

Modify request by PWR 1 /

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (6/7) PWR, BYPASS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 10 of 77

5 4 3 2 1
 5 4 3 2 1

D D
UC1F UC1G UC1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 VSS_326 VSS_410 F19
A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP14 VSS_327 VSS_411 F2
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP18 VSS_328 VSS_412 F21
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP21 VSS_329 VSS_413 F23
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP24 VSS_330 VSS_414 F25
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP25 VSS_331 VSS_415 F27
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP26 VSS_332 VSS_416 F29
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP29 VSS_333 VSS_417 F3
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR34 VSS_345 VSS_429 G20
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR36 VSS_346 VSS_430 G22
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT14 VSS_349 VSS_433 G26
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT18 VSS_350 VSS_434 G28
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
C C
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C25 VSS_364 VSS_448 J18
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C27 VSS_365 VSS_449 J22
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C29 VSS_366 VSS_450 J25
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C31 VSS_367 VSS_451 J32
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C37 VSS_368 VSS_452 J33
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D16 VSS_375 VSS_459 K2
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D18 VSS_376 VSS_460 K3
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D28 VSS_381 VSS_465 K8
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D3 VSS_382 VSS_466 K9
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
B
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4 B
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80 VSS_161 W34 BJ14 VSS_242 VSS_323 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 6 OF 13 VSS_162 VSS_2437 OF 13 VSS_324 N1 VSS_405 VSS_BT36 BT4
COFFEELAKE-H-CPU_BGA1440 COFFEELAKE-H-CPU_BGA1440 F11 VSS_406 VSS_BT4 C2
F13 VSS_407 VSS_C2 D38
@ @ VSS_4088 OF 13 VSS_D38
COFFEELAKE-H-CPU_BGA1440
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 CPU (6/7) PWR, VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 11 of 77

5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM A
+1.2V+1.2V +1.2V+1.2V
+1.2V
JDDRL1B
+1.2V+1.2V +1.2V+1.2V

1
RD5
JDDRL1A DDRA_MA3 131 132 DDRA_MA2
240_0402_5%
7 DDRA_MA3 DDRA_MA1 A3 A2 DDRA_EVENT# DDRA_MA2 7
133 134
7 DDRA_MA1 135 A1 EVENT_n/NF 136

2
1 2 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ4 VSS_1 VSS_2 DDRA_DQ1 DDRA_EVENT# 7 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t/NF DDRA_CLK1# DDRA_CLK1 7
3 4 139 140
7 DDRA_DQ4 5 DQ5 DQ4 6 DDRA_DQ1 7 7 DDRA_CLK0# 141 CK0_c CK1_c/NF 142 DDRA_CLK1# 7
DDRA_DQ0 7 VSS_3 VSS_4 8 DDRA_DQ5 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
7 DDRA_DQ0 9 DQ1 DQ0 10 DDRA_DQ5 7 7 DDRA_PARITY Parity A0 DDRA_MA0 7
DDRA_DQS#0 11 VSS_5 VSS_6 12
D 7 DDRA_DQS#0 DDRA_DQS0 DQS0_C DM0_n/DBl0_n DDRA_BA1 DDRA_MA10_AP D
13 14 145 146
7 DDRA_DQS0 15 DQS0_t VSS_7 16 DDRA_DQ6 7 DDRA_BA1 147 BA1 A10/AP 148 DDRA_MA10_AP 7
DDRA_DQ7 VSS_8 DQ6 DDRA_DQ6 7 DDRA_CS0# VDD_13 VDD_14 DDRA_BA0
17 18 149 150
7 DDRA_DQ7 19 DQ7 VSS_9 20 DDRA_DQ2 7 DDRA_CS0# DDRA_MA14_WE# 151 CS0_n BA0 152 DDRA_MA16_RAS# DDRA_BA0 7
DDRA_DQ3 VSS_10 DQ2 DDRA_DQ2 7 7 DDRA_MA14_WE# A14/WE_n A16/RAS_n DDRA_MA16_RAS# 7
21 22 153 154
7 DDRA_DQ3 DQ3 VSS_11 DDRA_DQ9 DDRA_ODT0 VDD_15 VDD_16 DDRA_MA15_CAS#
23 24 155 156
DDRA_DQ13 25 VSS_12 DQ12 26 DDRA_DQ9 7 7 DDRA_ODT0 DDRA_CS1# 157 ODT0 A15/CAS_n 158 DDRA_MA13 DDRA_MA15_CAS# 7
7 DDRA_DQ13 DQ13 VSS_13 DDRA_DQ8 7 DDRA_CS1# CS1_n A13 DDRA_MA13 7
27 28 159 160
DDRA_DQ12 29 VSS_14 DQ8 30 DDRA_DQ8 7 DDRA_ODT1 161 VDD_17 VDD_18 162
7 DDRA_DQ12 DQ9 VSS_15 DDRA_DQS#1 7 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMA
31 32 163 164
VSS_16 DQS1_c DDRA_DQS1 DDRA_DQS#1 7 VDD_19 VREFCA DDRA_SA2
33 34 165 166
35 DM1_n/DBl_n DQS1_t 36 DDRA_DQS1 7 167 C1/CS3_n/NC SA2 168

.1U_0402_10V6-K
VSS_17 VSS_18 VSS_53 VSS_54

2.2U_0603_6.3V6K
DDRA_DQ15 37 38 DDRA_DQ10 DDRA_DQ33 169 170 DDRA_DQ36
7 DDRA_DQ15 DQ15 DQ14 DDRA_DQ10 7 7 DDRA_DQ33 DQ37 DQ36 DDRA_DQ36 7 1 1
39 40 171 172
DDRA_DQ14 41 VSS_19 VSS_20 42 DDRA_DQ11 DDRA_DQ37 173 VSS_55 VSS_56 174 DDRA_DQ32
7 DDRA_DQ14 DQ10 DQ11 DDRA_DQ11 7 7 DDRA_DQ37 DQ33 DQ32 DDRA_DQ32 7
43 44 175 176
DDRA_DQ21 45 VSS_21 VSS_22 46 DDRA_DQ16 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
7 DDRA_DQ21 DQ21 DQ20 DDRA_DQ16 7 7 DDRA_DQS#4 DDRA_DQS4 DQS4_c DM4_n/DBl4_n
47 48 179 180

CD2

CD3
DDRA_DQ20 49 VSS_23 VSS_24 50 DDRA_DQ17 7 DDRA_DQS4 181 DQS4_t VSS_59 182 DDRA_DQ35
7 DDRA_DQ20 DQ17 DQ16 DDRA_DQ17 7 DDRA_DQ38 VSS_60 DQ39 DDRA_DQ35 7
51 52 183 184
DDRA_DQS#2 VSS_25 VSS_26 7 DDRA_DQ38 DQ38 VSS_61 DDRA_DQ34
53 54 185 186
7 DDRA_DQS#2 DDRA_DQS2 55 DQS2_c DM2_n/DBl2_n 56 DDRA_DQ39 187 VSS_62 DQ35 188 DDRA_DQ34 7
7 DDRA_DQS2 DQS2_t VSS_27 DDRA_DQ19 7 DDRA_DQ39 DQ34 VSS_63 DDRA_DQ40
57 58 189 190
DDRA_DQ22 59 VSS_28 DQ22 60 DDRA_DQ19 7 DDRA_DQ44 191 VSS_64 DQ45 192 DDRA_DQ40 7
7 DDRA_DQ22 DQ23 VSS_29 DDRA_DQ23 7 DDRA_DQ44 DQ44 VSS_65 DDRA_DQ45
61 62 193 194
DDRA_DQ18 VSS_30 DQ18 DDRA_DQ23 7 DDRA_DQ41 VSS_66 DQ41 DDRA_DQ45 7
63 64 195 196
7 DDRA_DQ18 65 DQ19 VSS_31 66 DDRA_DQ24 7 DDRA_DQ41 197 DQ40 VSS_67 198 DDRA_DQS#5
DDRA_DQ29 VSS_32 DQ28 DDRA_DQ24 7 VSS_68 DQS5_c DDRA_DQS5 DDRA_DQS#5 7
67 68 199 200
7 DDRA_DQ29 69 DQ29 VSS_33 70 DDRA_DQ25 201 DM5_n/DBl5_n DQS5_t 202 DDRA_DQS5 7
DDRA_DQ28 VSS_34 DQ24 DDRA_DQ25 7 DDRA_DQ43 VSS_69 VSS_70 DDRA_DQ47
71 72 203 204
7 DDRA_DQ28 DQ25 VSS_35 DDRA_DQS#3 7 DDRA_DQ43 DQ46 DQ47 DDRA_DQ47 7
73 74 205 206
75 VSS_36 DQS3_c 76 DDRA_DQS3 DDRA_DQS#3 7 DDRA_DQ46 207 VSS_71 VSS_72 208 DDRA_DQ42
DM3_n/DBl3_n DQS3_t DDRA_DQS3 7 7 DDRA_DQ46 DQ42 DQ43 DDRA_DQ42 7
77 78 209 210
DDRA_DQ27 79 VSS_37 VSS_38 80 DDRA_DQ26 DDRA_DQ50 211 VSS_73 VSS_74 212 DDRA_DQ48
7 DDRA_DQ27 DQ30 DQ31 DDRA_DQ26 7 7 DDRA_DQ50 DQ52 DQ53 DDRA_DQ48 7
81 82 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ31 DDRA_DQ52 215 VSS_75 VSS_76 216 DDRA_DQ49
7 DDRA_DQ30 85 DQ26 DQ27 86 DDRA_DQ31 7 7 DDRA_DQ52 217 DQ49 DQ48 218 DDRA_DQ49 7
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220
C C
89 CB5/NC CB4/NC 90 7 DDRA_DQS#6 DDRA_DQS6 221 DQS6_c DM6_n/DBl6_n 222
VSS_43 VSS_44 7 DDRA_DQS6 DQS6_t VSS_79 DDRA_DQ53
91 92 223 224
CB1/NC CB0/NC DDRA_DQ54 VSS_80 DQ54 DDRA_DQ53 7
93 94 225 226
95 VSS_45 VSS_46 96 7 DDRA_DQ54 227 DQS5 VSS_81 228 DDRA_DQ55
DQS8_c DM8_n/DBl_n/NC DDRA_DQ51 VSS_82 DQ50 DDRA_DQ55 7
97 98 229 230
99 DQS8_t VSS_47 100 7 DDRA_DQ51 231 DQ51 VSS_83 232 DDRA_DQ61
VSS_48 CB6/NC DDRA_DQ60 VSS_84 DQ60 DDRA_DQ61 7
101 102 233 234
CB2/NC VSS_49 7 DDRA_DQ60 DQ61 VSS_85 DDRA_DQ57
103 104 235 236
105 VSS_50 CB7/NC 106 DDRA_DQ56 237 VSS_86 DQ57 238 DDRA_DQ57 7
CB3/NC VSS_51 PCH_DRAMRST# 7 DDRA_DQ56 DQ56 VSS_87 DDRA_DQS#7
107 108 239 240
DDRA_CKE0 109 VSS_52 RESET_n 110 DDRA_CKE1 PCH_DRAMRST# 13,16 241 VSS_88 DQS7_c 242 DDRA_DQS7 DDRA_DQS#7 7
7 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 7 DM7_n/DBl7_n DQS7_t DDRA_DQS7 7
111 112 243 244
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# DDRA_DQ62 245 VSS_89 VSS_90 246 DDRA_DQ59
7 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 7 7 DDRA_DQ62 DQ62 DQ63 DDRA_DQ59 7
115 116 247 248
7 DDRA_BG0 BG0 ALERT_n DDRA_ALERT# 7 DDRA_DQ58 VSS_91 VSS_92 DDRA_DQ63
117 118 249 250
DDRA_MA12 119 VDD_3 VDD_4 120 DDRA_MA11 7 DDRA_DQ58 251 DQ58 DQ59 252 DDRA_DQ63 7
7 DDRA_MA12 DDRA_MA9 A12 A11 DDRA_MA7 DDRA_MA11 7 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
7 DDRA_MA9 121 122 1 13,16 SMB_CLK_S3 253 254
A9 A7 DDRA_MA7 7 RD18 1 DDRA_VDDSPD SCL SDA DDRA_SA0 SMB_DATA_S3 13,16
123 124 2 255 256
DDRA_MA8 125 VDD_5 VDD_6 126 DDRA_MA5 +3VS 257 VDDSPD SA0 258
7 DDRA_MA8 CD69 0_0402_5% +0.6VS
DDRA_MA6 A8 A5 DDRA_MA4 DDRA_MA5 7 0.1U_0402_10V7K VPP_1 VTT DDRA_SA1
7 DDRA_MA6 127 128 @ 1 1 259 260
129 A6 A4 130 DDRA_MA4 7 2 VPP_2 SA1
VDD_7 VDD_8 @
CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
Layout Note: 2 2
ARGOS_D4AR0-26005-1P40
Place near DIMM ARGOS_D4AR0-26005-1P40 ME@
ME@

RD20 1 2 0_0402_5%
+2.5V +2.5V

+0.6VS
+3VS +3VS +3VS V1 0

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M
1

1 1 1 1
RD22 RD24 RD26

CD59

CD60
CD57

CD58
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0402_6.3V6M

B 0_0402_5% 0_0402_5% 0_0402_5% B

1 1 1
CD23 @ @ @ 2@ 2@
CD24

CD25

2 2
2

2 2 2 DDRA_SA0 DDRA_SA1 DDRA_SA2

1

RD23 RD25 RD27

@ 0_0402_5% @ 0_0402_5% @ 0_0402_5%
2

Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
SPD Address 0H Layout Note:
Place near DIMM
+1.2V
+VREF_CA_DIMMA_R
Change RD to 0ohm jum
1

+1.2V

RD1
1K_0402_1%
2

220U_B2_6.3VM_R25M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+VREF_CA_DIMMA
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1 2
0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
0.1U_0402_10V7K

RD2 CD7 1 CD8 1 CD9 1 CD10 CD11 CD12 CD13 CD14

CD98 1 CD97 1 CD96 1 CD95 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

.1U_0402_10V6-K

2_0402_5% CD81 CD82

CD15

CD16

CD17

CD18

CD65

CD66

CD67

CD68
+

CD5
33P_0402_50V8J 33P_0402_50V8J
1K_0402_1%

1 1
CD21

CD1 RF_NS@ RF_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

0.022U_0402_16V7-K 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 @ 2 2
2
2

2 2
RD3

A A
1

RD4
24.9_0402_1%
Near JDDRL1
2

For EMC Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DDRVI SO-DIMM A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 12 of 77

5 4 3 2 1
 5 4 3 2 1

DDR4 SO-DIMM B
+1.2V +1.2V +1.2V +1.2V
+1.2V
JDDRH1A
+1.2V+1.2V +1.2V+1.2V

1
RD6
1 2 JDDRH1B
240_0402_5%
DDRB_DQ2 3 VSS_1 VSS_2 4 DDRB_DQ4
7 DDRB_DQ2 5 DQ5 DQ4 6 DDRB_DQ4 7

2
DDRB_DQ5 7 VSS_3 VSS_4 8 DDRB_DQ0 DDRB_MA3 131 132 DDRB_MA2
D 7 DDRB_DQ5 DQ1 DQ0 DDRB_DQ0 7 DDRB_EVENT# 7 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT# DDRB_MA2 7 D
9 10 133 134
DDRB_DQS#0 11 VSS_5 VSS_6 12 7 DDRB_MA1 135 A1 EVENT_n/NF 136
7 DDRB_DQS#0 DDRB_DQS0 DQS0_C DM0_n/DBI0_n DDRB_CLK0 VDD_9 VDD_10 DDRB_CLK1
13 14 137 138
7 DDRB_DQS0 15 DQS0_t VSS_7 16 DDRB_DQ1 7 DDRB_CLK0 DDRB_CLK0# 139 CK0_t CK1_t/NF 140 DDRB_CLK1# DDRB_CLK1 7
DDRB_DQ6 VSS_8 DQ6 DDRB_DQ1 7 7 DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# 7
17 18 141 142
7 DDRB_DQ6 DQ7 VSS_9 DDRB_DQ7 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0
19 20 143 144
DDRB_DQ3 21 VSS_10 DQ2 22 DDRB_DQ7 7 7 DDRB_PARITY Parity A0 DDRB_MA0 7
7 DDRB_DQ3 DQ3 VSS_11 DDRB_DQ8
23 24
DDRB_DQ10 25 VSS_12 DQ12 26 DDRB_DQ8 7 DDRB_BA1 145 146 DDRB_MA10_AP
7 DDRB_DQ10 DQ13 VSS_13 DDRB_DQ9 7 DDRB_BA1 BA1 A10/AP DDRB_MA10_AP 7
27 28 147 148
DDRB_DQ14 VSS_14 DQ8 DDRB_DQ9 7 DDRB_CS0# VDD_13 VDD_14 DDRB_BA0
29 30 149 150
7 DDRB_DQ14 DQ9 VSS_15 DDRB_DQS#1 7 DDRB_CS0# DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 7
31 32 151 152
VSS_16 DQS1_c DDRB_DQS1 DDRB_DQS#1 7 7 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 7
33 34 153 154
35 DM1_n/DBl1_n DQS1_t 36 DDRB_DQS1 7 DDRB_ODT0 155 VDD_15 VDD_16 156 DDRB_MA15_CAS#
DDRB_DQ12 VSS_17 VSS_18 DDRB_DQ11 7 DDRB_ODT0 DDRB_CS1# ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS# 7
37 38 7 DDRB_CS1# 157 158
7 DDRB_DQ12 DQ15 DQ14 DDRB_DQ11 7 CS1_n A13 DDRB_MA13 7
39 40 159 160
DDRB_DQ13 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_ODT1 161 VDD_17 VDD_18 162
7 DDRB_DQ13 DQ10 DQ11 DDRB_DQ15 7 7 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
43 44 163 164
DDRB_DQ22 45 VSS_21 VSS_22 46 DDRB_DQ17 165 VDD_19 VREFCA 166 DDRB_SA2
7 DDRB_DQ22 DQ21 DQ20 DDRB_DQ17 7 C1/CS3_n/NC RFU/SA2
47 48 167 168
DDRB_DQ18 49 VSS_23 VSS_24 50 DDRB_DQ16 DDRB_DQ38 169 VSS_53 VSS_54 170 DDRB_DQ34

.1U_0402_10V6-K
7 DDRB_DQ18 DDRB_DQ16 7 7 DDRB_DQ38 DDRB_DQ34 7

2.2U_0603_6.3V6K
51 DQ17 DQ16 52 171 DQ37 DQ36 172 1
VSS_25 VSS_26 VSS_55 VSS_56 1
DDRB_DQS#2 53 54 DDRB_DQ35 173 174 DDRB_DQ39
7 DDRB_DQS#2 DDRB_DQS2 55 DQS2_c DM2_n/DBl2_n 56 7 DDRB_DQ35 175 DQ33 DQ32 176 DDRB_DQ39 7
7 DDRB_DQS2 DQS2_t VSS_27 DDRB_DQ23 DDRB_DQS#4 VSS_57 VSS_58
57 58 177 178 2
DDRB_DQ20 VSS_28 DQ22 DDRB_DQ23 7 7 DDRB_DQS#4 DDRB_DQS4 DQS4_c DM4_n/DBl4_n 2
59 60 179 180
7 DDRB_DQ20 DQ23 VSS_29 7 DDRB_DQS4 DQS4_t VSS_59

CD31
61 62 DDRB_DQ21 181 182 DDRB_DQ36

CD30
DDRB_DQ19 VSS_30 DQ18 DDRB_DQ21 7 DDRB_DQ33 VSS_60 DQ39 DDRB_DQ36 7
63 64 183 184
7 DDRB_DQ19 65 DQ19 VSS_31 66 DDRB_DQ28 7 DDRB_DQ33 185 DQ38 VSS_61 186 DDRB_DQ37
DDRB_DQ27 VSS_32 DQ28 DDRB_DQ28 7 DDRB_DQ32 VSS_62 DQ35 DDRB_DQ37 7
67 68 187 188
7 DDRB_DQ27 DQ29 VSS_33 DDRB_DQ25 7 DDRB_DQ32 DQ34 VSS_63 DDRB_DQ44
69 70 189 190
DDRB_DQ31 71 VSS_34 DQ24 72 DDRB_DQ25 7 DDRB_DQ40 191 VSS_64 DQ45 192 DDRB_DQ44 7
7 DDRB_DQ31 DQ25 VSS_35 DDRB_DQS#3 7 DDRB_DQ40 DQ44 VSS_65 DDRB_DQ45
73 74 193 194
75 VSS_36 DQS3_c 76 DDRB_DQS3 DDRB_DQS#3 7 DDRB_DQ41 195 VSS_66 DQ41 196 DDRB_DQ45 7
DM3_n/DBl3_n DQS3_t DDRB_DQS3 7 7 DDRB_DQ41 DQ40 VSS_67 DDRB_DQS#5
77 78 197 198
DDRB_DQ30 VSS_37 VSS_38 DDRB_DQ26 VSS_68 DQS5_c DDRB_DQS5 DDRB_DQS#5 7
79 80 199 200
7 DDRB_DQ30 81 DQ30 DQ31 82 DDRB_DQ26 7 201 DM5_n/DBl5_n DQS5_t 202 DDRB_DQS5 7
DDRB_DQ24 83 VSS_39 VSS_40 84 DDRB_DQ29 DDRB_DQ42 203 VSS_69 VSS_70 204 DDRB_DQ47
C C
7 DDRB_DQ24 85 DQ26 DQ27 86 DDRB_DQ29 7 7 DDRB_DQ42 205 DQ46 DQ47 206 DDRB_DQ47 7
87 VSS_41 VSS_42 88 DDRB_DQ46 207 VSS_71 VSS_72 208 DDRB_DQ43
CB5/NC CB4/NC 7 DDRB_DQ46 DQ42 DQ43 DDRB_DQ43 7
89 90 209 210
91 VSS_43 VSS_44 92 DDRB_DQ52 211 VSS_73 VSS_74 212 DDRB_DQ54
CB1/NC CB0/NC 7 DDRB_DQ52 DQ52 DQ53 DDRB_DQ54 7
93 94 213 214
95 VSS_45 VSS_46 96 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ55
DQS8_c DM8_n/DBI_n/NC 7 DDRB_DQ48 DQ49 DQ48 DDRB_DQ55 7
97 98 217 218
99 DQS8_t VSS_47 100 DDRB_DQS#6 219 VSS_77 VSS_78 220
101 VSS_48 CB6/NC 102 7 DDRB_DQS#6 DDRB_DQS6 221 DQS6_c DM6_n/DBl6_n 222
CB2/NC VSS_49 7 DDRB_DQS6 DQS6_t VSS_79 DDRB_DQ53
103 104 223 224
105 VSS_50 CB7/NC 106 DDRB_DQ50 225 VSS_80 DQ54 226 DDRB_DQ53 7
CB3/NC VSS_51 PCH_DRAMRST# 7 DDRB_DQ50 DQ55 VSS_81 DDRB_DQ49
107 108 227 228
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 PCH_DRAMRST# 12,16 DDRB_DQ51 VSS_82 DQ50 DDRB_DQ49 7
109 110 229 230
7 DDRB_CKE0 111 CKE0 CKE1 112 DDRB_CKE1 7 7 DDRB_DQ51 231 DQ51 VSS_83 232 DDRB_DQ59
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# DDRB_DQ57 VSS_84 DQ60 DDRB_DQ59 7
113 114 233 234
7 DDRB_BG1 DDRB_BG0 115 BG1 ACT_n 116 DDRB_ALERT# DDRB_ACT# 7 7 DDRB_DQ57 235 DQ61 VSS_85 236 DDRB_DQ62
7 DDRB_BG0 BG0 ALERT_n DDRB_ALERT# 7 DDRB_DQ61 VSS_86 DQ57 DDRB_DQ62 7
117 118 1 237 238
DDRB_MA12 VDD_3 VDD_4 DDRB_MA11 7 DDRB_DQ61 DQ56 VSS_87 DDRB_DQS#7
119 120 239 240
7 DDRB_MA12 DDRB_MA9 121 A12 A11 122 DDRB_MA7 DDRB_MA11 7 241 VSS_88 DQS7_c 242 DDRB_DQS7 DDRB_DQS#7 7
CD70
7 DDRB_MA9 A9 A7 DDRB_MA7 7 0.1U_0402_10V7K DM7_n/DBl7_n DQS7_t DDRB_DQS7 7
123 124 243 244
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 2 DDRB_DQ56 245 VSS_89 VSS_90 246 DDRB_DQ63
7 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 7 @ 7 DDRB_DQ56 DQ62 DQ63 DDRB_DQ63 7
127 128 247 248
7 DDRB_MA6 A6 A4 DDRB_MA4 7 DDRB_DQ60 VSS_91 VSS_92 DDRB_DQ58
129 130 249 250
VDD_7 VDD_8 7 DDRB_DQ60 251 DQ58 DQ59 252 DDRB_DQ58 7
SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
RD19 1 12,16 2 SMB_CLK_S3 DDRB_VDDSPD 255 SCL SDA 256 DDRB_SA0 SMB_DATA_S3 12,16
+3VS VDDSPD SA0
0_0402_5% 1 1 257 258 +0.6VS
ARGOS_D4AS0-26005-1P40 @ CD53 259 VPP_1 Vtt 260 DDRB_SA1
ME@ 2.2U_0603_6.3V6K CD54 VPP_2 SA1
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
+3VS +3VS +3VS
ARGOS_D4AS0-26005-1P40
ME@
1

RD28 RD33
RD30
0_0402_5% @ 0_0402_5% RD21 1 2 0_0402_5%
B 0_0402_5% +2.5V B
@ @
2

V1 0
DDRB_SA0 DDRB_SA1 DDRB_SA2
1

RD31
RD29 RD32
@ @ 0_0402_5% @ +2.5V
0_0402_5% 0_0402_5%
2

1U_0402_6.3V6K

1U_0402_6.3V6K
10U_0402_6.3V6M

10U_0402_6.3V6M
+VREF_DQ_DIMMB_R +1.2V
1 1 1 1

CD61

CD62
CD63

CD64
Change RD1 to 0ohm jum
SPD Address H

1
2 2@ 2 2@
RD11
Layout Note: 1K_0402_1%
Place near DIMM
1 2 +VREF_CA_DIMMB

2
RD12
+1.2V 2_0402_5%

1
1 1
CD29

.1U_0402_10V6-K
Layout Note: 0.022U_0402_16V7-K

1K_0402_1%
Place near DIMM 2 2

2
1

CD47
RD14

RD13
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

24.9_0402_1%
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CD35 1 CD36 1 CD37 1 CD38 1 CD39 1 CD40 1 CD41 1 CD42 1 1 1 1 1 1 1 1 1 1 1
CD83 CD84
CD43

CD44

CD45

CD46

CD71

CD72

CD73

CD74

2
+0.6VS 33P_0402_50V8J 33P_0402_50V8J
RF_NS@ RF_NS@
A 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 CAD Note: A
Trace width= 20 mil, Spcing=20 mils
1U_0402_6.3V6K

For EMC
1U_0402_6.3V6K

10U_0402_6.3V6M

CD49
1 1 1
Near JDDRH1
CD50

CD51

2 2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DDRVI SO-DIMM B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 13 of 77

5 4 3 2 1
 5 4 3 2 1

D D

+3VS

UH1C
AR2 G36 PCIE_PRX_DTX_N9
CL_CLK PCIE9_RXN PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 45
AT5 F36
CL_DATA PCIE9_RXP PCIE_PTX_DRX_N9 PCIE_PRX_DTX_P9 45
AU4
CL_RST# PCIE9_TXN
C34
PCIE_PTX_DRX_N9 45 NGFF SSD

1
D34 PCIE_PTX_DRX_P9
PCIE9_TXP PCIE_PTX_DRX_P9 45
P48
RH133 V47 GPP_K8 K37 PCIE_PRX_DTX_N10
GPP_K9 PCIE10_RXN PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 45
10K_0201_5% V48 J37
GPP_K10 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 45
W47 C35
PCIE_PTX_DRX_N10 45 NGFF SSD

2
GPP_K11 PCIE10_TXN B35 PCIE_PTX_DRX_P10
V1 0 PCIE10_TXP PCIE_PTX_DRX_P10 45
L47
L46 GPP_K0 F44
EC_SCI# RH95 1 2 0_0201_5% U48 GPP_K1 PCIE15_RXN/SATA2_RXN E45
20,49 EC_SCI# RTS5455_SM_INT GPP_K2 PCIE15_RXP/SATA2_RXP
RH828 1 @ 2 0_0201_5% U47 B40
41,49 RTS5455_SM_INT GPP_K3 PCIE_15_SATA_2_TXN
N48 C40
N47 GPP_K4 PCIE15_TXP/SATA2_TXP
P47 GPP_K5 L41
R46 GPP_K6 PCIE16_RXN/SATA3_RXN M40
GPP_K7 PCIE16_RXP/SATA3_RXP B41
PCIE_PTX_DRX_P11 C36 PCIE16_TXN/SATA3_TXN C41
45 PCIE_PTX_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXP/SATA3_TXP
B36
45 PCIE_PTX_DRX_N11 PCIE_PRX_DTX_P11 PCIE11_TXN/SATA0A_TXN SATA_PRX_DTX_N4
NGFF SSD 45 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11
F39
PCIE11_RXP/SATA0A_RXP PCIE17_RXN/SATA4_RXN
K43
SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 46
G38 K44
45 PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXP/SATA4_RXP SATA_PTX_DRX_N4 SATA_PRX_DTX_P4 46
PCIE17_TXN/SATA4_TXN
A42
SATA_PTX_DRX_P4 SATA_PTX_DRX_N4 46 HDD
C AR42 B42 C
GPP_F10/SATA_SCLOCK PCIE17_TXP/SATA4_TXP SATA_PTX_DRX_P4 46
AR48
AU47 GPP_F11/SATA_SLOAD P41
AU46 GPP_F13/SATA_SDATAOUT0 PCIE18_RXN/SATA5_RXN R40
GPP_F12/SATA_SDATAOUT1 PCIE18_RXP/SATA5_RXP C42
CH15 1 2 0.1u_0201_10V6K PCIE_PTX_DRX_N14 C39 PCIE18_TXN/SATA5_TXN D42
51 PCIE_PTX_C_DRX_N14 PCIE_PTX_DRX_P14 PCIE14_TXN/SATA1B_TXN PCIE18_TXP/SATA5_TXP
CH16 1 2 0.1u_0201_10V6K D39
51 PCIE_PTX_C_DRX_P14 PCIE_PRX_DTX_N14 PCIE14_TXP/SATA1B_TXP SATA_LED#
LAN 51 PCIE_PRX_DTX_N14 PCIE_PRX_DTX_P14
D46
PCIE14_RXN/SATA1B_RXN GPP_E8/SATA_LED#
AK48 RH15 1 2 10K_0201_5% +3VS
C47 AH41
51 PCIE_PRX_DTX_P14 PCIE14_RXP/SATA1B_RXP GPP_E0/SATAXPCIE0/SATAGP0 SSD_DET#
AJ43
PCIE_PTX_DRX_N13 GPP_E1/SATAXPCIE1/SATAGP1 SSD_DET# 45
CH17 1 2 0.1u_0201_10V6K B38 AK47
45 PCIE_PTX_C_DRX_N13 PCIE_PTX_DRX_P13 PCIE13_TXN/SATA0B_TXN GPP_E2/SATAXPCIE2/SATAGP2
CH18 1 2 0.1u_0201_10V6K C38 AN47
45 PCIE_PTX_C_DRX_P13 PCIE_PRX_DTX_N13 PCIE13_TXP/SATA0B_TXP GPP_F0/SATAXPCIE3/SATAGP_3
WLAN 45 PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13
C45
PCIE13_RXN/SATA0B_RXN GPP_F1/SATAXPCIE4/SATAGP4
AM46
C46 AM43
45 PCIE_PRX_DTX_P13 PCIE13_RXP/SATA0B_RXP GPP_F2/SATAXPCIE5/SATAGP5 AM47
PCIE_SATA_PTX_DRX_P12 E37 GPP_F3/SATAXPCIE6/SATAGP6 AM48
45 PCIE_SATA_PTX_DRX_P12 PCIE_SATA_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F4/SATAXPCIE7/SATAGP7
D38
45 PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PRX_DTX_P12 PCIE12_TXN/SATA1A_TXN
NGFF SSD 45 PCIE_SATA_PRX_DTX_P12 PCIE_SATA_PRX_DTX_N12
J41
PCIE12_RXP/SATA_1A_RXP GPP_F21/EDP_BKLTCTL
AU48
PCH_EDP_PWM 57
H42 AV46
45 PCIE_SATA_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN GPP_F20/EDP_BKLTEN PCH_EDP_ENBKL 57
B44 AV44
PCIE20_TXP/SATA7_TXP GPP_F19/EDP_VDDEN PCH_EDP_ENVDD 57
A44
R37 PCIE20_TXN/SATA7_TXN AD3 THRMTRIP#_PCH RH34 1 2 620_0402_5%
PCIE20_RXP/SATA7_RXP THRMTRIP# PCH_PECI H_THRMTRIP# 6
R35 AF2 RH35 1 2 13_0402_5%
PCIE20_RXN/SATA7_RXN PECI H_PM_SYNC_R EC_PECI 6,49
D43 AF3 RH13 1 2 30_0402_1%
PCIE19_TXP/SATA6_TXP PM_SYNC CPU_PLTRST# H_PM_SYNC 6
C44 AG5
PCIE19_TXN/SATA6_TXN PLTRST_CPU# H_PM_DOWN CPU_PLTRST# 6
N42 AE2
PCIE19_RXP/SATA6_RXP PM_DOWN H_PM_DOWN 6
M44
PCIE19_RXN/SATA6_RXN 3 OF 13

1
CANNONLAKE-H-PCH_FCBGA874 1 1
B B

.1U_0402_10V6-K
CH280

.1U_0402_10V6-K
CH281
@
@ RH836
10K_0201_5%
@2 @2

2
@
PCH_EDP_PWM R10713 1 2 100K_0201_5%

@
PCH_EDP_ENBKL R10714 1 2 100K_0201_5%

@
PCH_EDP_ENVDD R10715 1 2 100K_0201_5%
A A

modify by grace 1 /

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (1/9) PCIe/SATA/GPPFG
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A3
Y540 2.0

Date: Friday, March 22, 2019 Sheet 14 of 77

5 4 3 2 1
 5 4 3 2 1

NEED close to PCH

EMC_NS@ 33P_0201_50V8-J 2 1 CH296 LPC_AD3

EMC_NS@ 33P_0201_50V8-J 2 1 CH293 LPC_AD2

EMC_NS@ 33P_0201_50V8-J 2 1 CH294 LPC_AD1

EMC_NS@ 33P_0201_50V8-J 2 1 CH295 LPC_AD0 +3VS

HuiH request Reserved Cap 11/12

D HM370 only have 4(#1-#4) USB3.1 GEN2 port D

1
10K_0201_5%

10K_0201_5%
UH1F

RH104

RH113
USB30_TX_N1 F9 BB39 LPC_AD0_R RH128 1 @ 2 0_0201_5%
48 USB30_TX_N1 USB30_TX_P1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 LPC_AD1_R LPC_AD0 49
F7 AW37 RH130 1 @ 2 0_0201_5%
Back USB (3.0) 48 USB30_TX_P1 USB30_RX_N1 D11 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 AV37 LPC_AD2_R RH131 1 @ 2 0_0201_5%
LPC_AD1 49
48 USB30_RX_N1 USB30_RX_P1 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 LPC_AD3_R LPC_AD2 49
C11 BA38 RH132 1 @ 2 0_0201_5%
48 USB30_RX_P1 LPC_AD3 49

2
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3
TYPE-C_USB3_TX_N2 C3 V1 0
40 TYPE-C_USB3_TX_N2 TYPE-C_USB3_TX_P2 USB31_2_TXN LPC_FRAME#
D4 BE38
TYPE-C USB (3.0) 40 TYPE-C_USB3_TX_P2 TYPE-C_USB3_RX_N2 B9 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# AW35 SERIRQ
LPC_FRAME# 49
40 TYPE-C_USB3_RX_N2 TYPE-C_USB3_RX_P2 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# SERIRQ 49
C9 BA36 TPM_SPI_IRQ#
40 TYPE-C_USB3_RX_P2 USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 KBRST#
GPP_A0/RCIN#/ESPI_ALERT1# KBRST# 49
C17 BF38
C16 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET#
G14 USB31_6_TXP For LPC_CLK
F14 USB31_6_RXN R：0Ω to Ω
USB31_6_RXP BB36 CLK_PCI_EC_R RH84 1 2 22_0402_5% CLK_PCI_EC
GPP_A9/CLKOUT_LPC0/ESPI_CLK BB34 CLK_PCI_EC 49
C15
B15 USB31_5_TXN GPP_A10/CLKOUT_LPC1
J13 USB31_5_TXP T48 PCH_SMI# RH821 1 @ 2 0_0201_5%
USB31_5_RXN GPP_K19/SMI# EC_SMI# 49
K13 T47 1
USB31_5_RXP GPP_K18/NMI# RH129 1 @ 2 10K_0201_5% +3VS
USB30_TX_P3 G12 AH40 CH265
47 USB30_TX_P3 USB30_TX_N3 USB31_3_TXP GPP_E6/SATA_DEVSLP2 33P_0402_50V8J
F11 AH35 DEVSLP1
LEFT USB (3.0) 47 USB30_TX_N3 USB30_RX_P3 C10 USB31_3_TXN GPP_E5/SATA_DEVSLP1 AL48
DEVSLP1 45 NGFF SSD 2 EMC@
47 USB30_RX_P3 USB31_3_RXP GPP_E4/SATA_DEVSLP0
MB(AOU) 47 USB30_RX_N3
USB30_RX_N3 B10
USB31_3_RXN GPP_F9/SATA_DEVSLP7
AP47 change D VSLP to SATA Port1 by Bing 0 1
AN37 H：Slee Mode
USB30_TX_P4 C14 GPP_F8/SATA_DEVSLP6 AN46 L：Active Mode V0
50 USB30_TX_P4 USB30_TX_N4 USB31_4_TXP GPP_F7/SATA_DEVSLP5
B14 AR47
C
Right USB (3.0) 50 USB30_TX_N4 USB30_RX_P4 J15 USB31_4_TXN 6 OF 13 GPP_F6/SATA_DEVSLP4 AP48
C

50 USB30_RX_P4 USB31_4_RXP GPP_F5/SATA_DEVSLP3

DB 50 USB30_RX_N4
USB30_RX_N4 K16
USB31_4_RXN

CANNONLAKE-H-PCH_FCBGA874
@

+3VS

DDPB_DATA RH834 1 @ 2 2.2K_0201_5%

B B
DDPC_DATA RH33 1 @ 2 2.2K_0201_5%
UH1E
RH23 1 @ 2 0_0201_5% AT6 AL13 DDPB_CLK PAD 1 @
41 TYPE-C_DP_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I5/DDPB_CTRLCLK DDPB_DATA IT37 DDPD_DATA
RH26 1 @ 2 0_0201_5% AN10 AR8 RH835 1 @ 2 2.2K_0201_5%
44 HDMI_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I6/DDPB_CTRLDATA DDPC_CLK
RH27 1 @ 2 0_0201_5% AP9 AN13 PAD 1 @
43 DP_HPD CNVI_EN# GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I7/DDPC_CTRLCLK DDPC_DATA IT28
AL15 AL10
45 CNVI_EN# GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I8/DDPC_CTRLDATA DDPD_CLK
AL9 PAD 1 @
GPP_I9/DDPD_CTRLCLK DDPD_DATA IT36
AR3
GPP_I10/DDPD_CTRLDATA AN40
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK
AP41
PCH_EDP_HPD AN6 GPP_F14/EXT_PWR_GATE#/PS_ON#
57 PCH_EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4 M45 DDPB_CTRLDATA
GPP_K23/IMGCLKOUT1 L48
GPP_K22/IMGCLKOUT0 The signal has a weak internal pull-down.
1

T45 H Port B is detected.

R10712 GPP_K21 T46
100K_0201_5%
5 OF 13
GPP_K20
GPP_H23/TIME_SYNC0
AJ47 * L Port B is not detected.
@
CANNONLAKE-H-PCH_FCBGA874 DDPC_CTRLDATA
2

Modify by grace 1 / @ The signal has a weak internal pull-down.

H Port C is detected.
* L Port C is not detected. (Default)
DDPD_CTRLDATA
The signal has a weak internal pull-down.
H Port D is detected.
A
* L Port D is not detected. (Default)
A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (2/9) USB3/GPPAEFGHI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 15 of 77
5 4 3 2 1
 5 4 3 2 1

+3VALW_PCH
HDA_SDO This signal has a weak internal pull-down.
* 0 = Enable security measures defined in the Flash Descriptor.
1 = Disable Flash Descriptor Security (override). This

1
strap should only be asserted high using external pull- RH25
up in manufacturing/debug environments ONLY. 1K_0201_5%
@

2
V1 0 +1.2V
RH9 1 2 0_0201_5%
49 ME_FLASH
@ UH1D
RH805 1 2 33_0402_5% HDA_BIT_CLK BD11 BF36
54 PCH_HDA_BIT_CLK HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

1
PCH_HDA_SDIN0 BE11 AV32 PM_CLKRUN#
D 54 PCH_HDA_SDIN0 HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN# D
RH806 1 2 33_0402_5% BF12 RH756
54 PCH_HDA_SDOUT HDA_SYNC HDA_SDO/I2S0_TXD
RH804 1 2 33_0402_5% BG13 BF41 470_0201_5%
54 PCH_HDA_SYNC HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
PLAC N AR PCH 1 HDA_RST# BE10 BD42
@ PAD

2
TH39 BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# PM_SLP_WLAN# 45
BE12 HDA_SDI1/I2S1_RXD BB46
BD12 I2S1_TXD/SNDW2_DATA DRAM_RESET# BE32 PCH_DRAMRST# 12,13
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
PLAC N AR PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH754 1 2 30_0402_5% PROC_AUDIO_SDO_PCH AM2 GPP_B0/GSPI0_CS1# R47
8 PROC_AUDIO_SDO_CPU HDACPU_SDO GPP_K17/ADR_COMPLETE
AN3 AP29
8 PROC_AUDIO_SDI_CPU 1 2 30_0402_5% PROC_AUDIO_CLK_PCH AM3 HDACPU_SDI GPP_B11/I2S_MCLK AU3 SYS_PWROK_R
RH755 RH193 1 @ 2 0_0201_5%
8 PROC_AUDIO_CLK_CPU HDACPU_SCLK SYS_PWROK SYS_PWROK 49
@
AV18 BB47 WAKE# RH69 1 2 0_0201_5%
AW18 GPP_D8/I2S2_SCLK WAKE# BE40 SLP_A# 1 PCIE_WAKE# 45,49
CNVI_MODEM_CLKREQ GPP_D7/I2S2_RXD GPD6/SLP_A# SLP_LAN# TH30 PAD @
BA17 BF40 1
CNVI_RF_RESET# BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 SLP_S0 1 TH31 PAD @
GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# PM_SLP_S3#_R TH32 PAD @
BF15 BF42 RH70 1 @ 2 0_0201_5%
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# BE42 PM_SLP_S4#_R PM_SLP_S3# 49
RH71 1 @ 2 0_0201_5%
AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42 PM_SLP_S5#_R 1 PM_SLP_S4# 49
GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# TH33 PAD @
AW15 V1 0
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45 SUSCLK
PCH_RTCRST# GPD8/SUSCLK SUSCLK 45
BE47 BF44 BATLOW#
49 PCH_RTCRST# PCH_SRTCRST# BD46 RTCRST# GPD0/BATLOW# BE35 SUSACK#_R
SRTCRST# GPP_A15/SUSACK# BC37 SUSWARN#_R RH745 1 @ 2 0_0201_5%
RH12 1 @ 2 0_0201_5% PCH_PWROK_R AY42 GPP_A13/SUSWARN#/SUSPWRDNACK
49 PCH_PWROK PCH_RSMRST#_R PCH_PWROK
RH14 1 @ 2 0_0201_5% BA47
49,56 EC_RSMRST# RSMRST# PCH_LAN_WAKE#
BG44 V1 0
RH239 1 @ 2 0_0201_5% PCH_DPWROK_R AW41 GPD2/LAN_WAKE# BG42 PCH_AC_PRESENT_R RH76 1 @ 2 0_0201_5%
SMB_ALERT# BE25 DSW_PWROK GPD1/ACPRESENT BD39 SLP_SUS# 1 AC_PRESENT 49
@
PCH_SMBCLK GPP_C2/SMBALERT# SLP_SUS# PM_PWRBTN#_R TH34 PAD @
BE26 BE46 RH75 1 2 0_0201_5%
PCH_SMBDATA BF26 GPP_C0/SMBCLK GPD3/PWRBTN# AU2 SYS_RESET# PBTN_OUT# 49,56
V1 0 SMB0_ALERT# GPP_C1/SMBDATA SYS_RESET# SYS_RESET# 56
BF24 AW29
BF25 GPP_C5/SML0ALERT# GPP_B14/SPKR AE3 PCH_BEEP 54
SML0CLK
BE24 GPP_C3/SML0CLK CPUPWRGD H_CPUPWRGD 6
SML0DATA
SMB1_ALERT# BD33 GPP_C4/SML0DATA AL3
49,55 SMB1_ALERT# BF27 GPP_B23/SML1ALERT#/PCHHOT# ITP_PMODE AH4 ITP_PMODE 56
SML1CLK
GPP_C6/SML1CLK PCH_JTAGX JTAGX 56
SML1DATA BE27 AJ4
GPP_C7/SML1DATA PCH_JTAG_TMS AH3 PCH_TMS 56
+3VALW_PCH PCH_JTAG_TDO AH2 PCH_TDO 56
PCH_JTAG_TDI PCH_TDI 56
AJ3
1 2 10K_0201_5% SUSWARN#_R 4 OF 13 PCH_JTAG_TCK PCH_TCK 56
RH56 @
CANNONLAKE-H-PCH_FCBGA874
@

+3VALW

RH17 1 2 10K_0201_5% PM_PWRBTN#_R

PCH_AC_PRESENT_R
CMOS
C RH58 1 2 10K_0201_5% C
RH60 1 2 10K_0201_5% BATLOW#
RH80 1 2 4.7K_0201_5% WAKE#
RH747 1 2 10K_0201_5% PCH_LAN_WAKE#
1

1
VCCRTC CH4 @ @ @ DV13
+3VS 1U_0402_6.3V6K JME1 RC284 1 2 0_0201_5% 1 2 EC_RSMRST#
64,66 ALW_PWRGD
SHORT PADS

2
RH3 1 2 20K_0402_5% 2 PCH_SRTCRST# RB751V-40_SOD323-2
RH67 1 2 10K_0201_5% SYS_RESET#
RH65 1 2 8.2K_0201_5% PM_CLKRUN# V0
RH4 1 2 20K_0402_5% PCH_RTCRST#
1 @

1
1 CH5 JCMOS1
CH1 1U_0402_6.3V6K SHORT PADS
1U_0402_6.3V6K

2
2
2@

RH18 1 2 100K_0201_5% SYS_PWROK_R

RH54 1 2 10K_0201_5% PCH_PWROK_R
RH59 1 2 100K_0201_5% PCH_RSMRST#_R
PCH_DPWROK_R
RSMRST# sequence control circuit
RH61 1 2 100K_0201_5%
@

+3VALW_PCH AS EMC request

close to PCH
HDA_SDOUT
RH28 1 @ 2 1K_0201_5% PCH_BEEP PCH_PWROK_R SYS_PWROK_R PCH_DPWROK_R PCH_HDA_SDIN0
+3VALW_PCH
ST
Ph
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Bh
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4

RPH3 @
TT
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1 1 1 1 1

CH83 EMC_NS@

.1U_0402_10V6-K

CH84 EMC_NS@

.1U_0402_10V6-K

CH85 EMC_NS@

.1U_0402_10V6-K

CH283
2.2P_0402_50V8-C

CH284
2.2P_0402_50V8-C
2 3 SML0DATA
* 〃



 

 g


S

h




k


c

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〃
c



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,
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h
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2.2K_0404_4P2R_5%




f
c
h-


hk

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
w





A
c6
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

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2 2 2 2 2
f
h

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g
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c
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C
H


6
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
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f
h
)

EMC_NS@

EMC_NS@
H
c
y
h

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g

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h
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w
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4
-(
BA
,
A
k7
,
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RH765 1 2 2.2K_0201_5% SMB_ALERT# RH768 1 @ 2 2.2K_0201_5%

FA
W
)







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
w



c

z

6





RH766 1 @ 2 2.2K_0201_5% SMB0_ALERT# RH769 1 @ 2 2.2K_0201_5%

8




c
h
F
T
T


S


B


k




f


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RH767 1 @ 2 2.2K_0201_5% SMB1_ALERT# RH770 1 @ 2 2.2K_0201_5%

(
h



h

g

I
C
)

Strap
GPP_C2 /SMBALERT#
This signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security DIMM1, DIMM2, WLAN, TP RPH8 +3VS GPU, EC, Thermal Sensor
1 4
(TLS) cipher suite (with confidentiality). Must be +3VS +3VALW_PCH

2
B RPH4 RPH7 2 3 B

G
2

pulled up to support Intel AMT with TLS. 1 4 2N7002KDWH 1 4

G

+3VALW_PCH Vth= min 1V, max 2.5V +3VS

2 3 2 3 2.2K_0404_4P2R_5%
ESD 2KV
GPP_C5 /SML0ALERT#
This signal has a weak internal pull-down. 2.2K_0404_4P2R_5% 2.2K_0404_4P2R_5% SML1CLK 6 1 EC_SMB_CK2

S
PCH_SMBCLK SMB_CLK_S3 EC_SMB_CK2 29,49,55
6 1

D
0 = LPC is selected (for EC). (Default) 65 PCH_SMBCLK
S

SMB_CLK_S3 12,13

5
QH2A L2N7002KDW1T1G_SOT363-6
D

1 = eSPI is selected (for EC).

G
5

QH1A L2N7002KDW1T1G_SOT363-6
G

GPP_B23 /SML1ALERT# /PCHHOT#

0 = Disable Intel DCI-OOB (Default) SML1DATA 3 4 EC_SMB_DA2

S
1 = Enable Intel DCI-OOB PCH_SMBDATA 3 4 SMB_DATA_S3 EC_SMB_DA2 29,49,55

D
65 PCH_SMBDATA
S

Note:When used as PCHHOT# and strap low, a 150K SMB_DATA_S3 12,13

QH2B L2N7002KDW1T1G_SOT363-6
D

pull-up is needed to ensure it does not override the QH1B L2N7002KDW1T1G_SOT363-6

internal pull-down strap sampling.
+3VS

RH849 1 @ 2 150K_0402_5% SMB1_ALERT#

CNVI_RF_RESET#
CNVI_MODEM_CLKREQ CNVI_RF_RESET# 45
CNVI_MODEM_CLKREQ 45
1

RH830
71.5K_0402_1% RH829
CNVI@ 75K_0402_5%
CNVI@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (3/9) HDA,RTC,SMBUS,PM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 16 of 77
5 4 3 2 1
 5 4 3 2 1

D UH1G D
BE33 Y3
GPP_A16/CLKOUT_48 CLKOUT_ITPXDP Y4
D7 CLKOUT_ITPXDP_P
6 PCH_CPU_NSSC_CLK CLKOUT_CPUNSSC_P
C6 B6
6 PCH_CPU_NSSC_CLK# CLKOUT_CPUNSSC CLKOUT_CPUPCIBCLK PCH_CPU_PCIBCLK# 6
A6
CLKOUT_CPUPCIBCLK_P PCH_CPU_PCIBCLK 6
B8
6 PCH_CPU_BCLK CLKOUT_CPUBCLK_P
C8 AJ6
6 PCH_CPU_BCLK# CLKOUT_CPUBCLK CLKOUT_PCIE_N0 AJ7
XTAL24_OUT U9 CLKOUT_PCIE_P0
XTAL24_IN U10 XTAL_OUT AH9
XTAL_IN CLKOUT_PCIE_N1 AH10
RH6 1 2 60.4_0402_1% PCH_CLK_BIASREF T3 CLKOUT_PCIE_P1
XCLK_BIASREF AE14 CLK_PCIE_WLAN#
PDG_0 71 0Ω±1 % PCH_RTCX1 CLKOUT_PCIE_N2 CLK_PCIE_WLAN CLK_PCIE_WLAN# 45
CRB 0 Ω±1% PCH_RTCX2
BA49
RTCX1 CLKOUT_PCIE_P2
AE15
CLK_PCIE_WLAN 45 WLAN
BA48
need to confirm 0903 RTCX2 AE6 CLK_PCIE_LAN#
CLKOUT_PCIE_N3 CLK_PCIE_LAN CLK_PCIE_LAN# 51
+3VS
BF31
GPP_B5/SRCCLKREQ0# CLKOUT_PCIE_P3
AE7
CLK_PCIE_LAN 51 LAN
BE31
WLAN_CLKREQ# AR32 GPP_B6/SRCCLKREQ1# AC2
45 WLAN_CLKREQ# LAN_CLKREQ# GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_N4
BB30 AC3
51 LAN_CLKREQ# GPP_B8/SRCCLKREQ3# CLKOUT_PCIE_P4
BA30
AN29 GPP_B9/SRCCLKREQ4# AB2
RH89 1 2 10K_0201_5% LAN_CLKREQ# AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_N5 AB3
SSD_CLKREQ# AC48 GPP_H0/SRCCLKREQ6# CLKOUT_PCIE_P5
WLAN_CLKREQ# 45 SSD_CLKREQ# GPP_H1/SRCCLKREQ7#
RH90 1 2 10K_0201_5% AE41 W4
AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_N6 W3
RH93 1 2 10K_0201_5% SSD_CLKREQ# AC41 GPP_H3/SRCCLKREQ9# CLKOUT_PCIE_P6
GPU_CLKREQ# AC39 GPP_H4/SRCCLKREQ10# W7 CLK_PCIE_SSD#
GPU_CLKREQ# 24 GPU_CLKREQ# GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_N7 CLK_PCIE_SSD CLK_PCIE_SSD# 45
C RH94 1 2 10K_0201_5% AE39
GPP_H6/SRCCLKREQ12# CLKOUT_PCIE_P7
W6
CLK_PCIE_SSD 45 M.2 SSD C
AB48
RH852 1 @ 2 10K_0201_5% AC44 GPP_H7/SRCCLKREQ13# AC14
AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_N8 AC15
GPP_H9/SRCCLKREQ15# CLKOUT_PCIE_P8
V2 U2
V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_N9 U3
CLKOUT_PCIE_P15 CLKOUT_PCIE_P9
T2 AC9
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_N10 AC11
CLKOUT_PCIE_P14 CLKOUT_PCIE_P10
AA1 AE9 CLK_PCIE_GPU#
CLKOUT_PCIE_N13 CLKOUT_PCIE_N11 CLK_PCIE_GPU CLK_PCIE_GPU# 24
24 GPU
Y2 AE11
CLKOUT_PCIE_P13 CLKOUT_PCIE_P11 CLK_PCIE_GPU
AC7 R6
CLKOUT_PCIE_N12 CLKIN_XTAL CLKIN_XTAL_LCP 45
AC6 RH824 1 2 10K_0402_5%
CLKOUT_PCIE_P12
7 OF 13
CANNONLAKE-H-PCH_FCBGA874
@
change from 0ohm to 10K on 080 by Bing

change to 200K±1% on 0703

PCH_RTCX1
RH92 2 1 200K_0402_1%
B B
RH1 1 2 10M_0402_5% PCH_RTCX2
YH2
RH30
RH32 2 3 XTAL24_IN_LR 1 2 XTAL24_IN YH1
GND1 OSC2 1 2
XTAL24_OUT 1 2 XTAL24_OUT_LR 1 4 0_0402_5%
OSC1 GND2 32.768KHZ_9PF_X1A0001410002
0_0402_5% 1 1 1 1
24MHZ_6PF_7V24000032 V1 0
CH9 CH10 CH2 CH3
V1 0 15P_0402_50V8J 15P_0402_50V8J 9P_0402_50V8-B 8P_50V_B_NPO_0402
2 2 2 2

V1 0

Stone 051

Default De-Po if want to Po in B M need change PN to SM07000 00

L78 @
XTAL24_IN 1 2 XTAL24_IN_LR
1 2

XTAL24_OUT 4 3 XTAL24_OUT_LR
4 3
EXC24CH500U_4P
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (3/9) CLOCK,GPPBH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
A3 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 17 of 77
5 4 3 2 1
 5 4 3 2 1

SPI_SI_C
49,50 SPI_SI_C
SPI_SO_C
49,50 SPI_SO_C
SPI_CLK_PCH_C
49,50 SPI_CLK_PCH_C

D D

UH1A
BE36 AV29
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST# PLT_RST# 29,45,49,50,51

1
R15 Y47
R13 RSVD9 GPP_K16/GSXCLK Y46 RH43
RSVD10 GPP_K12/GSXDOUT Y48 RGB_KB_INT 50
100K_0201_5%
RH826 1 2 0_0201_5% AL37 GPP_K13/GSXSLOAD W46
1 AN35 VSS_247 GPP_K14/GSXDIN AA45
@ PAD TH37

2
TP_1 GPP_K15/GSXSRESET#
SPI_SI_R0 RH109 1 2 33_0402_5% SPI_SI_C R10668 1 2 1/16W_10_1%_0402 SPI_SI AU41 AL47
SPI_SO_R0 RH111 1 2 33_0402_5% SPI_SO_C R10669 1 2 1/16W_10_1%_0402 SPI_SO BA45 SPI0_MOSI GPP_E3/CPU_GP0 AM45
SPI_CS0#_R RH107 1 @ 2 0_0201_5% V1 0 SPI_CS0# AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32
SPI_CLK_PCH_0 49 SPI_CS0#_R 1 2 33_0402_5% SPI_CLK_PCH_CR10670 1 2 1/16W_10_1%_0402 SPI_CLK_PCH AW47 SPI0_CS0# GPP_B3/CPU_GP2 BC33
RH105 AW48 SPI0_CLK GPP_B4/CPU_GP3
SPI_WP#_R0 RH250 1 2 33_0402_5% SPI_WP#_C R10671 1 2 1/16W_10_1%_0402 SPI0_CS1# AE44 +3VALW_PCH
SPI_WP# AY48 GPP_H18/SML4ALERT# AJ46
56
SPI_HOLD#_R0 SPI_WP# 1 2 33_0402_5% SPI_HOLD#_C SPI_HOLD# SPI0_IO2 GPP_H17/SML4DATA
RH252 R10672 1 2 1/16W_10_1%_0402 BA46 AE43
SPI_CS2# AT40 SPI0_IO3 GPP_H16/SML4CLK AC47 RH825 1 2 100K_0402_5% Follow PDG:100K
50 SPI_CS2# SPI0_CS2# GPP_H15/SML3ALERT# AD48
BE19 GPP_H14/SML3DATA AF47 Strap PIN
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 RH753 1 @ 2 4.7K_0402_5%
BF18 GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# AD47
BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
BC17 GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
BD17 GPP_D22/SPI1_IO3 BB44 RH743 2 1 1M_0402_5%
GPP_D21/SPI1_IO2 INTRUDER# VCCRTC
1 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

+3VALW_PCH

change to 100K ull-u on 0703 GPP_H15 /SML3ALERT# (Strap reserved)

External pull-up is required. Recommend 100K if pulled
RH123 1 2 100K_0402_5% SPI_WP# up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be
C RH125 1 2 100K_0402_5% SPI_HOLD# RH771 1 @ 2 1K_0402_5% any on-board device driving it to opposite direction C
during strap sampling.
Power Plane: Primary Well

RH772 1 @ 2 1K_0402_5% SPI_SO GPP_H12 /SML2ALERT#

This signal has a weak internal pull-down.
0 = Master Attached Flash Sharing (MAFS) enabled
RH773 1 2 100K_0402_5% SPI_SI RH833 1 @ 2 1K_0402_5% (Default)
SPI_SI_XDP 56 1 = Slave Attached Flash Sharing (SAFS) enabled.
change to 100K ull-u on 070 Warning: This strap must be configured to ‘0’
+3V_SPI (SAFS is disabled) if the eSPI or LPC
+3VALW_PCH D2201 NPI@ 2 +3V_SPI
1RB520CM-30T2R_VMN2M2 strap is configured to ‘0’ (eSPI i s
SPI0_MOSI,SPI0_MISO,SPI0_IO[2:3] all have internal pull up disabled)
RC171 1 2 0_0402_5% Notes:
SPI0_MOSI 1. The internal pull-down is disabled after RSMRST#
+3VS V1 0 128Mb Flash ROM 1 External pull-up is required. Recommend 100K if pulled de-asserts.
UC3 up to 3.3V or 75K if pulled up to 1.8V. 2. This signal is in the primary well.
CH13
RC172 1 @ 2 0_0402_5% SPI_CS0#_R 1 8 .1U_0402_10V6-K This strap should sample HIGH. There should NOT be
/CS VCC any on-board device driving it to opposite direction
SPI_SO_R0 2 7 SPI_HOLD#_R0 2 during strap sampling.
DO(IO1) /HOLD(IO3)
+3V_SPI
SPI_WP#_R0 3 6 SPI_CLK_PCH_0 SPI0_IO2
1. If support DS3, connect to +3VS and don't support EC mirror code; /WP(IO2) CLK External pull-up is required. Recommend 100K if pulled
SPI_SI_R0 up to 3.3V or 75K if pulled up to 1.8V.
* 2. If don't support DS3, connect to +3VALW_PCH and support EC mirror code. 4
GND DI(IO0)
5
This strap should sample HIGH. There should NOT be

2
1
any on-board device driving it to opposite direction
RH119 CH268 during strap sampling.
W25Q128JVSIQ_SO8 10_0402_5% 10P_0402_50V8J
EMC_NS@ @ SPI0_IO3
2 External pull-up is required. Recommend 100K if pulled

1
up to 3.3V or 75K if pulled up to 1.8V.
1
CH11 This strap should sample HIGH. There should NOT be
10P_0402_50V8J any on-board device driving it to opposite direction
EMC_NS@ during strap sampling.
2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (5/9) SPI,SMBUS,GPPBEGH
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
Y540 2.0

Date: Friday, March 22, 2019 Sheet 18 of 77

5 4 3 2 1
 5 4 3 2 1

UH1B
DMI_CTX_PRX_N0 K34 J3 USB20_N0
5 DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI0_RXN USB2N_1 USB20_P0 USB20_N0 48
J35 J2
5 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 C33 DMI0_RXP USB2P_1 N13 USB20_N1 USB20_P0 48 BACK USB (3.0)
5 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI0_TXN USB2N_2 USB20_P1 USB20_N1 47
B33 N15
5 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 G33 DMI0_TXP USB2P_2 K4 USB20_N2 USB20_P1 47 LEFT USB (3.0)
5 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI1_RXN USB2N_3 USB20_P2 USB20_N2 50
D F34 K3 D
5 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 C32 DMI1_RXP USB2P_3 M10
USB20_P2 50 Right USB (3.0)
5 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI1_TXN USB2N_4 TYPE-C_PCH_USB20_N4 42
B32 L9
5 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI1_TXP USB2P_4 TYPE-C_PCH_USB20_P4 42Type C
5 DMI_CTX_PRX_N2 K32 M1
DMI_CTX_PRX_P2 J32 DMI2_RXN USB2N_5 L2
5 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI2_RXP USB2P_5 USB20_N6
C31 K7
5 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI2_TXN USB2N_6 USB20_P6 USB20_N6 39
B31 K6
5 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 G30 DMI2_TXP USB2P_6 L4 USB20_P6 39 Camera
5 DMI_CTX_PRX_N3 DMI3_RXN USB2N_7
DMI_CTX_PRX_P3 F30 L3
5 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI3_RXP USB2P_7
C29 G4
5 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3 DMI3_TXN USB2N_8
B29 G5
5 DMI_CRX_PTX_P3 DMI3_TXP USB2P_8 USB20_N9
A25 M6
DMI7_TXP USB2N_9 USB20_P9 USB20_N9 58
B25 N8
P24 DMI7_TXN USB2P_9 H3
USB20_P9 58 AG
R24 DMI7_RXP USB2N_10 H2
C26 DMI7_RXN USB2P_10 R10
B26 DMI6_TXP USB2N_11 P9 +3VALW_PCH
F26 DMI6_TXN USB2P_11 G1 RPH5
G26 DMI6_RXP USB2N_12 G2
B27 DMI6_RXN USB2P_12 N3 USB_OC4# 4 5
C27 DMI5_TXP USB2N_13 N2 USB_OC7# 3 6
L26 DMI5_TXN USB2P_13 E5 USB20_N14 USB_OC6# 2 7
DMI5_RXP USB2N_14 USB20_P14 USB20_N14 45 USB_OC3#
M26 F6 1 8
D29 DMI5_RXN USB2P_14 USB20_P14 45 Bluetooth
E28 DMI4_TXP AH36 USB_OC0# 10K_1206_8P4R_5%
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1#
M29 DMI4_RXP GPP_E10/USB2_OC1# AJ44 USB_OC2# USB_OC1# 50 USB 3.1 RPH6
DMI4_RXN GPP_E11/USB2_OC2# AL41 USB_OC3# USB_OC2# 47 USB Charger USB_OC0# 4 5
G17 GPP_E12/USB2_OC3# AV47 USB_OC4# USB_OC3# 48 USB 3.1 USB_OC5# 3 6
F16 PCIE1_RXN/USB31_7_RXNGPP_F15/USB2_OC4# AR35 USB_OC5# USB_OC2# 2 7
A17 PCIE1_RXP/USB31_7_RXPGPP_F16/USB2_OC5# AR37 USB_OC6# USB_OC1# 1 8
B17 PCIE1_TXN/USB31_7_TXNGPP_F17/USB2_OC6# AV43 USB_OC7#
R21 PCIE1_TXP/USB31_7_TXPGPP_F18/USB2_OC7#
PCIE2_RXN/USB31_8_RXN F4 Within 10K_1206_8P4R_5%
P21
PCIE2_RXP/USB31_8_RXP USB2_COMP 500 mils RH127 2 1 113_0402_1%
B18 F3 RC184 2 1 1K_0402_5%
C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 +3VALW_PCH
K18 PCIE2_TXP/USB31_8_TXP RSVD11 G3 RC183 2 1 1K_0402_5%
J18 PCIE3_RXN/USB31_9_RXN USB2_ID
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD7 RH814 1 2 100K_0201_5%
C19 PCIE3_TXN/USB31_9_TXN GPD7
C N18 PCIE3_TXP/USB31_9_TXP G45 C
R18 PCIE4_RXN/USB31_10_RXN PCIE24_TXP G46
Strap Pin, refer PDG
D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN

2
F20 G48
G20 PCIE5_RXN PCIE23_TXP G49 RH837
B21 PCIE5_RXP PCIE23_TXN W44
PCIE5_TXN PCIE23_RXP 10K_0201_5%
A22 W43 @
K21 PCIE5_TXP PCIE23_RXN H48

1
J21 PCIE6_RXN PCIE22_TXP H47
D21 PCIE6_RXP PCIE22_TXN U41
C21 PCIE6_TXN PCIE22_RXP U40
B23 PCIE6_TXP PCIE22_RXN F46
C23 PCIE7_TXP PCIE21_TXP G47
J24 PCIE7_TXN PCIE21_TXN R44
L24 PCIE7_RXP PCIE21_RXP T43
F24 PCIE7_RXN PCIE21_RXN
G24 PCIE8_RXN
B24 PCIE8_RXP
C24 PCIE8_TXN
PCIE8_TXP 2 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

B B

UH1M

PXS_PWREN RC10 1 @ 2 0_0201_5% PXS_PWREN_R AW13 BD4 CNVI_WR_CLK_N

29,53 PXS_PWREN PCH_GPU_EVENT# GPP_G0/SD_CMD CNV_WR_CLKN BE3 CNVI_WR_CLK_P CNVI_WR_CLK_N 45
BE9
29 PCH_GPU_EVENT# GPP_G1/SD_A0 CNV_WR_CLKP CNVI_WR_CLK_P 45
BF8
BF9 GPP_G2/SD_A1 BB3 CNVI_WR_D0_N
PXS_RST# PXS_RST#_R GPP_G3/SD_A2 CNV_WR_D0N BB4 CNVI_WR_D0_P CNVI_WR_D0_N 45
RC12 1 @ 2 0_0201_5% BG8
29 PXS_RST# GPP_G4/SD_A3 CNV_WR_D0P BA3 CNVI_WR_D1_N CNVI_WR_D0_P 45
Need to confirm with intel 05 @Stone BE8
GPP_G5/SD_CD# CNV_WR_D1N BA2 CNVI_WR_D1_P CNVI_WR_D1_N 45
V1 0 BD8
+1.8VALW PCH_FB_GC6_EN GPP_G6/SD_CLK CNV_WR_D1P CNVI_WR_D1_P 45
AV13
29 PCH_FB_GC6_EN GPP_G7/SD_WP BC5 CNVI_WT_CLK_N CNVI_WT_CLK_N 45
CNV_WT_CLKN BB6 CNVI_WT_CLK_P
CNV_WT_CLKP CNVI_WT_CLK_P 45
RH815 2 1 10K_0201_5% GPP_J4 AP3
RH809 1 2 20K_0402_5% GPP_J6 RH812 1 @ 2 2.2K_0402_5% +1.8VALW AP2 GPP_I11/M2_SKT2_CFG0 BE6 CNVI_WT_D0_N
GPP_I12/M2_SKT2_CFG1 CNV_WT_D0N BD7 CNVI_WT_D0_P CNVI_WT_D0_N 45
RH810 1 @ 2 2.2K_0201_5% GPP_J9 RH808 1 @ 2 2.2K_0201_5% AN4 CNVI_WT_D0_P 45
AM7 GPP_I13/M2_SKT2_CFG2 CNV_WT_D0P BG6 CNVI_WT_D1_N
GPP_I14/M2_SKT2_CFG3 CNV_WT_D1N BF6 CNVI_WT_D1_P CNVI_WT_D1_N 45
Strap Pin CNV_WT_D1P BA1 CNVI_WT_D1_P 45
1

AV6 R10391 1 CNVI@ 2

RH831 RH832 AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_RCOMP 150_0402_1%
20K_0402_5% 20K_0402_5% AR13 GPP_ J1 / CPU_C10_GATE# B12 PCIE_RCOMN
@ @ AV7 GPP_J11/A4WP_PRESENT PCIE_RCOMPN A13 PCIE_RCOMP RH741 2 1 100_0402_1%
GPP_J10 PCIE_RCOMPP BE5 SD_1P8_RCOMP CAD Note:
AW3 RH742 1 2 200_0402_1% Trace width=15 mils ,Spacing=15mil
2

AT10 GPP_J2 SD_1P8_RCOMP BE4 SD_3P3_RCOMP RH819 1 2 200_0402_1%

R10389 1 CNVI@ 2 33_0402_5% GPP_J4 AV4 GPP_J3 SD_3P3_RCOMP BD1 Max length= N/A mils.
45 CNVI_BRI_DT GPP_J4/CNV_BRI_DT_UART0B_RTS#GPPJ_RCOMP_1P8_1 BE1 RCOMP_1P8
45 CNVI_BRI_RSP AY2 RH820 1 2 200_0402_1% 0602 Stone: Add refer to EDS&CRB
R10393 1 CNVI@ 2 33_0402_5% GPP_J6 BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXDGPPJ_RCOMP_1P8_2 BE2
45 CNVI_RGI_DT GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P8_3
45 CNVI_RGI_RSP AV3
AW2 GPP_J7/CNV_RGI_RSP/UART0B_CTS# Y35
GPP_J9 AU9 GPP_J8/CNV_MFUART2_RXD RSVD12 Y36
GPP_J9/CNV_MFUART2_TXD RSVD13
BC1 CNVI_LDO_MON 1
13 OF 13 RSVD14 AL35 TH38 @
TP_2
CANNONLAKE-H-PCH_FCBGA874
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Blank
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 19 of 77
5 4 3 2 1
 5 4 3 2 1

+3VS

modify by Grace

@ Bit Boot BI S
RH160 2 1 10K_0201_5% PCH_BT_OFF#
GPP_B22 /GSPI1_MOSI (Boot BIOS Strap Bit BBS)
Destination
RH161 2 @ 1 10K_0201_5% PCH_WLAN_OFF# This Signal has a weak internal pull-down.
This field determines the destination of accesses to the
RH854 2 @ 1 10K_0201_5% VGA_ALERT#_PCH BIOS memory range. Also controllable using Boot BIOS 0 SPI (Default)
Destination bit (Bus0, Device31, Function0, offset DCh,bit6)
0: SPI(default)
1: LPC
D Notes: 1 LPC D
1. The internal pull-down is disabled after PCH_PWROK is high.
4. This signal is in the primary well.

+3VALW_PCH
Strap PIN
+3VALW_PCH
SKU ID
UH1K
RH750 1 @ 2 4.7K_0201_5% BA26
PCH_WLAN_OFF# BD30 GPP_B22/GSPI1_MOSI BA20
45 PCH_WLAN_OFF# V1 0 AU26 GPP_B21/GSPI1_MISO GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20
RH853 1 2 0_0201_5% AW26 GPP_B20/GSPI1_CLK GPP_D10/ISH_SPI_CLK/GSPI2_CLK BB16
58 F2_KEY

2
GPP_B19/GSPI1_CS0# GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
GPP_B18_NO_REBOOT BE30 GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI @ @
56 GPP_B18_NO_REBOOT GPP_B18/GSPI0_MOSI
BD29 BF14 @ @ @ @
51 LAN_PWR_ON# BF29 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18
BB26 GPP_B16/GSPI0_CLK GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN BF17

RH152 1

RH155 1

RH153 1

RH163 1

RH774 1

RH776 1
GPP_B15/GSPI0_CS0# GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17
EC_SCI# RH780 1 @ 2 0_0201_5% BB24 GPP_D13/ISH_UART0_RXD/I2C2_SDA
14,49 EC_SCI# PCH_BT_OFF# GPP_C9/UART0A_TXD PCH_GPA18
BE23
45 PCH_BT_OFF# AP24 GPP_C8/UART0A_RXD AG45 PCH_GPA19
50 PCH_TP_INT GPP_C11/UART0A_CTS# GPP_H20/ISH_I2C0_SCL PCH_GPA20
BA24 AH46
48 USBDEBUG GPP_C10/UART0A_RTS# GPP_H19/ISH_I2C0_SDA PCH_GPA21
BD21 AH47 PCH_GPA23
AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H22/ISH_I2C1_SCL AH48 PCH_GPA22
AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_H21/ISH_I2C1_SDA
24,29 VGA_PWRGD VGA_ALERT#_PCH GPP_C13/UART1_TXD/ISH_UART1_TXD
AU24

2 RH157

2 RH158

2 RH159

2 RH195

2 RH775

2 RH777
V1 0 GPP_C12/UART1_RXD/ISH_UART1_RXD AV34 PCH_GPA23
RH865 1 2 0_0201_5% EDP_SW_R AV21 GPP_A23/ISH_GP5 AW32 PCH_GPA22
57 EDP_SW GPP_C23/UART2_CTS# GPP_A22/ISH_GP4 PCH_GPA21
AW21 BA33
PCH_UART2_TXD BE20 GPP_C22/UART2_RTS# GPP_A21/ISH_GP3 BE34 PCH_GPA20

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%
45 PCH_UART2_TXD PCH_UART2_RXD GPP_C21/UART2_TXD GPP_A20/ISH_GP2 PCH_GPA19
BD20 BD34 @ @ @ @
45 PCH_UART2_RXD V1 0 GPP_C20/UART2_RXD GPP_A19/ISH_GP1 BF35 PCH_GPA18 @
RH857 1 2 0_0201_5% PCH_TP_CLK_R BE21 GPP_A18/ISH_GP0 BD38
50 PCH_TP_CLK PCH_TP_DATA_R BF21 GPP_C19/I2C1_SCL GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
RH858 1 2 0_0201_5%
50 PCH_TP_DATA

1
RH846 1 RGB@ 2 0_0201_5% BC22 GPP_C18/I2C1_SDA
50 PCH_RGBKB_SCL GPP_C17/I2C0_SCL
C RH847 1 RGB@ 2 0_0201_5% BF23 C
50 PCH_RGBKB_SDA BE15 GPP_C16/I2C0_SDA
BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
GPP_D23/ISH_I2C2_SCL/I2C3_SCL 11 OF 13
CANNONLAKE-H-PCH_FCBGA874
@

+3VALW_PCH
+1.8VS_AON

Function PCH_GPA18 PCH_GPA19 PCH_GPA 0 PCH_GPA 1 PCH_GPA PCH_GPA 3

1

R7725
4.7K_0402_5%
X X
Y540-15-N17P 0 0 0 0
2

@
2

EDP_SW_R
3 1 VGA_ALERT#_PCH
X X
29 VGA_ALERT#
Y540-15-N18E G0 0 0 0 1
1

R7726
QV22 4.7K_0402_5%
X X
B
LSI1012XT1G_SC-89-3
@
Y540-15-N18E G1 0 0 1 0 B
2

Y540-15-N18P 0 0 1 1 X X
V0

Y7000P-15-N17P 0 1 0 0 X X
X X
Y7000P-15-N18E G0 0 1 0 1
X X
Y7000P-15-N18E G1 0 1 1 0
X X
Y7000P-15-N18P 0 1 1 1
X X
Y540-17-N17P 1 0 0 0
Y540-17-N18E G0 1 0 0 1 X X

Y540-17-N18E G1 1 0 1 0 X X

Y540-17-N18P 1 0 1 1 X X
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (6/9) GPPPABCD, I2C
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 20 of 77

5 4 3 2 1
 5 4 3 2 1

+VCCPGPPD +1.8VALW

RH221 1 2 0_0402_5% +3VALW_PCH

+VCCPRIM_1P05 +VCCPFUSE_3P3
D D

1
RH220 1 2 0_0402_5%
RH789 +1.05VALW Need short +VCCPRIM_1P05
0_0805_5%
JC2 UH1H
1 2 AA22 AW9
+VCCPHV_3P3
+VCCPRIM_FUSE_1P05 2 1 2 AA23 VCCPRIM_1P05_1 VCCPRIM_3P3_2
@ VCCPRIM_1P05_2 +VCCPGPPA
AB20 BF47
JUMP_43X79 AB22 VCCPRIM_1P05_3 DCPRTC_1 BG47
VCCPRIM_1P05_4 DCPRTC_2 2

.1U_0402_10V6-K
RH791 1 2 0_0402_5% @ AB23 RH222 1 2 0_0402_5%
AB27 VCCPRIM_1P05_5 V23

CH26
+VCCPRIM_CNV_HVLDO_1P05 VCCPRIM_1P05_6 VCCPRIM_3P3_5 +VCCPUSB2_3P3 +VCCPGPPBC
AB28 AN44
VCCPRIM_1P05_7 VCCSPI +3V_SPI 1
AB30
RH790 1 2 0_0402_5% 4.174A (VCCPRIM_1P05) AD20 VCCPRIM_1P05_8 BC49 RH223 1 2 0_0402_5%
AD23 VCCPRIM_1P05_9 VCCRTC_1 BD49
+VCCDUSB_1P05 VCCPRIM_1P05_10 VCCRTC_2 +VCCRTC_3P3 +VCCPGPPEF
AD27
AD28 VCCPRIM_1P05_11 AN21
VCCPRIM_1P05_12 VCCPGPPG_3P3 +VCCPGPPG
RH792 1 2 0_0402_5% AD30 AY8 +VCCPHVLDO_3P3 RH224 1 2 0_0402_5%
+VCCPRIM_1P05 +VCCMPHY_1P05 AF23 VCCPRIM_1P05_13 VCCPRIM_3P3_3 BB7
+VCCDSW_1P05 AF27 VCCPRIM_1P05_16 VCCPRIM_3P3_4 +VCCPGPPG
JC4 AF30 VCCPRIM_1P05_17 AC35
VCCPRIM_1P05_18 VCCPGPPHK_1 +VCCPGPPHK
RH793 1 @ 2 0_0402_5% 1 2 U26 AC36 RH225 1 2 0_0402_5%
1 2 U29 VCCPRIM_1P05_23 VCCPGPPHK_2 AE35
+VCCCLPLLEBB_1P05 VCCPRIM_1P05_24 VCCPGPPEF_1 +VCCPGPPEF +VCCPUSB2_3P3
V25 AE36
JUMP_43X79 VCCPRIM_1P05_25 VCCPGPPEF_2
V27
RH794 1 2 0_0402_5% @ Add Jump by Bing 0627 V28 VCCPRIM_1P05_26 AN24 RH226 1 2 0_0402_5%
VCCPRIM_1P05_27 VCCPGPPD +VCCPGPPD
V30
+VCCAZPLL_1P05 V31 VCCPRIM_1P05_28 AN26 +VCCPGPPHK
VCCPRIM_1P05_29 VCCPGPPBC_1 AP26
VCCPGPPBC_2 +VCCPGPPBC
RH795 1 2 0_0402_5% +VCCPRIM_FUSE_1P05 AD31 RH784 1 2 0_0402_5%
+VCCA_SRC_1P05 AE17 VCCPRIM_1P05_14 AN32
+VCCPRIM_CNV_HVLDO_1P05 VCCPRIM_1P05_15 VCCPGPPA +VCCPGPPA +VCCPHV_3P3
RH797 1 2 0_0402_5% +VCCDUSB_1P05 W22 AT44 +VCCPFUSE_3P3 +VCCPGPPEF +VCCPGPPHK
W23 VCCDUSB_1P05_1 VCCPRIM_3P3_1 RH746 1 2 0_0402_5%
VCCDUSB_1P05_2 BE48
+VCCA_OCPLL1_1P05 VCCDSW_3P3_1 +VCCDSW +VCCPHVLDO_3P3
BG45 BE49

.1U_0402_10V6-K
+VCCDSW_1P05

.1U_0402_10V6-K
BG46 VCCDSW_1P05_1 VCCDSW_3P3_2
RH787 1 2 0_0402_5% VCCDSW_1P05_2 BB14 RH785 1 2 0_0402_5% 1 1
C C

CH270
+VCCHDA

CH81
W31 VCCHDA @
+VCCCLPLLEBB_1P05 VCCPRIM_MPHY_1P05 @
+VCCA_OC_1P05 D1 AG19
+VCCAZPLL_1P05 VCCPRIM_1P05_21 VCCPRIM_1P8_3
E1 AG20 2 2
RH798 1 2 0_0402_5% VCCPRIM_1P05_22 VCCPRIM_1P8_4 AN15
C49 VCCPRIM_1P8_5 AR15
+VCCAMPHYPLL_1P05 VCCAMPHYPLL_1P05_1 VCCPRIM_1P8_6
+VCCA_BCLKPLL2_1P05 D49 BB11
VCCAMPHYPLL_1P05_2 VCCPRIM_1P8_7 +VCCPRIM_1P8
E49
RH799 1 2 0_0402_5% VCCAMPHYPLL_1P05_3 AF19
P2 VCCPRIM_1P8_1 AF20 Option1:Use external VRM(default)
+VCCA_XTAL_1P05 VCCA_XTAL_1P05_1 VCCPRIM_1P8_2 +VCCPHVLDO_1P8 stuff RH816,unstuff RH807
P3
VCCA_XTAL_1P05_2 AG31 Option2:Use internal LDO
VCCPRIM_1P05_20 +VCCFHV1_1P05 unstuff RH816,stuff RH807
+VCCA_SRC_1P05 W19 AF31 +VCCFHV0_1P05 RH807 RH816
+VCCPRIM_1P05 W20 VCCA_SRC_1P05_1 VCCPRIM_1P05_19 +VCCPHVLDO_1P8 1 2 0_0402_5% +VCCPRIM_1P8 1 2 0_0402_5%
VCCA_SRC_1P05_2 +1.8VALW
+VCCFHV1_1P05 AK22 @
VCCPRIM_1P24_1 +VCCLDOSRAM_IN_1P24
+VCCA_OCPLL1_1P05 C1 AK23
RH199 1 2 0_0402_5% C2 VCCAPLL_1P05_4 VCCPRIM_1P24_2
VCCAPLL_1P05_5 AJ22
+VCCFHV0_1P05 V19 VCCDPHY_1P24_1 AJ23
+VCCA_OC_1P05 VCCA_BCLK_1P05 VCCDPHY_1P24_2 +VCCDPHY_1P24 1 1

CH278
1U_0402_6.3V6K
BG5

C10118
4.7U_0603_6.3V6K
VCCDPHY_1P24_3 +VCCDPHY_1P24_MAR
RH200 1 2 0_0402_5% B1
+VCCA_BCLKPLL2_1P05 B2 VCCAPLL_1P05_1 8 OF 13 K47 VCCMPHY_SENSE
B3 VCCAPLL_1P05_2 VCCMPHY_SENSE K46 VSSMPHY_SENSE 2 2@
VCCAPLL_1P05_3 VSSMPHY_SENSE
CANNONLAKE-H-PCH_FCBGA874
@

RH817 1 2 0_0402_5% +VCCDPHY_1P24

+VCCPRIM_1P05
+VCCA_XTAL_1P05
+VCCDPHY_1P24_MAR RH818 1 2 0_0402_5% +VCCLDOSRAM_IN_1P24
+VCCPRIM_1P05 +VCCMPHY_1P05 +VCCDSW_1P05 +VCCA_BCLKPLL2_1P05 +VCCDUSB_1P05
RH827 1 2 0_0603_5%

4.7U_0603_6.3V6K
1

CH276
22U_0603_6.3V6-M

CH274
22U_0603_6.3V6-M
1

C10119
1
CH253
22U_0603_6.3V6-M

1U_0402_6.3V6K

1 1 1 1 2 1 +VCCAMPHYPLL_1P05
CH29
22U_0603_6.3V6-M

CH30
1U_0402_6.3V6K

CH25
1U_0402_6.3V6K

CH272
1U_0402_6.3V6K

.1U_0402_10V6-K

2 Place close to BG5

B 2 B
CH279

CH292

@ LH2 1 2 0_0603_5% 2@ 2@
2 2 2 2 1@ 2
1 @ 1 1 1

CH255
1U_0402_6.3V6K

CH273
22U_0603_6.3V6-M

CH275
22U_0603_6.3V6-M
folllow PDG:
placeholder LC filter
If used,need to confirm LC spec
2 2 @ 2 @

VCCRTC +VCCRTC_3P3

RH216 1 2 0_0402_5%

1U_0402_6.3V6K

.1U_0402_10V6-K
1 1
CRB lace to PCH

CH245
CH244
+VCCPRIM_1P05
+1.05VALW_SENSE 2 2
1

RC283
100_0402_1%
@
2

+3VALW +VCCHDA +3VALW_PCH +VCCDSW

67 VCCMPHY_SENSE

67 VSSMPHY_SENSE
LH1 1 2 0_0402_5% RH206 1 2 0_0402_5%
1

@
+3VS +3VALW
@ RC281
100_0402_1%
LH3 1 @ 2 0_0402_5% RH205 1 2 0_0402_5%
2

.1U_0402_10V6-K
+VCCA_OCPLL1_1P05 +VCCPHVLDO_3P3 +VCCCLPLLEBB_1P05 +VCCAZPLL_1P05 +VCCA_OC_1P05

.1U_0402_10V6-K
2 V1 0 1

CH248

CH271
A A
@
.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

1 2
4.7U_0603_6.3V6K

2 1 1 1 2 1
CH287
1U_0402_6.3V6K

CH288

CH289

CH290
1U_0402_6.3V6K

CH291
C10050

1@ 2 2@ 2@ 1@ 2@

Security Classification LC Future Center Secret Data Title

follow CRB
Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (7/9) PWR
reservd by Bing 0627
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 21 of 77

5 4 3 2 1
 5 4 3 2 1

UH1L
BG3 M24
BG33 VSS_145 VSS_196 M32 UH1I
BG37 VSS_146 VSS_197 M34 A2 AL12
BG4 VSS_147 VSS_198 M49 A28 VSS_1 VSS_73 AL17
BG48 VSS_148 VSS_199 M5 A3 VSS_2 VSS_74 AL21
C12 VSS_149 VSS_200 N12 A33 VSS_3 VSS_75 AL24
D C25 VSS_150 VSS_201 N16 A37 VSS_4 VSS_76 AL26 D
C30 VSS_151 VSS_202 N34 A4 VSS_5 VSS_77 AL29
C4 VSS_152 VSS_203 N35 A45 VSS_6 VSS_78 AL33
C48 VSS_153 VSS_204 N37 A46 VSS_7 VSS_79 AL38
C5 VSS_154 VSS_205 N38 A47 VSS_8 VSS_80 AM1
D12 VSS_155 VSS_206 P26 A48 VSS_9 VSS_81 AM18
D16 VSS_156 VSS_207 P29 A5 VSS_10 VSS_82 AM32 UH1J
D17 VSS_157 VSS_208 P4 A8 VSS_11 VSS_83 AM49 Y14
D30 VSS_158 VSS_209 P46 AA19 VSS_12 VSS_84 AN12 RSVD7 Y15
D33 VSS_159 VSS_210 R12 AA20 VSS_13 VSS_85 AN16 RSVD8
VSS_160 VSS_211 VSS_14 VSS_86 U37
D8 R16 AA25 AN34 RSVD6
VSS_161 VSS_212 VSS_15 VSS_87 U35
E10 R26 AA27 AN38 RSVD5
E13 VSS_162 VSS_213 R29 AA28 VSS_16 VSS_88 AP4 N32
E15 VSS_163 VSS_214 R3 AA30 VSS_17 VSS_89 AP46 RSVD3 R32
E17 VSS_164 VSS_215 R34 AA31 VSS_18 VSS_90 AR12 RSVD4
E19 VSS_165 VSS_216 R38 AA49 VSS_19 VSS_91 AR16 AH15
E22 VSS_166 VSS_217 R4 AA5 VSS_20 VSS_92 AR34 RSVD2 AH14
E24 VSS_167 VSS_218 T17 AB19 VSS_21 VSS_93 AR38 RSVD1
E26 VSS_168 VSS_219 T18 AB25 VSS_22 VSS_94 AT1
E31 VSS_169 VSS_220 T32 AB31 VSS_23 VSS_95 AT16
E33 VSS_170 VSS_221 T4 AC12 VSS_24 VSS_96 AT18 AL2
E35 VSS_171 VSS_222 T49 AC17 VSS_25 VSS_97 AT21 PREQ#
10 OF 13 AM5 PCH_PREQ# 56
E40 VSS_172 VSS_223 T5 AC33 VSS_26 VSS_98 AT24 PRDY# AM4 PCH_PRDY# 56
VSS_173 VSS_224 VSS_27 VSS_99 CPU_TRST# CPU_TRST# 56
E42 T7 AC38 AT26 AK3 PCH_TRIGOUT RH758 1 2 30_0402_5% CPU_TRIGIN 6
C VSS_174 VSS_225 VSS_28 VSS_100 TRIGGER_OUT C
E8 U12 AC4 AT29 AK2
VSS_175 VSS_226 VSS_29 VSS_101 TRIGGER_IN PCH_TRIGIN 6
F41 U15 AC46 AT32
F43 VSS_176 VSS_227 U17 AD1 VSS_30 VSS_102 AT34 CANNONLAKE-H-PCH_FCBGA874
F47 VSS_177 VSS_228 U21 AD19 VSS_31 VSS_103 AT45
VSS_178 VSS_229 VSS_32 VSS_104 @
G44 U24 AD2 AV11 1
G6 VSS_179 VSS_230 U33 AD22 VSS_33 VSS_105 AV39 CC181
H8 VSS_180 VSS_231 U38 AD25 VSS_34 VSS_106 AW10 .1U_0402_10V6-K
J10 VSS_181 VSS_232 V20 AD49 VSS_35 VSS_107 AW4 @
J26 VSS_182 VSS_233 V22 AE12 VSS_36 VSS_108 AW40 2
J29 VSS_183 VSS_234 V4 AE33 VSS_37 VSS_109 AW46
J4 VSS_184 VSS_235 V46 AE38 VSS_38 VSS_110 B47
J40 VSS_185 VSS_236 W25 AE4 VSS_39 VSS_111 B48
J46 VSS_186 VSS_237 W27 AE46 VSS_40 VSS_112 B49
J47 VSS_187 VSS_238 W28 AF22 VSS_41 VSS_113 BA12
J48 VSS_188 VSS_239 W30 AF25 VSS_42 VSS_114 BA14
J9 VSS_189 VSS_240 Y10 AF28 VSS_43 VSS_115 BA44
K11 VSS_190 VSS_241 Y12 AG1 VSS_44 VSS_116 BA5
K39 VSS_191 VSS_242 Y17 AG22 VSS_45 VSS_117 BA6
M16 VSS_192 VSS_243 Y33 AG23 VSS_46 VSS_118 BB41
M18 VSS_193 VSS_244 AG25 VSS_47 VSS_119 BB43
M21 VSS_194 Y38 AG27 VSS_48 VSS_120 BB9
VSS_19512 OF 13VSS_245 Y9 AG28 VSS_49 VSS_121 BC10
VSS_246 AG30 VSS_50 VSS_122 BC13
CANNONLAKE-H-PCH_FCBGA874 AG49 VSS_51 VSS_123 BC15
B B
AH12 VSS_52 VSS_124 BC19
@ VSS_53 VSS_125
AH17 BC24
AH33 VSS_54 VSS_126 BC26
AH38 VSS_55 VSS_127 BC31
AJ19 VSS_56 VSS_128 BC35
AJ20 VSS_57 VSS_129 BC40
AJ25 VSS_58 VSS_130 BC45
AJ27 VSS_59 VSS_131 BC8
AJ28 VSS_60 VSS_132 BD43
AJ30 VSS_61 VSS_133 BE44
AJ31 VSS_62 VSS_134 BF1
AK19 VSS_63 VSS_135 BF2
AK20 VSS_64 VSS_136 BF3
AK25 VSS_65 VSS_137 BF48
AK27 VSS_66 VSS_138 BF49
AK28 VSS_67 VSS_139 BG17
AK30 VSS_68 VSS_140 BG2
AK31 VSS_69 VSS_141 BG22
AK4 VSS_70 VSS_142 BG25
AK46 VSS_71 VSS_143 BG28
VSS_72 9 OF 13 VSS_144
CANNONLAKE-H-PCH_FCBGA874
@
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PCH (9/9) VSS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Y540 2.0

Date: Friday, March 22, 2019 Sheet 22 of 77

5 4 3 2 1
 5 4 3 2 1

N18E-G1 GPIO H=High: Tied to 1.8V

M=Middle: Tied to 0.9V
GPIO I/O GPIO Name Function Description Net name I/O Termination
L=Low: Tied to 0V FS_OVERT# FUNCTION
GPIO0 OUT NVVDD_PWM_VID PWM Output to control NVVDD NVVDD_PWM_VID
STRAP2 STRAP1 STRAP0 RAMCFG[4:0] N18E-G1 VRAM ROM_SO ROM_SI ROM_SCLK FS_OVERT# FUNCTION
GPIO1 OUT GC6:GC6_FB_EN GC6 FRAME BUFFER ENABLE FB_GC6_EN (10K pull down) Samsung
L L L 0 (0x0000) K4Z80325BC-HC14 L L L FS_OVERT# function ENABLE
GPIO2 IN GC6:GPU_EVENT* Wake the GPU from GC6 state GPU_EVENT#_R (10K pull High) Micron FS_OVERT# function DISABLED
L L H 1 (0x0001) MT61K256M32JE-14:A L L H Reserved; do not configure
GPIO3 OUT UNUSED UNUSED UNUSED
D L H L 2 (0x0002) D

GPIO4 OUT GC6:1V8_MAIN_EN GPU power sequencing for GC6 --- 1V8_MAIN_EN 1V8_MAIN_EN (10K pull High)
L H H 3 (0x0003)
GPIO5 IN FRAME_LOCK* Active low Frame Lock for NVSR panel GPU_FRAME_LOCK#
H L L 4 (0x0004)
GPIO6 OUT NVVDD_PSI* Phase Shedding, NVVDD_PSI NVVDD_PSI (5.1K pull High)
H L H 5 (0x0005)
GPIO7 OUT LCD_BL_PWM LCD Panel Backlight PWM GPU_EDP_PWM (100K pull down)
H H L 6 (0x0006)
GPIO8 OUT MEM_VDD_CTL Memory voltage Control FBVDDQ_SEL (10K pull down)
H H H 7 (0x0007)
GPIO9 I/O THERM_ALERT* Active Low Thermal Alert VGA_ALERT# (10K pull High)
L L M 8 (0x0008)
GPIO10 OUT MEM_VREF_CTL Memory VREF Control MEM_VREF (10K pull down)
L M L 9 (0x0009)
GPIO11 OUT LCD_VCC LCD Panel VOLTAGE GPU_EDP_ENVDD (10K pull down)
L M H 10 (0x000A)
GPIO12 IN PWR_LEVEL AC power detect or power supply overdraw input VGA_AC_DET_R (10K pull High)
L H M 11 (0x000B)
GPIO13 OUT UNUSED UNUSED UNUSED
M L L 12 (0x000C)
GPIO14 IN HPD_IFPA* Hot Plug Detect for IFPA IFPA_HPD (10K pull High)
M L H 13 (0x000D)
GPIO15 IN HPD_IFPB* Hot Plug Detect for IFPB UNUSED

C GPIO16 OUT UNUSED UNUSED UNUSED C

GPIO17 IN HPD_IFPD* Hot Plug Detect for IFPD GPU_EDP_ENBKL (100K pull down)

GPIO18 IN HPD_IFPE* Hot Plug Detect for IFPE IFPE_HPD (10K pull High)

GPIO19 OUT Reserved UNUSED UNUSED

GPIO20 OUT GC6:NB_FGC6 Low Power States Fast CG6 NB_FGC6 (10K pull down)

GPIO21 OUT LCD_BLEN LCD Panel Backlight Enable GPU_EDP_ENBKL

GPIO22 UNUSED UNUSED UNUSED

GPIO23 UNUSED UNUSED RASTER_SYNC1 (100K pull down)

HPD_IFPF*/USBC_HPD*
GPIO24 IN or DONGLE_DET* Hot Plug Detect for IFPF or USBC UNUSED

GPIO25 OUT FBVDD_PSI Turns off phases of the Frame buffer power supply FBVDDQ_PSI (5.1K pull High)
1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO26 FP_FUSE Field-programming of select fuses GPIO26_FP_FUSE (10K pull down) 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO27 IN HPD_IFPC* Hot Plug Detect for IFPC IFPC_HPD (10K pull High) 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO28 ADC_MUX_SEL OVRM MUX SEL ADC_MUX_SEL_R (10K pull High)
B B
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO29 OUT IDLE_IN_SW IDLE_IN_SW IDLE_IN_SW (10K pull down)
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO30 UNUSED UNUSED UNUSED
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
0:VGA_DEVICE DISABLE
L M H 1 0 1 0
N18E-G1 Power Sequence
L M L 1 0 0 1

L L M 1 0 0 0
+1 0VGS
+1 8VS_A N
H H H 0 1 1 1
+1 8VGS
+1 8VGS
H H L 0 1 1 0
NVVDD
NVVDD
H L H 0 1 0 1
FBVDDQ
+1 0VGS
H L L 0 1 0 0
+1 8VS_A N
FBVDDQ
L H H 0 0 1 1

L H L 0 0 1 0
1 The ram time for any rail must be more than 0us 1 P XVDD must ower down before NVVDD
and is recommended to be less than ms L L H 0 0 0 1 DEFAULT
A For GDDR VPP must be equal to or higher than A
Delay from 1V8_MAIN_ N to P XVDD/NVVDD_PG D FBVDD/Q at all times use gate logic and discharge
must N T e ceed ms circuit as needed L L L 0 0 0 0
3 It is recommended that the delay from 1V8_A N 3 All 3 3V devices that connect to the GPU must be
on to P XVDD/NVVDD_PG D assertion not e ceed 0ms ram down before 1V8_A N GPU can N T have any 3 3V
leakage ath after 1V8_A N and 1 8V_MAIN ower down
Power u NVVDD must be 90% before P XVDD can start ram -u
Power down of P XVDD must be less than 10% before
5 All 3 3V devices that connect to the GPU must be owered after NVVDD can start ram -down
1V8_A N GPU cannot have any 3 3V leakage aths before 1V8_A N is resent Title
Security Classification LC Future Center Secret Data
Refer to the J D C Memory SP C for memory-related ower sequencing
Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E VGA Notes List
7 FBVDD/Q USB_VDDP and 1V8_A N don't need ower cycle for GC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 23 of 77

5 4 3 2 1
 5 4 3 2 1

UV1A
?
?
COMMON
UV1V
+1.0VGS CORE_PLLVDD ?
1/22 PCI_EXPRESS ?
COMMON
TV12@ 1 PEX_WAKE# BK44 under GPU near GPU 13/22 XTAL/PLL
PEX_WAKE_N BB35

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
PLT_RST_VGA# BK26 PEX_DVDD_1 BB36 VID_PLLVDD_GPU_BD12 BD12
29 PLT_RST_VGA# PEX_RST_N PEX_DVDD_2 SP_PLLVDD
BC35 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
CLK_REQ_GPU# BL26 PEX_DVDD_3 BC36 VID_PLLVDD_GPU_BC12 BC12
PEX_CLKREQ_N PEX_DVDD_4 BD33 VID_PLLVDD
CLK_PCIE_GPU BM26 PEX_DVDD_5 BD36
17 CLK_PCIE_GPU PEX_REFCLK PEX_DVDD_6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1
CLK_PCIE_GPU# BM27 CV314 CV315
17 CLK_PCIE_GPU# PEX_REFCLK_N

@
BB33

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV2

CV3

CV4

CV5
1U_6.3V_K_X5R_0201 1U_6.3V_K_X5R_0201

CV536

CV537

CV538

CV539

CV540

CV541

CV542

CV543

CV544

CV545

CV546

CV547

CV548

CV549

CV550

CV553

CV551

CV552

CV555

CV554
PCIE_CRX_GTX_P0 CV12 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P0 BG26 PEX_CVDD_1 BC33 OPT@ OPT@
5 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0 PCIE_CRX_C_GTX_N0 PEX_TX0 PEX_CVDD_2 2 2
5 PCIE_CRX_GTX_N0 CV13 1 2 0.22U_0201_6.3V6-K OPT@ BH26
PEX_TX0_N
PCIE_CTX_C_GRX_P0 BL27 under GPU
5 PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_N0 PEX_RX0 +1.8VS_VGA
BK27
5 PCIE_CTX_C_GRX_N0 PEX_RX0_N CORE_PLLVDD_GPU U42
D PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1 GPCPLL_AVDD0
5 PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0201_6.3V6-K OPT@ BF26
PEX_TX1
under GPU near GPU D
PCIE_CRX_GTX_N1 PCIE_CRX_C_GTX_N1

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
5 PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0201_6.3V6-K OPT@ BE26 BB26 1 1 1 AF11

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
PEX_TX1_N PEX_HVDD_1 GPCPLL_AVDD1

CV316 OPT@

CV317 OPT@

CV318 OPT@
BB27

22U_6.3V_M_X6S_0603
PCIE_CTX_C_GRX_P1 BK29 PEX_HVDD_2 BB29 BB24
5 PCIE_CTX_C_GRX_P1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
PEX_RX1 PEX_HVDD_3 XSN_PLLVDD

1
PCIE_CTX_C_GRX_N1 BL29 BB32 +1.8VS_AON
5 PCIE_CTX_C_GRX_N1 PEX_RX1_N PEX_HVDD_4 2 2 2
BC26
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P2 BF27 PEX_HVDD_5 BC27
5 PCIE_CRX_GTX_P2

2
PEX_TX2 PEX_HVDD_6

2
PCIE_CRX_GTX_N2 CV23 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N2 BG27 BC29 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
5 PCIE_CRX_GTX_N2 PEX_TX2_N PEX_HVDD_7

@
BC30

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
RV211

CV522

CV523

CV524

CV525

CV526

CV527

CV528

CV529

CV530

CV531

CV532

CV533

CV309

CV310

CV534

CV302

CV535
PCIE_CTX_C_GRX_P2 BM29 PEX_HVDD_8 BC32 10K_0402_5%
5 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_N2 PEX_RX2 PEX_HVDD_9
5 PCIE_CTX_C_GRX_N2
BM30
PEX_RX2_N PEX_HVDD_10
BD27 under GPU @
BD30

1
PCIE_CRX_GTX_P3 CV24 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P3 BG29 PEX_HVDD_11
5 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_C_GTX_N3 PEX_TX3
5 PCIE_CRX_GTX_N3 CV25 1 2 0.22U_0201_6.3V6-K OPT@ BH29 1 2 XTALSSIN BJ6 BK6 XTALOUT
PEX_TX3_N RV305 EXT_REFCLK_FL XTAL_OUTBUFF
PCIE_CTX_C_GRX_P3 BL30 10K_0402_5% XTAL_IN BL6 BM6 XTAL_OUT
5 PCIE_CTX_C_GRX_P3

1
PCIE_CTX_C_GRX_N3 BK30 PEX_RX3 V1 0 OPT@ XTAL_IN XTAL_OUT
5 PCIE_CTX_C_GRX_N3 PEX_RX3_N RV46
PCIE_CRX_GTX_P4 CV26 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P4 BF29 N18E-FCBGA2228_BGA2228 100K_0402_5%
5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_C_GTX_N4 PEX_TX4
5 PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0201_6.3V6-K OPT@ BE29 @ 1 2 OPT@
PEX_TX4_N
Need cofirm RV209

2
PCIE_CTX_C_GRX_P4 BK32 near GPU 10M_0402_5% OPT@
5 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_N4 PEX_RX4 +1.8VS_VGA
BL32
5 PCIE_CTX_C_GRX_N4 PEX_RX4_N YV1
PCIE_CRX_GTX_P5 PCIE_CRX_C_GTX_P5 +1.8VS_VGA
30ohms (ESR=0.01) Bead CORE_PLLVDD
CV28 1 2 0.22U_0201_6.3V6-K OPT@ BF30
5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 CV29 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N5 BG30 PEX_TX5 P/N;SM01000M300 XTAL_IN 1 4
5 PCIE_CRX_GTX_N5 PEX_TX5_N PEX_PLL_HVDD N18 change OSC1 GND2
BB30 LV9 1 2 0_0603_5%
PCIE_CTX_C_GRX_P5 BM32 PEX_PLL_HVDD 1 2 2 3 XTAL_OUT
5 PCIE_CTX_C_GRX_P5

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
PCIE_CTX_C_GRX_N5 BM33 PEX_RX5 V1 0 LV11 GND1 OSC2
5 PCIE_CTX_C_GRX_N5 PEX_RX5_N
1 1 1 HCB1608KF-300T60_2P 1 1 1 1

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
PCIE_CRX_GTX_P6 PCIE_CRX_C_GTX_P6

22U_0603_6.3V6-M
5 PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0201_6.3V6-K OPT@ BG32 OPT@ CV262 27MHZ_10PF_7V27000050 CV263
PCIE_CRX_GTX_N6 CV34 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N6 BH32 PEX_TX6 10P_0402_50V8J OPT@ 10P_0402_50V8J
5 PCIE_CRX_GTX_N6 PEX_TX6_N OPT@ OPT@
PCIE_CTX_C_GRX_P6 BL33 2 2 2 2 2 2 2

OPT@
5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_N6 PEX_RX6

@
BK33

OPT@

OPT@

OPT@
CV311

CV521

CV520

CV313
5 PCIE_CTX_C_GRX_N6

CV312
PEX_RX6_N
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P7 BF32
5 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_C_GTX_N7 PEX_TX7
5 PCIE_CRX_GTX_N7 CV36 1 2 0.22U_0201_6.3V6-K OPT@ BE32
PEX_TX7_N
PCIE_CTX_C_GRX_P7 BK35
5 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_N7 PEX_RX7
BL35
5 PCIE_CTX_C_GRX_N7 PEX_RX7_N
PCIE_CRX_GTX_P8 CV38 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P8 BF33
5 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_N8 PCIE_CRX_C_GTX_N8 PEX_TX8
5 PCIE_CRX_GTX_N8 CV39 1 2 0.22U_0201_6.3V6-K OPT@ BG33
PEX_TX8_N
PCIE_CTX_C_GRX_P8 BM35
5 PCIE_CTX_C_GRX_P8 PCIE_CTX_C_GRX_N8 PEX_RX8
BM36
5 PCIE_CTX_C_GRX_N8 PEX_RX8_N
PCIE_CRX_GTX_P9 CV40 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P9 BG35
5 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_N9 PCIE_CRX_C_GTX_N9 PEX_TX9
5 PCIE_CRX_GTX_N9 CV42 1 2 0.22U_0201_6.3V6-K OPT@ BH35
C PEX_TX9_N C
PCIE_CTX_C_GRX_P9 BL36
5 PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_N9 PEX_RX9
BK36
5 PCIE_CTX_C_GRX_N9 PEX_RX9_N
PCIE_CRX_GTX_P10 CV43 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P10 BF35
5 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_N10 PCIE_CRX_C_GTX_N10 PEX_TX10
5 PCIE_CRX_GTX_N10 CV44 1 2 0.22U_0201_6.3V6-K OPT@ BE35
PEX_TX10_N
PCIE_CTX_C_GRX_P10 BK38
5 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10 PEX_RX10
BL38
5 PCIE_CTX_C_GRX_N10 PEX_RX10_N
PCIE_CRX_GTX_P11 CV45 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P11 BF36
5 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_N11 PCIE_CRX_C_GTX_N11 PEX_TX11
5 PCIE_CRX_GTX_N11 CV46 1 2 0.22U_0201_6.3V6-K OPT@ BG36
PEX_TX11_N
PCIE_CTX_C_GRX_P11 BM38 +1.8VS_VGA
5 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11 PEX_RX11
BM39
5 PCIE_CTX_C_GRX_N11 PEX_RX11_N
PCIE_CRX_GTX_P12 CV47 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P12 BG38
5 PCIE_CRX_GTX_P12 PEX_TX12

2
PCIE_CRX_GTX_N12 CV48 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N12 BH38
5 PCIE_CRX_GTX_N12 PEX_TX12_N RV27 RV29
PCIE_CTX_C_GRX_P12 BL39 5.6K_0402_1% 10K_0402_5%
5 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PEX_RX12
BK39 @ OPT@
5 PCIE_CTX_C_GRX_N12 PEX_RX12_N

1
PCIE_CRX_GTX_P13 CV49 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P13 BF38 +1.8VS_AON
5 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_N13 PCIE_CRX_C_GTX_N13 PEX_TX13
5 PCIE_CRX_GTX_N13 CV50 1 2 0.22U_0201_6.3V6-K OPT@ BE38
20,29 VGA_PWRGD
1 2
PEX_TX13_N RV31
PCIE_CTX_C_GRX_P13 BK41 0_0402_5%
5 PCIE_CTX_C_GRX_P13 PEX_RX13 1
PCIE_CTX_C_GRX_N13 BL41 @ CV66
5 PCIE_CTX_C_GRX_N13 PEX_RX13_N

2
.1U_0402_10V6-K
PCIE_CRX_GTX_P14 CV54 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P14 BF39 @
5 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_N14 PCIE_CRX_C_GTX_N14 PEX_TX14 2
5 PCIE_CRX_GTX_N14 CV55 1 2 0.22U_0201_6.3V6-K OPT@ BG39
PEX_TX14_N

10K_0402_5%
PCIE_CTX_C_GRX_P14 BM41
5 PCIE_CTX_C_GRX_P14

1
PCIE_CTX_C_GRX_N14 BM42 PEX_RX14
5 PCIE_CTX_C_GRX_N14 PEX_RX14_N

OPT@
RV67
2
PCIE_CRX_GTX_P15 CV56 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P15 BH41
5 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_N15 PCIE_CRX_C_GTX_N15 PEX_TX15
5 PCIE_CRX_GTX_N15 CV57 1 2 0.22U_0201_6.3V6-K OPT@ BG41
PEX_TX15_N
PCIE_CTX_C_GRX_P15 BL42 BL44 PEX_TERMP 1 2 1 3 CLK_REQ_GPU#
5 PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15 PEX_RX15 PEX_TERMP 17 GPU_CLKREQ#
BK42 RV34
5 PCIE_CTX_C_GRX_N15 PEX_RX15_N 2.49K_0402_1%
OPT@ QV2
LSI1012XT1G_SC-89-3
OPT@
N18E-FCBGA2228_BGA2228 Vgs(th)≤0.9V
@

B B

choose one 1
RV1207
2
OVERT#_NVEN 29 u dated by bing gu 0180308
0_0402_5%
@
1 2 +1.0VGS
WRST# 49
RV20

+3VS
0_0402_5%
@
For SWG mode +1.0VGS Discharge
1

1
RV2 RV102 RV109
10K_0402_5% 5.11_0805_1% 5.11_0805_1%
@ +5VALW OPT@ OPT@
V0
2

2
3

D
1

5 QV24B
G LBSS138DW1T1G_SOT363-6 RV100
S @ 47K_0402_5%
4
6

1
D OPT@
OVERT# 2 QV24A

D
29 OVERT#
2

G LBSS138DW1T1G_SOT363-6
A S @ 2 QV15 A
1

G AO3402_SOT-23-3
OPT@
S
1

D D
1
3

PLT_RST_VGA# 1 2 2 QV16
29,74 1V0_MAIN_EN
2 QV14 Vgs(th)≤1.5V
RV3 G LBSS139WT1G_SC70-3 CV20 G LBSS139WT1G_SC70-3
1

0_0402_5% S @ .1U_0402_10V6-K S OPT@

3

@ 2@ RV104
1 100K_0402_5% Vgs(th)≤1.5V
CV21 @
.1U_0402_10V6-K
2

@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_PEG I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 2.0

Date: Friday, March 22, 2019 Sheet 24 of 77

5 4 3 2 1
 5 4 3 2 1

GPU_SNK0_AUX_DN RV14 1 OPT@ 2 100K_0402_5%

GPU_SNK0_AUX_DP RV15 1 OPT@ 2 100K_0402_5%

UV1N
?
? UV1O
COMMON
?
?
7/22 IFPAB COMMON
8/22 IFPC
DL-DVI DVI/HDMI DP
RV73 2 OPT@ 1 IFPCD_RSET BD20
1K_0402_1% IFPCD_RSET
GPU_SNK0_AUX_DN DVI/HDMI DP
BH11 CORE_PLLVDD
SDA SDA IFPA_AUX_SDA_N GPU_SNK0_AUX_DP GPU_SNK0_AUX_DN 41
BG11
SCL SCL IFPA_AUX_SCL GPU_SNK0_AUX_DP 41 1 2 0_0603_5% +IFPCD_PLLVDD BD18 BL9
RV341
V1 0 IFPCD_PLLVDD SDA IFPC_AUX_SDA_N BK9 HDMI1_DAT 44
GPU_SNK0_DP3N SCL IFPC_AUX_SCL HDMI1_CLK 44

1U_6.3V_K_X5R_0201
D BF21 D
TXC TXC IFPA_L3_N GPU_SNK0_DP3N 41 1
IFPAB_RSET GPU_SNK0_DP3P

CV222

OPT@
RV68 2 OPT@ 1 BD23 BG21
IFPAB_RSET TXC TXC IFPA_L3 GPU_SNK0_DP3P 41 HDMI1_TXC-
1K_0402_1% TXC
BF17
IFPC_L3_N BE17 HDMI1_TXC+ HDMI1_TXC- 44
CORE_PLLVDD BG23 GPU_SNK0_DP2N 2 TXC IFPC_L3 HDMI1_TXC+ 44 HDMI CLK
TXD0 TXD0 IFPA_L2_N GPU_SNK0_DP2P GPU_SNK0_DP2N 41 HDMI1_TX0-
BH23 BF18
+IFPAB_PLLVDD TXD0 TXD0 IFPA_L2 GPU_SNK0_DP2P 41 TXD0 IFPC_L2_N HDMI1_TX0+ HDMI1_TX0- 44
RV69 1 2 0_0603_5% BD21 TXD0
BG18 HDMI D0
IFPAB_PLLVDD IFPC_L2 HDMI1_TX0+ 44
GPU_SNK0_DP1N IFPC HDMI1_TX1- For HDMI

1U_6.3V_K_X5R_0201
V1 0 1 BF23 TXD1 BG20
TXD1 TXD1 IFPA_L1_N GPU_SNK0_DP1P GPU_SNK0_DP1N 41 IFPC_L1_N HDMI1_TX1+ HDMI1_TX1- 44

CV7

OPT@
BE23 TXD1 BH20 HDMI D1
TXD1 TXD1 IFPA_L1 GPU_SNK0_DP1P 41 IFPC_L1 HDMI1_TX1+ 44
BF20 HDMI1_TX2-
2 GPU_SNK0_DP0N TXD2 IFPC_L0_N HDMI1_TX2+ HDMI1_TX2- 44
TXD2 TXD2
BF24 TXD2
BE20 HDMI D2
IFPA_L0_N BG24 GPU_SNK0_DP0P GPU_SNK0_DP0N 41 +1.0VGS IFPC_L0 HDMI1_TX2+ 44
TXD2 TXD2 IFPA_L0 GPU_SNK0_DP0P 41
RV501 1 2 0_0603_5% +IFPC_IOVDD BB23
V1 0 BC17 IFP_IOVDD_5
IFP_IOVDD_6

Type-C DP

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1 1 1 N18E-FCBGA2228_BGA2228

OPT@

OPT@

OPT@
BG12 @

4.7U_0603_6.3V6K
SDA IFPB_AUX_SDA_N BH12
SCL IFPB_AUX_SCL
+1.0VGS 2 2 2
V1 0 BL18

CV68
CV488

CV223
RV72 1 2 0_0603_5% +IFPAB_IOVDD BB18 TXC IFPB_L3_N BK18
BB17 IFP_IOVDD_2 TXC IFPB_L3
IFP_IOVDD_1
1 1 1 1 1 BB20 BK20
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
IFP_IOVDD_3 TXD3 TXD0 IFPB_L2_N
@

@
BB21 BL20 near GPU under GPU
OPT@

OPT@

OPT@
4.7U_0603_6.3V6K

IFP_IOVDD_4 TXD3 TXD0 IFPB_L2

2 2 2 2 2 BM20
TXD4 TXD1 IFPB_L1_N BM21
CV75

CV69

CV70

CV71
CV227

TXD4 TXD1 IFPB_L1

TXD5 TXD2
BL21
IFPB_L0_N BK21
TXD5 TXD2 IFPB_L0
near GPU under GPU IFPAB
N18E-FCBGA2228_BGA2228
@

UV1Q
C ? C
?
COMMON
10/22 IFPE
UV1P DVI/HDMI DP
?
?
COMMON GPU_EDP_AUX# RV1286 1 2 100K_0402_5% RV71 2 OPT@ 1 IFPE_RSET BD17 BL8 GPU_DPC_AUX_DN
IFPE_RSET SDA IFPE_AUX_SDA_N GPU_DPC_AUX_DN 43
9/22 IFPD OPT@ 1K_0402_1% BK8 GPU_DPC_AUX_DP
SCL IFPE_AUX_SCL GPU_DPC_AUX_DP 43
GPU_EDP_AUX RV1287 1 2 100K_0402_5%
OPT@ CORE_PLLVDD
DVI/HDMI DP BG14 GPU_DPC_TX3_DN
1 2 0_0603_5% +IFPE_PLLVDD BD15 TXC IFPE_L3_N BH14 GPU_DPC_TX3_DP GPU_DPC_TX3_DN 43
RV70
IFPE_PLLVDD TXC IFPE_L3 GPU_DPC_TX3_DP 43
GPU_EDP_AUX# GPU_DPC_TX2_DN

1U_6.3V_K_X5R_0201
BF11 1 BF14
SDA IFPD_AUX_SDA_N GPU_EDP_AUX GPU_EDP_AUX# 57 TXD0 IFPE_L2_N GPU_DPC_TX2_DP GPU_DPC_TX2_DN 43

CV479

OPT@
BE11 V1 0 TXD0 BE14
SCL IFPD_AUX_SCL GPU_EDP_AUX 57 IFPE_L2 GPU_DPC_TX2_DP 43
BF15 GPU_DPC_TX1_DN
TXD1 IFPE_L1_N GPU_DPC_TX1_DN 43
BM14 GPU_EDP_TX3- 2 BG15 GPU_DPC_TX1_DP
TXC GPU_EDP_TX3- 57 TXD1 GPU_DPC_TX1_DP 43
IFPD_L3_N GPU_EDP_TX3+ IFPE_L1
TXC IFPD_L3
BM15
GPU_EDP_TX3+ 57
IFPE
BG17 GPU_DPC_TX0_DN
TXD2 IFPE_L0_N GPU_DPC_TX0_DN 43
BL15 GPU_EDP_TX2- BH17 GPU_DPC_TX0_DP
TXD0 IFPD_L2_N GPU_EDP_TX2- 57 TXD2 IFPE_L0 GPU_DPC_TX0_DP 43
BK15 GPU_EDP_TX2+
TXD0 IFPD_L2 GPU_EDP_TX2+ 57 +1.0VGS
IFPD
TXD1 BK17 GPU_EDP_TX1- Mini DP Change to IFPE from IFPF
IFPD_L1_N BL17 GPU_EDP_TX1+ GPU_EDP_TX1- 57 1 2 0_0603_5% +IFPE_IOVDD BC21
TXD1 RV307
IFPD_L1 GPU_EDP_TX1+ 57 IFP_IOVDD_9
BC23
BM17 GPU_EDP_TX0- IFP_IOVDD_10
TXD2 GPU_EDP_TX0- 57

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
IFPD_L0_N BM18 GPU_EDP_TX0+
TXD2 IFPD_L0 GPU_EDP_TX0+ 57 1 1 1 1
+1.0VGS

@
OPT@

OPT@

OPT@
4.7U_0603_6.3V6K
V1 0 N18E-FCBGA2228_BGA2228 GPU_DPC_AUX_DN RV112 1 OPT@ 2 100K_0402_5%
RV340 1 2 0_0603_5% +IFPD_IOVDD BC18 Modify by grace 1 /
IFP_IOVDD_7 2 2 2 2 @
BC20 GPU_DPC_AUX_DP RV113 1 OPT@ 2 100K_0402_5%
IFP_IOVDD_8

CV72

CV73
CV557

CV486
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1
@
OPT@

OPT@

N18E-FCBGA2228_BGA2228
4.7U_0603_6.3V6K

@
near GPU under GPU
2 2 2
CV556

CV224

CV225

near GPU under GPU

B B

UV1R
?
?
COMMON
6/22 IFPF/USB-C

USB-C DP

10K_0402_5% 1 OPT@ 2 RV610 USB_DVDD_12 BB15 BM9

USB_DVDD_1 SBU2 IFPF_AUX_SDA_N
BC15 SBU1
BM8
USB_DVDD_2 IFPF_AUX_SCL

RX1
BK11
IFPF_L3_N BL11
RX1 IFPF_L3
BM11
TX1 IFPF_L2_N
TX1
BM12
IFPF_L2

TX2
BL12
IFPF_L1_N BK12
USB_HVDD_12 TX2 IFPF_L1
+1.8VS_AON 10K_0402_5% 1 OPT@ 2 RV611 AW10
AW11 USB_HVDD_1 BK14
USB_HVDD_2 RX2 IFPF_L0_N
RX2
BL14
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

AW9 IFPF_L0
10U_0603_6.3V6M
22U_0603_6.3V6-M

4.7U_0603_6.3V6K

USB_PLL_HVDD
1 1 1 1 1 1 1
BA1
CV560

CV559

CV558
CV1107

CV1108

CV1110

CV1109

USB_L0_N BA2
USB_L0
@

@
OPT@

OPT@

OPT@

2 2 2 2 2 2 2 BA7
USB_L1_N BA8
under GPU USB_L1
near GPU
10K_0402_5% 1 OPT@ 2 RV612 USB_VDDP BE12
USB_VDDP

+1.8VS_AON

A BB8 USB_SCL RV1202 1 OPT@ 2 2.2K_0402_5% A

USB_SCL BB7 USB_SDA RV1201 1 OPT@ 2 2.2K_0402_5%
USB_SDA
2.49K_0402_1% 2 @ 1 RV613 USB_TERMP0 BG6
USB_TERMP0
2.49K_0402_1% 2 @ 1 RV614 USB_TERMP1 BH6
USB_TERMP1
1K_0402_1% 2 @ 1 RV615 USB_RBIAS BA6
USB_RBIAS
IFPF/USB-C
not support type-c
N18E-FCBGA2228_BGA2228
@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_DIGITAL OUT I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 2.0

Date: Friday, March 22, 2019 Sheet 25 of 77

5 4 3 2 1
 5 4 3 2 1

UV1C
UV1B ?
? ?
? COMMON
COMMON 3/22 FBB
35,36 FBB_D[0..63] FBB_CMD[0..33] 35,36
2/22 FBA
33,34 FBA_D[0..63] FBA_CMD[0..33] 33,34 FBB_D0 H32 B35 FBB_CMD0
FBA_D0 U51 Y51 FBA_CMD0 FBB_D1 D32 FBB_D0 FBB_CMD0 A35 FBB_CMD1
FBA_D1 U48 FBA_D0 FBA_CMD0 Y52 FBA_CMD1 FBB_D2 A33 FBB_D1 FBB_CMD1 D35 FBB_CMD2
FBA_D2 U50 FBA_D1 FBA_CMD1 Y49 FBA_CMD2 FBB_D3 B32 FBB_D2 FBB_CMD2 A36 FBB_CMD3
FBA_D3 U49 FBA_D2 FBA_CMD2 AA52 FBA_CMD3 FBB_D4 E32 FBB_D3 FBB_CMD3 B36 FBB_CMD4
FBA_D4 R51 FBA_D3 FBA_CMD3 AA51 FBA_CMD4 FBB_D5 G32 FBB_D4 FBB_CMD4 C36 FBB_CMD5
FBA_D5 R50 FBA_D4 FBA_CMD4 AA50 FBA_CMD5 FBB_D6 J30 FBB_D5 FBB_CMD5 C38 FBB_CMD6
FBA_D6 R47 FBA_D5 FBA_CMD5 AC50 FBA_CMD6 FBB_D7 F32 FBB_D6 FBB_CMD6 B38 FBB_CMD7
FBA_D7 U46 FBA_D6 FBA_CMD6 AC51 FBA_CMD7 FBB_D8 H36 FBB_D7 FBB_CMD7 A38 FBB_CMD8
FBA_D8 V46 FBA_D7 FBA_CMD7 AC52 FBA_CMD8 FBB_D9 G36 FBB_D8 FBB_CMD8 D38 FBB_CMD9
FBA_D9 Y45 FBA_D8 FBA_CMD8 AC49 FBA_CMD9 FBB_D10 J36 FBB_D9 FBB_CMD9 A39 FBB_CMD10
FBA_D10 Y47 FBA_D9 FBA_CMD9 AD52 FBA_CMD10 FBB_D11 F36 FBB_D10 FBB_CMD10 B39 FBB_CMD11
FBA_D11 Y46 FBA_D10 FBA_CMD10 AD51 FBA_CMD11 FBB_D12 F33 FBB_D11 FBB_CMD11 C39 FBB_CMD12
D D
FBA_D12 V50 FBA_D11 FBA_CMD11 AD50 FBA_CMD12 FBB_D13 D33 FBB_D12 FBB_CMD12 C41 FBB_CMD13
FBA_D13 V47 FBA_D12 FBA_CMD12 AF50 FBA_CMD13 FBB_D14 J32 FBB_D13 FBB_CMD13 B41 FBB_CMD14
FBA_D14 U52 FBA_D13 FBA_CMD13 AF51 FBA_CMD14 GDDR6 CMD Mapping FBB_D15 G33 FBB_D14 FBB_CMD14 A41 FBB_CMD15
x16 Mode
FBA_D15 V51 FBA_D14 FBA_CMD14 AF52 FBA_CMD15 Lower 0..31 Upper 32..63 FBB_D16 E45 FBB_D15 FBB_CMD15 B49 FBB_CMD16
FBA_D16 AJ44 FBA_D15 FBA_CMD15 AN50 FBA_CMD16 FBB_D17 D45 FBB_D16 FBB_CMD16 A49 FBB_CMD17
DRAM1 DRAM2
FBA_D17 AG48 FBA_D16 FBA_CMD16 AN51 FBA_CMD17 FBB_D18 F45 FBB_D17 FBB_CMD17 A48 FBB_CMD18
CHA-Byte 0,1 CHA-Byte 4,5
FBA_D18 AJ45 FBA_D17 FBA_CMD17 AN52 FBA_CMD18 FBB_D19 G45 FBB_D18 FBB_CMD18 D47 FBB_CMD19
FBA_D19 AG49 FBA_D18 FBA_CMD18 AM49 FBA_CMD19 FBB_D20 D42 FBB_D19 FBB_CMD19 A47 FBB_CMD20
CA0_A CMD0 CMD20
FBA_D20 AF46 FBA_D19 FBA_CMD19 AM52 FBA_CMD20 CA1_A CMD9 CMD28 FBB_D21 E42 FBB_D20 FBB_CMD20 B47 FBB_CMD21
FBA_D21 AF47 FBA_D20 FBA_CMD20 AM51 FBA_CMD21 FBB_D22 F42 FBB_D21 FBB_CMD21 C47 FBB_CMD22
CA2_A CMD8 CMD21
FBA_D22 AF48 FBA_D21 FBA_CMD21 AM50 FBA_CMD22 FBB_D23 H41 FBB_D22 FBB_CMD22 C45 FBB_CMD23
CA3_A CMD32 CMD29
FBA_D23 AD47 FBA_D22 FBA_CMD22 AK50 FBA_CMD23 FBB_D24 E41 FBB_D23 FBB_CMD23 B45 FBB_CMD24
CA4_A CMD7 CMD23
FBA_D24 AD49 FBA_D23 FBA_CMD23 AK51 FBA_CMD24 FBB_D25 F39 FBB_D24 FBB_CMD24 A45 FBB_CMD25
CA5_A CMD11 CMD27
FBA_D25 AD48 FBA_D24 FBA_CMD24 AK52 FBA_CMD25 CA6_A CMD15 CMD30 FBB_D26 E39 FBB_D25 FBB_CMD25 D44 FBB_CMD26
FBA_D26 AC46 FBA_D25 FBA_CMD25 AJ49 FBA_CMD26 FBB_D27 D39 FBB_D26 FBB_CMD26 A44 FBB_CMD27
CA7_A CMD14 CMD31
FBA_D27 AC47 FBA_D26 FBA_CMD26 AJ52 FBA_CMD27 FBB_D28 F38 FBB_D27 FBB_CMD27 B44 FBB_CMD28
CA8_A CMD3 CMD19
FBA_D28 AA47 FBA_D27 FBA_CMD27 AJ51 FBA_CMD28 FBB_D29 E38 FBB_D28 FBB_CMD28 C44 FBB_CMD29
CA9_A CMD1 CMD17
FBA_D29 AA46 FBA_D28 FBA_CMD28 AJ50 FBA_CMD29 FBB_D30 D36 FBB_D29 FBB_CMD29 C42 FBB_CMD30
CABI_A CMD6 CMD22
FBA_D30 AA45 FBA_D29 FBA_CMD29 AG50 FBA_CMD30 CKE_A CMD10 CMD26 FBB_D31 E36 FBB_D30 FBB_CMD30 B42 FBB_CMD31 FBVDDQ
FBA_D31 Y44 FBA_D30 FBA_CMD30 AG51 FBA_CMD31 FBVDDQ FBB_D32 M50 FBB_D31 FBB_CMD31 D41 FBB_CMD32
FBA_D32 AW51 FBA_D31 FBA_CMD31 AF49 FBA_CMD32 FBB_D33 P48 FBB_D32 FBB_CMD32 A42 FBB_CMD33
CHB-Byte 2,3 CHB-Byte 6,7
FBA_D33 BA52 FBA_D32 FBA_CMD32 AG52 FBA_CMD33 FBB_D34 M51 FBB_D33 FBB_CMD33 C35 FBB_DEBUG0 1 2
CA0_B CMD4 CMD16
FBA_D34 AW50 FBA_D33 FBA_CMD33 Y50 FBA_DEBUG0 1 2 FBB_D35 M49 FBB_D34 FBB_CMD34 B50 FBB_DEBUG1 1 2 RV83 @ 60.4_0402_1%
CA1_B CMD12 CMD25
FBA_D35 BA51 FBA_D34 FBA_CMD34 AR50 FBA_DEBUG1 1 2 RV81 @ 60.4_0402_1% FBB_D36 P47 FBB_D35 FBB_CMD35 RV84 @ 60.4_0402_1%
CA2_B CMD5 CMD24
FBA_D36 BA50 FBA_D35 FBA_CMD35 RV82 @ 60.4_0402_1% FBB_D37 P52 FBB_D36
CA3_B CMD13 CMD33
FBA_D37 BB50 FBA_D36 FBB_D38 R46 FBB_D37
CA4_B CMD7 CMD23
FBA_D38 BA49 FBA_D37 FBB_D39 P46 FBB_D38 J35
CA5_B CMD11 CMD27
FBA_D39 AW49 FBA_D38 AA44 FBB_D40 L50 FBB_D39 FBB_DBG_RFU1 J41
CA6_B CMD15 CMD30
FBA_D40 AV48 FBA_D39 FBA_DBG_RFU1 AN44 CA7_B CMD14 CMD31 FBB_D41 L51 FBB_D40 FBB_DBG_RFU2
FBA_D41 AT49 FBA_D40 FBA_DBG_RFU2 FBB_D42 L52 FBB_D41
CA8_B CMD3 CMD19
FBA_D42 AT47 FBA_D41 FBB_D43 L49 FBB_D42
CA9_B CMD1 CMD17
FBA_D43 AT48 FBA_D42 FBB_D44 M46 FBB_D43 H42
CABI_B CMD6 CMD22
FBA_D44 AT46 FBA_D43 AG45 FBA_CLK0 FBB_D45 L47 FBB_D44 FBB_CLK0 G42 FBB_CLK0 35
CKE_B CMD10 CMD26
FBA_D45 AV51 FBA_D44 FBA_CLK0 AG46 FBA_CLK0# FBA_CLK0 33 FBB_D46 M48 FBB_D45 FBB_CLK0_N F47 FBB_CLK0# 35
FBA_D46 AV52 FBA_D45 FBA_CLK0_N AK46 FBA_CLK1 FBA_CLK0# 33 FBB_D47 M47 FBB_D46 FBB_CLK1 E47 FBB_CLK1 36
RESET* CMD2 CMD18
FBA_D47 AV49 FBA_D46 FBA_CLK1 AK45 FBA_CLK1# FBA_CLK1 34 FBB_D48 D48 FBB_D47 FBB_CLK1_N FBB_CLK1# 36
FBA_D48 AJ48 FBA_D47 FBA_CLK1_N FBA_CLK1# 34 FBB_D49 C50 FBB_D48
FBA_D49 AJ46 FBA_D48 FBB_D50 C48 FBB_D49
FBA_D50 AJ47 FBA_D49 FBB_D51 C49 FBB_D50
FBA_D51 AK49 FBA_D50 FBB_D52 E49 FBB_D51
FBA_D52 AM47 FBA_D51 FBB_D53 E50 FBB_D52
C C
FBA_D53 AM46 FBA_D52 FBB_D54 F49 FBB_D53
FBA_D54 AN48 FBA_D53 FBB_D55 F48 FBB_D54
FBA_D55 AN49 FBA_D54 FBB_D56 F50 FBB_D55 J33 FBB_WCK01
FBA_D56 AM44 FBA_D55 U45 FBA_WCK01 FBB_D57 D52 FBB_D56 FBB_WCK01 H33 FBB_WCK01_N FBB_WCK01 35
FBA_D57 AM45 FBA_D56 FBA_WCK01 U44 FBA_WCK01_N FBA_WCK01 33 FBB_D58 J50 FBB_D57 FBB_WCK01_N G35 FBB_WCKB01 FBB_WCK01_N 35
FBA_D58 AN45 FBA_D57 FBA_WCK01_N V45 FBA_WCKB01 FBA_WCK01_N 33 FBB_D59 H48 FBB_D58 FBB_WCKB01 H35 FBB_WCKB01_N FBB_WCKB01 35
FBA_D59 AN46 FBA_D58 FBA_WCKB01 V44 FBA_WCKB01_N FBA_WCKB01 33 FBB_D60 H51 FBB_D59 FBB_WCKB01_N J39 FBB_WCK23 FBB_WCKB01_N 35
FBA_D60 AR48 FBA_D59 FBA_WCKB01_N AC45 FBA_WCK23 FBA_WCKB01_N 33 FBB_D61 J51 FBB_D60 FBB_WCK23 H39 FBB_WCK23_N FBB_WCK23 35
FBA_D61 AN47 FBA_D60 FBA_WCK23 AC44 FBA_WCK23_N FBA_WCK23 33 FBB_D62 H49 FBB_D61 FBB_WCK23_N F41 FBB_WCKB23 FBB_WCK23_N 35
FBA_D62 AR47 FBA_D61 FBA_WCK23_N AD46 FBA_WCKB23 FBA_WCK23_N 33 FBB_D63 H52 FBB_D62 FBB_WCKB23 G41 FBB_WCKB23_N FBB_WCKB23 35
FBA_D63 AR46 FBA_D62 FBA_WCKB23 AD45 FBA_WCKB23_N FBA_WCKB23 33 FBB_D63 FBB_WCKB23_N L46 FBB_WCK45 FBB_WCKB23_N 35
FBA_D63 FBA_WCKB23_N AV47 FBA_WCK45 FBA_WCKB23_N 33 FBB_WCK45 L45 FBB_WCK45_N FBB_WCK45 36
FBA_WCK45 AV46 FBA_WCK45_N FBA_WCK45 34 FBB_DBI0# C32 FBB_WCK45_N M44 FBB_WCKB45 FBB_WCK45_N 36
FBA_DBI0# U47 FBA_WCK45_N AW48 FBA_WCKB45 FBA_WCK45_N 34 35 FBB_DBI0# FBB_DBI1# E33 FBB_DQM0 FBB_WCKB45 M45 FBB_WCKB45_N FBB_WCKB45 36
33 FBA_DBI0# FBA_DBI1# Y48 FBA_DQM0 FBA_WCKB45 AW47 FBA_WCKB45_N FBA_WCKB45 34 35 FBB_DBI1# FBB_DBI2# E44 FBB_DQM1 FBB_WCKB45_N H47 FBB_WCK67 FBB_WCKB45_N 36
33 FBA_DBI1# FBA_DBI2# AG47 FBA_DQM1 FBA_WCKB45_N AR45 FBA_WCK67 FBA_WCKB45_N 34 35 FBB_DBI2# FBB_DBI3# G39 FBB_DQM2 FBB_WCK67 H46 FBB_WCK67_N FBB_WCK67 36
33 FBA_DBI2# FBA_DBI3# AC48 FBA_DQM2 FBA_WCK67 AR44 FBA_WCK67_N FBA_WCK67 34 35 FBB_DBI3# FBB_DBI4# P49 FBB_DQM3 FBB_WCK67_N J47 FBB_WCKB67 FBB_WCK67_N 36
33 FBA_DBI3# FBA_DBI4# BB51 FBA_DQM3 FBA_WCK67_N AT45 FBA_WCKB67 FBA_WCK67_N 34 36 FBB_DBI4# FBB_DBI5# L48 FBB_DQM4 FBB_WCKB67 J46 FBB_WCKB67_N FBB_WCKB67 36
34 FBA_DBI4# FBA_DBI5# AV50 FBA_DQM4 FBA_WCKB67 AT44 FBA_WCKB67_N FBA_WCKB67 34 36 FBB_DBI5# FBB_DBI6# D50 FBB_DQM5 FBB_WCKB67_N FBB_WCKB67_N 36
34 FBA_DBI5# FBA_DBI6# AM48 FBA_DQM5 FBA_WCKB67_N FBA_WCKB67_N 34 36 FBB_DBI6# FBB_DBI7# H50 FBB_DQM6
34 FBA_DBI6# FBA_DBI7# AR49 FBA_DQM6 36 FBB_DBI7# FBB_DQM7
34 FBA_DBI7# FBA_DQM7
FBB_EDC0 B33
FBA_EDC0 R48 35 FBB_EDC0 FBB_EDC1 E35 FBB_DQS_WP0
33 FBA_EDC0 FBA_EDC1 V48 FBA_DQS_WP0 35 FBB_EDC1 FBB_EDC2 G44 FBB_DQS_WP1
33 FBA_EDC1 FBA_EDC2 AF44 FBA_DQS_WP1 35 FBB_EDC2 FBB_EDC3 H38 FBB_DQS_WP2
33 FBA_EDC2 FBA_EDC3 AA48 FBA_DQS_WP2 35 FBB_EDC3 FBB_EDC4 P50 FBB_DQS_WP3 +FB_PLLAVDD
33 FBA_EDC3 FBA_EDC4 BB52 FBA_DQS_WP3 +FB_PLLAVDD 36 FBB_EDC4 FBB_EDC5 J48 FBB_DQS_WP4
34 FBA_EDC4 FBA_EDC5 AT50 FBA_DQS_WP4 36 FBB_EDC5 FBB_EDC6 D51 FBB_DQS_WP5
34 FBA_EDC5 FBA_EDC6 AK48 FBA_DQS_WP5 36 FBB_EDC6 FBB_EDC7 F51 FBB_DQS_WP6 L38
34 FBA_EDC6 FBA_EDC7 AR51 FBA_DQS_WP6 AN42 36 FBB_EDC7 FBB_DQS_WP7 FBB_PLL_AVDD
34 FBA_EDC7 FBA_DQS_WP7 FBA_PLL_AVDD
Y16 1
W45 Y17 GND_702 CV477
GND_694 1 GND_703
W47 CV473 Y18 1U_6.3V_K_X5R_0201
W49 GND_695 1U_6.3V_K_X5R_0201 Y19 GND_704 OPT@
W51 GND_696 OPT@ Y20 GND_705 2
W6 GND_697 2 Y21 GND_706
W8 GND_698 Y22 GND_707
Y14 GND_699 Y23 GND_708
B Y15 GND_700 GND_709 B
GND_701
Under GPU
+FB_PLLAVDD Under GPU
AF42
L29 FB_REFPLL_AVDD0
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

FB_REFPLL_AVDD1
1 1 1 1 1
22U_0603_6.3V6-M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

N18E-FCBGA2228_BGA2228
N18E-FCBGA2228_BGA2228 @
2 2 2 2 2 @
OPT@

OPT@

OPT@

OPT@

OPT@
CV64
CV475

CV474

CV562

CV476

Near GPU Under GPU

FBVDDQ FBVDDQ

1
CKE_A CKE_A
RV57 RV75 RV85 RV86
30ohms (ESR=0.01) Bead 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
OPT@ OPT@ OPT@ OPT@
P/N;SM01000M300

2
+1.8VS_VGA N18 change +FB_PLLAVDD FBA_CMD10 FBB_CMD10
FBA_CMD26 FBB_CMD26

FBA_CMD2 FBB_CMD2
1 2 +FB_PLLAVDD FBA_CMD18 FBB_CMD18
LV1
HCB1608KF-300T60_2P
OPT@

1
Place close to BGA RESET RV76 RV80 RESET RV87 RV88
10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
OPT@ OPT@ OPT@ OPT@
A A

2
Security Classification LC Future Center Secret Data Title
Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_VRAM A/B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2 Y540 2.0

Date: Friday, March 22, 2019 Sheet 26 of 77

5 4 3 2 1
 5 4 3 2 1

UV1D UV1E
? ?
? ?
COMMON COMMON
4/22 FBC 5/22 FBD
37,38 FBC_D[0..63] FBC_CMD[0..33] 37,38
FBC_D0 C6 C11 FBC_CMD0 AK8 AD2
FBC_D1 D6 FBC_D0 FBC_CMD0 B11 FBC_CMD1 AK4 FBD_D0 FBD_CMD0 AD1
FBC_D2 A6 FBC_D1 FBC_CMD1 A11 FBC_CMD2 AK2 FBD_D1 FBD_CMD1 AD4
FBC_D3 B6 FBC_D2 FBC_CMD2 D11 FBC_CMD3 AK3 FBD_D2 FBD_CMD2 AC1
FBC_D4 B4 FBC_D3 FBC_CMD3 A12 FBC_CMD4 AK5 FBD_D3 FBD_CMD3 AC2
D D
FBC_D5 A4 FBC_D4 FBC_CMD4 B12 FBC_CMD5 GDDR6 CMD Mapping AK6 FBD_D4 FBD_CMD4 AC3
x16 Mode
FBC_D6 B3 FBC_D5 FBC_CMD5 C12 FBC_CMD6 AK9 FBD_D5 FBD_CMD5 AA3
Lower 0..31 Upper 32..63
FBC_D7 C4 FBC_D6 FBC_CMD6 C14 FBC_CMD7 AK7 FBD_D6 FBD_CMD6 AA2
DRAM1 DRAM2
FBC_D8 D9 FBC_D7 FBC_CMD7 B14 FBC_CMD8 AG4 FBD_D7 FBD_CMD7 AA1
CHA-Byte 0,1 CHA-Byte 4,5
FBC_D9 C9 FBC_D8 FBC_CMD8 A14 FBC_CMD9 AF9 FBD_D8 FBD_CMD8 AA4
FBC_D10 E9 FBC_D9 FBC_CMD9 D14 FBC_CMD10 AG6 FBD_D9 FBD_CMD9 Y1
CA0_A CMD0 CMD20
FBC_D11 B9 FBC_D10 FBC_CMD10 A15 FBC_CMD11 AG7 FBD_D10 FBD_CMD10 Y2
CA1_A CMD9 CMD28
FBC_D12 B8 FBC_D11 FBC_CMD11 B15 FBC_CMD12 AJ4 FBD_D11 FBD_CMD11 Y3
CA2_A CMD8 CMD21
FBC_D13 A8 FBC_D12 FBC_CMD12 C15 FBC_CMD13 AJ5 FBD_D12 FBD_CMD12 V3
CA3_A CMD32 CMD29
FBC_D14 F6 FBC_D13 FBC_CMD13 C17 FBC_CMD14 AJ6 FBD_D13 FBD_CMD13 V2
CA4_A CMD7 CMD23
FBC_D15 E6 FBC_D14 FBC_CMD14 B17 FBC_CMD15 AG5 FBD_D14 FBD_CMD14 V1
CA5_A CMD11 CMD27
FBC_D16 F18 FBC_D15 FBC_CMD15 B24 FBC_CMD16 Y6 FBD_D15 FBD_CMD15 L3
CA6_A CMD15 CMD30
FBC_D17 G18 FBC_D16 FBC_CMD16 A24 FBC_CMD17 Y5 FBD_D16 FBD_CMD16 L2
CA7_A CMD14 CMD31
FBC_D18 E18 FBC_D17 FBC_CMD17 D23 FBC_CMD18 CA8_A CMD3 CMD19 V5 FBD_D17 FBD_CMD17 L1
FBC_D19 H18 FBC_D18 FBC_CMD18 A23 FBC_CMD19 Y4 FBD_D18 FBD_CMD18 M4
CA9_A CMD1 CMD17
FBC_D20 D15 FBC_D19 FBC_CMD19 B23 FBC_CMD20 AA6 FBD_D19 FBD_CMD19 M1
CABI_A CMD6 CMD22
FBC_D21 E15 FBC_D20 FBC_CMD20 C23 FBC_CMD21 AA5 FBD_D20 FBD_CMD20 M2
CKE_A CMD10 CMD26
FBC_D22 G17 FBC_D21 FBC_CMD21 C21 FBC_CMD22 AC5 FBD_D21 FBD_CMD21 M3
FBC_D23 H17 FBC_D22 FBC_CMD22 B21 FBC_CMD23 CHB-Byte 2,3 CHB-Byte 6,7 AC4 FBD_D22 FBD_CMD22 P3
FBC_D24 J15 FBC_D23 FBC_CMD23 A21 FBC_CMD24 AD7 FBD_D23 FBD_CMD23 P2
CA0_B CMD4 CMD16
FBC_D25 H15 FBC_D24 FBC_CMD24 D20 FBC_CMD25 AC6 FBD_D24 FBD_CMD24 P1
CA1_B CMD12 CMD25
FBC_D26 E14 FBC_D25 FBC_CMD25 A20 FBC_CMD26 AF6 FBD_D25 FBD_CMD25 R4
CA2_B CMD5 CMD24
FBC_D27 F14 FBC_D26 FBC_CMD26 B20 FBC_CMD27 AD6 FBD_D26 FBD_CMD26 R1
CA3_B CMD13 CMD33
FBC_D28 H11 FBC_D27 FBC_CMD27 C20 FBC_CMD28 CA4_B CMD7 CMD23 AF7 FBD_D27 FBD_CMD27 R2
FBC_D29 G11 FBC_D28 FBC_CMD28 C18 FBC_CMD29 AF8 FBD_D28 FBD_CMD28 R3
CA5_B CMD11 CMD27
FBC_D30 F11 FBC_D29 FBC_CMD29 B18 FBC_CMD30 AF2 FBD_D29 FBD_CMD29 U3
CA6_B CMD15 CMD30
FBC_D31 E11 FBC_D30 FBC_CMD30 A18 FBC_CMD31 FBVDDQ AF3 FBD_D30 FBD_CMD30 U2
CA7_B CMD14 CMD31
FBC_D32 J29 FBC_D31 FBC_CMD31 A17 FBC_CMD32 F4 FBD_D31 FBD_CMD31 V4
CA8_B CMD3 CMD19
FBC_D33 F30 FBC_D32 FBC_CMD32 D17 FBC_CMD33 E1 FBD_D32 FBD_CMD32 U1
CA9_B CMD1 CMD17
FBC_D34 H29 FBC_D33 FBC_CMD33 A9 FBC_DEBUG0 1 2 F3 FBD_D33 FBD_CMD33 AD3
CABI_B CMD6 CMD22
FBC_D35 G30 FBC_D34 FBC_CMD34 C24 FBC_DEBUG1 1 2 RV110 @ 60.4_0402_1% F5 FBD_D34 FBD_CMD34 J3
CKE_B CMD10 CMD26
FBC_D36 B30 FBC_D35 FBC_CMD35 RV111 @ 60.4_0402_1% D2 FBD_D35 FBD_CMD35
FBC_D37 A30 FBC_D36 D1 FBD_D36
RESET* CMD2 CMD18
FBC_D38 H30 FBC_D37 C3 FBD_D37
FBC_D39 C30 FBC_D38 J14 C2 FBD_D38 AC9
FBC_D40 D27 FBC_D39 FBC_DBG_RFU1 J23 J5 FBD_D39 FBD_DBG_RFU1 P9
FBC_D41 J26 FBC_D40 FBC_DBG_RFU2 J4 FBD_D40 FBD_DBG_RFU2
FBC_D42 F27 FBC_D41 L8 FBD_D41
FBC_D43 G27 FBC_D42 J2 FBD_D42
FBC_D44 C27 FBC_D43 G15 FBC_CLK0 F1 FBD_D43 Y8
FBC_D45 B27 FBC_D44 FBC_CLK0 F15 FBC_CLK0# FBC_CLK0 37 F2 FBD_D44 FBD_CLK0 Y7
C C
FBC_D46 A27 FBC_D45 FBC_CLK0_N H21 FBC_CLK1 FBC_CLK0# 37 H4 FBD_D45 FBD_CLK0_N R8
FBC_D47 G29 FBC_D46 FBC_CLK1 J21 FBC_CLK1# FBC_CLK1 38 H5 FBD_D46 FBD_CLK1 R7
FBC_D48 H20 FBC_D47 FBC_CLK1_N FBC_CLK1# 38 V7 FBD_D47 FBD_CLK1_N
FBC_D49 D18 FBC_D48 V8 FBD_D48
FBC_D50 G20 FBC_D49 V6 FBD_D49
FBC_D51 E20 FBC_D50 V9 FBD_D50
FBC_D52 F23 FBC_D51 U4 FBD_D51
FBC_D53 E21 FBC_D52 R5 FBD_D52
FBC_D54 D21 FBC_D53 R6 FBD_D53
FBC_D55 E23 FBC_D54 U8 FBD_D54
FBC_D56 G24 FBC_D55 F8 FBC_WCK01 P6 FBD_D55 AJ8
FBC_D57 H26 FBC_D56 FBC_WCK01 G8 FBC_WCK01_N FBC_WCK01 37 R9 FBD_D56 FBD_WCK01 AJ7
FBC_D58 F24 FBC_D57 FBC_WCK01_N G9 FBC_WCKB01 FBC_WCK01_N 37 P4 FBD_D57 FBD_WCK01_N AG8
FBC_D59 G26 FBC_D58 FBC_WCKB01 F9 FBC_WCKB01_N FBC_WCKB01 37 P5 FBD_D58 FBD_WCKB01 AG9
FBC_D60 F26 FBC_D59 FBC_WCKB01_N H12 FBC_WCK23 FBC_WCKB01_N 37 L7 FBD_D59 FBD_WCKB01_N AD8
FBC_D61 D26 FBC_D60 FBC_WCK23 G12 FBC_WCK23_N FBC_WCK23 37 L6 FBD_D60 FBD_WCK23 AD9
FBC_D62 B26 FBC_D61 FBC_WCK23_N G14 FBC_WCKB23 FBC_WCK23_N 37 L4 FBD_D61 FBD_WCK23_N AC7
FBC_D63 C26 FBC_D62 FBC_WCKB23 H14 FBC_WCKB23_N FBC_WCKB23 37 L5 FBD_D62 FBD_WCKB23 AC8
FBC_D63 FBC_WCKB23_N J27 FBC_WCK45 FBC_WCKB23_N 37 FBD_D63 FBD_WCKB23_N J6
FBC_WCK45 H27 FBC_WCK45_N FBC_WCK45 38 FBD_WCK45 J7
FBC_DBI0# A5 FBC_WCK45_N E29 FBC_WCKB45 FBC_WCK45_N 38 AJ1 FBD_WCK45_N H7
37 FBC_DBI0# FBC_DBI1# C8 FBC_DQM0 FBC_WCKB45 F29 FBC_WCKB45_N FBC_WCKB45 38 AG1 FBD_DQM0 FBD_WCKB45 H6
37 FBC_DBI1# FBC_DBI2# J18 FBC_DQM1 FBC_WCKB45_N G23 FBC_WCK67 FBC_WCKB45_N 38 AA7 FBD_DQM1 FBD_WCKB45_N P8
37 FBC_DBI2# FBC_DBI3# F12 FBC_DQM2 FBC_WCK67 H23 FBC_WCK67_N FBC_WCK67 38 AD5 FBD_DQM2 FBD_WCK67 P7
37 FBC_DBI3# FBC_DBI4# D29 FBC_DQM3 FBC_WCK67_N H24 FBC_WCKB67 FBC_WCK67_N 38 D3 FBD_DQM3 FBD_WCK67_N M7
38 FBC_DBI4# FBC_DBI5# E27 FBC_DQM4 FBC_WCKB67 J24 FBC_WCKB67_N FBC_WCKB67 38 H3 FBD_DQM4 FBD_WCKB67 M8
38 FBC_DBI5# FBC_DBI6# F20 FBC_DQM5 FBC_WCKB67_N FBC_WCKB67_N 38 U5 FBD_DQM5 FBD_WCKB67_N
38 FBC_DBI6# FBC_DBI7# E26 FBC_DQM6 M9 FBD_DQM6
38 FBC_DBI7# FBC_DQM7 FBD_DQM7

FBC_EDC0 D5 AJ3
37 FBC_EDC0 FBC_EDC1 D8 FBC_DQS_WP0 AG2 FBD_DQS_WP0
37 FBC_EDC1 FBC_EDC2 E17 FBC_DQS_WP1 AA9 FBD_DQS_WP1
37 FBC_EDC2 FBC_EDC3 E12 FBC_DQS_WP2 AF4 FBD_DQS_WP2
37 FBC_EDC3 FBC_EDC4 E30 FBC_DQS_WP3 +FB_PLLAVDD E3 FBD_DQS_WP3 +FB_PLLAVDD
38 FBC_EDC4 FBC_EDC5 B29 FBC_DQS_WP4 FBVDDQ H2 FBD_DQS_WP4
38 FBC_EDC5 FBC_EDC6 G21 FBC_DQS_WP5 U6 FBD_DQS_WP5
38 FBC_EDC6 FBC_EDC7 E24 FBC_DQS_WP6 L17 M5 FBD_DQS_WP6 V11
38 FBC_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD FBD_DQS_WP7 FBD_PLL_AVDD

1
CKE_A
B Y24 RV91 RV92 Y32 B
Y25 GND_710 10K_0402_1% 10K_0402_1% Y33 GND_718
GND_711 1 GND_719 1
Y26 CV478 OPT@ OPT@ Y34 CV481
Y27 GND_712 1U_6.3V_K_X5R_0201 Y35 GND_720 1U_6.3V_K_X5R_0201

2
Y28 GND_713 OPT@ FBC_CMD10 Y36 GND_721 OPT@
Y29 GND_714 2 FBC_CMD26 Y37 GND_722 2
Y30 GND_715 Y38 GND_723
Y31 GND_716 FBC_CMD2 Y39 GND_724
GND_717 FBC_CMD18 GND_725

Under GPU Under GPU

N18E-G3

1
RESET RV95 RV96
10K_0402_1% 10K_0402_1% FBD N/A
OPT@ OPT@
N18E-FCBGA2228_BGA2228 N18E-FCBGA2228_BGA2228

2
@ @

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_VRAM C/D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
Y540 2.0

Date: Friday, March 22, 2019 Sheet 27 of 77

5 4 3 2 1
 5 4 3 2 1

UV1S
?
?
COMMON
11/22 NVHS

D AM1 D
NVHS0_RX0 AN1
NVHS0_RX0_N
AN2
NVHS0_RX1 AN3
NVHS0_RX1_N
AR3
NVHS0_RX2 AR2
NVHS0_RX2_N
AR1
NVHS0_RX3 AT1
NVHS0_RX3_N
10K_0402_5% 2 OPT@ 1 RV1194 NVHS_DVDD AT10 AT2
AT9 NVHS_DVDD_1 NVHS0_RX4 AT3
AV10 NVHS_DVDD_2 NVHS0_RX4_N
+1.0VGS AV11 NVHS_DVDD_3 AV3
NVHS_DVDD_4 NVHS0_RX5 AV2
0_0603_5% 1 @ 2 RV1203 NVHS_CVDD AR10 NVHS0_RX5_N
AT11 NVHS_CVDD_1 AV1

1U_6.3V_K_X5R_0201
NVHS_CVDD_2 NVHS0_RX6 AW1
1

1
@ NVHS0_RX6_N
RV1219 AW2
10K_0402_5% NVHS0_RX7 AW3
OPT@ 2 NVHS0_RX7_N

CV1106
AM7
2

NVHS0_TX0 AM8
NVHS0_TX0_N
under GPU AN7
NVHS0_TX1 AN6
NVHS0_TX1_N
10K_0402_5% 2 OPT@ 1 RV1196 NVHS_HVDD AM10 AR6
AM11 NVHS_HVDD_1 NVHS0_TX2 AR5
AN10 NVHS_HVDD_2 NVHS0_TX2_N
AN11 NVHS_HVDD_3 AR7
AR11 NVHS_HVDD_4 NVHS0_TX3 AR8
NVHS_HVDD_5 NVHS0_TX3_N
10K_0402_5% 2 OPT@ 1 RV1197 NVHS_PLL_HVDD AN9 AT7
NVHS_PLL_HVDD NVHS0_TX4 AT6
NVHS0_TX4_N
AV6
NVHS0_TX5 AV5
NVHS0_TX5_N
C C
AV7
NVHS0_TX6 AV8
NVHS0_TX6_N
AW7
NVHS0_TX7 AW6
NVHS0_TX7_N

AM3 AM6
NVHS_TERMP NVHS_REFCLK AM5
NVHS_REFCLK_N

AM2
EXT_REFCLK_SLI

N18E-G3

NVHS RX/TX N/A

N18E-FCBGA2228_BGA2228
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_NVHS I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
A2
Y540 2.0

Date: Friday, March 22, 2019 Sheet 28 of 77

5 4 3 2 1
 5 4 3 2 1

UV1U
+1.8VS_AON +1.8VS_AON
?
?
COMMON
14/22 MISC 2

2
BJ4 ROM_CS# +3VS
ROM_CS_N RV1105
ROM_SI
BK2
BK4
ROM_SI
ROM_SO
10K_0402_5%
OPT@
1
CV443
10U_0402_6.3V6M
1
CV442
.1U_0402_10V6-K Power on/off sequence

2
STRAP0 BL3 ROM_SO BK3 ROM_SCLK @ OPT@ +3VALW RV1164
by Bing 20180315

1
STRAP1 BL4 STRAP0 ROM_SCLK UV10 2 2 10K_0402_5%
STRAP2 BM4 STRAP1 ROM_CS# RV1102 2 OPT@ 1 33_0402_5% ROM_CS#_R 1 8 OPT@
STRAP3 BM5 STRAP2 ROM_SO 2 1 0_0402_5% ROM_SO_R 2 CS# VCC 7
RV1101
STRAP3 DO HOLD#

2
STRAP4 BK5 V1 0 3 6 ROM_SCLK_R RV1103 2 OPT@ 1 33_0402_5% ROM_SCLK +1.8VS_AON RV1165

1
STRAP5 BJ5 STRAP4 4 WP# CLK 5 ROM_SI_R RV1104 2 OPT@ 1 33_0402_5% ROM_SI 10K_0402_5%
STRAP5 GND DI 1V8_MAIN_EN_R
OPT@
1V8_MAIN_EN_R 31
W25Q80EWSNIG_SO8
OPT@

3
BF9 GPU_BUFRST# 1 @ TV4 D
BUFRST_N 5 QV32B

1
G LBSS138DW1T1G_SOT363-6
RV314 RV312 RV316 S OPT@

4
NV RVL 100K_0402_1% 100K_0402_1% 100K_0402_1%
X76@ X76@ X76@

6
D
Vgs(th)≤1.5V

2
STRAP0 1V8_MAIN_EN 2 QV32A
N18E-FCBGA2228_BGA2228 STRAP1 G LBSS138DW1T1G_SOT363-6
@ STRAP2 S OPT@

1
1
1

1
RV1166
RV313 RV309 RV315 100K_0402_5%
100K_0402_1% 100K_0402_1% 100K_0402_1% @

2
X76@ X76@ X76@

2
D D

+1.8VS_AON

DV10
OVERT#_NVEN 1 2 +1.8VS_VGA +3VS
24 OVERT#_NVEN
2

UV1T
RV214
100K_0402_5%
?
?
RAMCFG RB751V-40_SOD323-2
@

1
OPT@ COMMON
12/22 MISC 1 RV116 RV114
1

Internal Thermal Sensor 0_0201_5% 10K_0402_5%

@ OPT@
OVERT# BG5 BJ8 VGA_SMB_CK2 +1.8VS_AON DV8
24 OVERT#

2
OVERT I2CS_SCL BH8 VGA_SMB_DA2 +1.8VS_AON PXS_PWREN RV51 1 2 0_0201_5% 2
I2CS_SDA 19,53 PXS_PWREN 1 NVVDD_EN
1 TS_VREF BF12 1V8_MAIN_EN 2 OPT@ 1 10K_0402_5% 1V8_MAIN_EN_R 1 2 0_0201_5% 3 NVVDD_EN 75
TV5 @ RV18 RV117
TS_VREF BG9 I2CC_SCL

1
I2CC_SCL BH9 I2CC_SDA NVVDD_PSI RV30 2 @ 1 10K_0402_5% LBAT54AWT1G_SOT323-3
I2CC_SDA VGA_ALERT# RV23 1 OPT@ 2 10K_0402_5% OPT@ RV115
VGA_AC_DET_R RV26 2 OPT@ 1 10K_0402_5% 100K_0402_1%
BG8 I2CB_SCL RV22 1 OPT@ 2 2.2K_0402_5% ADC_MUX_SEL RV381 1 OPT@ 2 10K_0402_5% RV220 1 @ 2 0_0201_5% @

1
I2CB_SCL BF8 I2CB_SDA RV25 1 OPT@ 2 2.2K_0402_5%
+1.8VS_AON

2
I2CB_SDA RV322 RV320 RV324
FBVDDQ_SEL RV40 2 @ 1 10K_0402_5% 100K_0402_1% 100K_0402_1% 100K_0402_1%
BJ1 OPT@ @ @
THERMDN FBVDDQ_SEL RV41 2 OPT@ 1 10K_0402_5%

2
BJ2 STRAP3
THERMDP MEM_VREF RV373 2 OPT@ 1 10K_0402_5% STRAP4
STRAP5
NB_FGC6 RV758 2 OPT@ 1 10K_0402_5%
BD6 NVVDD_PWM_VID
NVVDD_PWM_VID

1
GPIO0 BB5 FB_GC6_EN RASTER_SYNC1 RV377 1 OPT@ 2 100K_0402_5%
GPIO1 BD1 GPU_EVENT#_R RV321 RV319 RV323
ADC_IN_P BJ9 GPIO2 BE4 IDLE_IN_SW RV375 1 OPT@ 2 10K_0402_5% 100K_0402_1% 100K_0402_1% 100K_0402_1%
76 ADC_IN_P ADC_IN_N BJ11 ADC_IN GPIO3 BE1 1V8_MAIN_EN @ OPT@ OPT@
76 ADC_IN_N ADC_IN_N GPIO4 GPU_FRAME_LOCK# GPU_EDP_ENBKL +1.8VS_AON +3VS
BG2 RV1291 1 OPT@ 2 100K_0201_5%
GPU_FRAME_LOCK# 39

2
GPIO5 BD2 NVVDD_PSI
modify by grace 1 /
GPIO6 BD7 NVVDD_PSI GPU_EDP_PWM 1 OPT@ 2 100K_0201_5%
RV1289 DV3
GPIO7 BH4 FBVDDQ_SEL GPU_EDP_PWM 57 PXS_PWREN
modify by grace 1 / OPT@ 1 2
GPIO8 BJ3 VGA_ALERT# FBVDDQ_SEL 73 GPU_EDP_ENVDD 1 2 10K_0201_5%
RV1290
GPIO9 VGA_ALERT# 20

2
BD3 MEM_VREF RB751V-40_SOD323-2
1 PAD JTAG_TCK BK24 GPIO10 BH3 MEM_VREF 33,35,37
@ OPT@ RV1169 RV62
TV1 1 PAD JTAG_TMS BL23 JTAG_TCK GPIO11 BE6 VGA_AC_DET_R GPU_EDP_ENVDD 57
@ modify by grace 1 / 10K_0402_5% 8.2K_0402_1%
TV6 1 PAD JTAG_TDI JTAG_TMS GPIO12
BM23 BB1
TV7
@
@ 1 PAD JTAG_TDO BM24 JTAG_TDI GPIO13 BG4 IFPA_HPD
modify by grace 1 / 8
VGA_DEVICE 1V8_MAIN_EN_R
RV1168 1 2 0_0402_5%
@ OPT@
TV8 IFPA_HPD 41

1
JTAG_TRST BL24 JTAG_TDO GPIO14 BG1 DV7
JTAG_TRST_N GPIO15 BE2 1V8_MAIN_EN 1 2 0_0402_5% 2
RV1167 @
GPIO16 BH1 IFPD_HPD 1 RV63 1 2 0_0402_5%
IFPD_HPD 57 1V0_MAIN_EN 24,74
2

GPIO17 BE3 IFPE_HPD modify by grace 1 / NVVDD_PWRGD RV1176 1 2 0_0402_5% 3

IFPE_HPD 43 75 NVVDD_PWRGD

1
RV37 NVJTAG_SEL BK23 GPIO18 BD4 V1 0
10K_0402_5% NVJTAG_SEL GPIO19 BE5 NB_FGC6 LBAT54AWT1G_SOT323-3 RV64
OPT@ GPIO20 BA5 RV4 1 OPT@ 2 10K_0402_5% OPT@ 10K_0402_5%
GPIO21 GPU_EDP_ENBKL 57 +3VS
BB6 modify by grace 1 / +1.8VS_AON @
1

GPIO22 BG3 RASTER_SYNC1

2
RV337 GPIO23 BD5
10K_0402_5% GPIO24 BB2 FBVDDQ_PSI
GPIO25 GPIO26_FP_FUSE FBVDDQ_PSI 73
OPT@ BE7
GPIO26 BA4 IFPC_HPD GPIO26_FP_FUSE 31
IFPC_HPD 44
1

GPIO27 BB4 ADC_MUX_SEL_R RV66 1 2 0_0402_5%

ADC_MUX_SEL 76

1
GPIO28 BA3 IDLE_IN_SW
GPIO29 BB3
GPIO30
V1 0 RV327
100K_0402_1%
RV326
10K_0402_1%
RV330
100K_0402_1%
For GC6 20180827 change
@ @ @ Need change to SA00009PM00

2
ROM_SI
N18E-FCBGA2228_BGA2228 ROM_SO
ROM_SCLK UV12
@ FB_GC6_EN_R FBVDDQ_PWR_EN
RV49 1 2 0_0402_5% 1 4
1.0VGS_PG 1 2 0_0402_5% IN B OUT Y FBVDDQ_PWR_EN 73
RV1171 2

1
IN A
RV328 RV325 RV329 V1 0 3 5 RV1218 1 2 0_0402_5%
GND Vcc +3VS
100K_0402_1% 10K_0402_1% 100K_0402_1%
OPT@ OPT@ OPT@ V1 0
1 MC74VHC1G32DFT2G_SC70-5 1

2
CV480 GC6@
1U_0402_6.3V6K CV1111
@ modify by Grace .1U_0402_10V6-K
2 2 OPT@

C C

ROM_SO ROM_SI ROM_SCLK FS_OVERT# Function

+1.8VS_AON
+1.8VS_AON L L L ENABLE
PLT_RST_VGA#
2

+3VS
RV1214
0_0402_5%
+1.8VS_AON
+1.8VS_AON OPT@ +1.8VS_AON +3VS

2
1

RV44
2

10K_0402_5%
RV1221 RV1220 10K_0402_5% OPT@
0_0402_5% 2 1 DV9

1
OPT@ @ RV1172 1 2 0_0402_5% 2
73 FBVDDQ_PWROK
2

1
VGA_PWRGD 20,24
1
2

RV1215 RV1208 RV1174 1 2 0_0402_5% 3

74 1.0VGS_PG
RV5 RV6 10K_0402_5% RV1209 2.2K_0402_5% RV1212 RV1213
2.2K_0402_5% 2.2K_0402_5% @ 2.2K_0402_5% OPT@ 2.2K_0402_5% 2.2K_0402_5% V1 0 LBAT54AWT1G_SOT323-3
5

OPT@ OPT@ V0 3 OPT@ OPT@ OPT@ OPT@

1

1
G2

G2
1

VGA_SMB_CK2 4 3 I2CC_SCL 4 3
S2 D2 EC_SMB_CK2 16,49,55 S2 D2 NVDD_SCL 75

QV3B QV35B
PJT7838_SOT363-6 PJT7838_SOT363-6
OPT@ OPT@

V0
2

NVVDD
V0
G1

G1

FBVDDQ
VGA_SMB_DA2 1 6 I2CC_SDA 1 6
EC_SMB_DA2 16,49,55 NVDD_SDA 75

1
S1 D1 S1 D1
+5VALW
Vgs(th)≤1.0V Vgs(th)≤1.0V RV108 RV77

1
QV3A PU AT C SID +3VS AND 7K QV35A 5.11_0805_1% 5.11_0805_1%
PJT7838_SOT363-6 PJT7838_SOT363-6 +5VALW @ @ RV43 +3VS

2
OPT@ OPT@ 470_0603_5%

2
RV48 @

2
V0 47K_0402_5%

2
V0 RV78 @
47K_0402_5% RV61

1
1

3
@ D 10K_0402_5%
FBVDDQ_PWR_EN# 5 QV6B OPT@

D
1
G LBSS138DW1T1G_SOT363-6

1
6
NVVDD_EN# 2 QV8 D @
S

4
G AO3402_SOT-23-3 FBVDDQ_PWR_EN 2 QV6A PXS_PWREN
@ G LBSS138DW1T1G_SOT363-6

S
D @
S

1
NVVDD_EN 2 QV9

3
@
G
S
LBSS139WT1G_SC70-3
@
Reserve RV106
10K_0402_5%

3
VGA_ALERT# DV6 2 1 RB751V-40_SOD323-2 +3VS @

2
Reserve
2

VGA_AC_DET_R 2 1 RB751V-40_SOD323-2
DV1
VGA_AC_DET 49 +3VS RV54
OPT@ 10K_0402_5%
GC6@
1
2

RV55 1 2 0_0402_5%
PCH_FB_GC6_EN 19

Y540 N18E Strap5 Strap4 Strap3

RV53
10K_0402_5% FB_GC6_EN_R V1 0
GC6@
1

D
FB_GC6_EN# 5 QV7B
G LBSS138DW1T1G_SOT363-6
6

D GC6@

DGPU only+Non G-sync panel 0 0 1

S
4

FB_GC6_EN 2 QV7A
G LBSS138DW1T1G_SOT363-6
S GC6@
1
2

RV56
10K_0402_5%
GC6@

DGPU only+G-sync panel 1 0 1

1

B B
+3VS
1

RV36
0_0402_5%
+3VS
2

+1.8VS_AON +1.8VS_AON +3VS

+1.8VS_AON
1
2

CV58
RV216 .1U_0402_10V6-K
2

10K_0402_5% 2 OPT@ 1
@ RV50 RV58 RV1175
.1U_0402_10V6-K

10K_0402_5% 10K_0402_5% CV65 10K_0402_5%

1

OPT@ GC6@ GC6@ GC6@

5

UV3 2
1

PLT_RST# 1
P

18,45,49,50,51 PLT_RST# B VGA_RST# PLT_RST_VGA#

4 RV391 1 2 0_0402_5%
2 Y PLT_RST_VGA# 24
19 PXS_RST#
G

A GPU_EVENT#_R 3 1 GPU_EVENT# RV59 1 2 0_0402_5%

PCH_GPU_EVENT# 19
MC74VHC1G09DFT2G_SC70-5
3

OPT@
1

QV13
RV392 LSI1012XT1G_SC-89-3
RV217 100K_0402_5% GC6@
100K_0402_5% OPT@ Vgs(th)≤0.9V
OPT@
2

V0

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GPIO I/F

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A0 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 29 of 77
5 4 3 2 1
 5 4 3 2 1

UV1I UV1M
? UV1J ? NVVDD
? ? ?
NVVDD COMMON NVVDD ? COMMON
NVVDD COMMON NVVDD NVVDD NVVDD
17/22 VDD_1/3 22/22 VDD_3/3 Near GPU
82A 18/22 VDD_2/3 NVVDD NVVDD
AA13 AE28 Under GPU Under GPU

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M

330U_B2_2.5VM_R9M
AA14 VDD_001 VDD_076 AE29 AH39 AP23 BG45 R23
VDD_002 VDD_077 VDD_145 VDD_219 VDD_382 VDD_465 1 1 1
AA15 AE30 AH40 AP24 BG46 R24

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AA16 VDD_003 VDD_078 AE31 AJ13 VDD_146 VDD_220 AP25 BG47 VDD_383 VDD_466 R25 + + +
VDD_004 VDD_079 VDD_147 VDD_221 VDD_384 VDD_467

@
AA17 AE32 AJ40 AP26 BG48 R26 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AA18 VDD_005 VDD_080 AE33 AK13 VDD_148 VDD_222 AP27 BG49 VDD_385 VDD_468 R27
AA19 VDD_006 VDD_081 AE34 AK14 VDD_149 VDD_223 AP28 BG50 VDD_386 VDD_469 R28 2 2 2

OPT@

OPT@
VDD_007 VDD_082 VDD_150 VDD_224 VDD_387 VDD_470

@
AA20 AE35 AK15 AP29 BG51 R29 DG两两 70uf具具具具具具，用3两330uf代代

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV9

CV10

CV83

CV1013

CV1002

CV1004

CV1003

CV1007

CV1005

CV1006

CV1009

CV1010

CV1008

CV1011

CV1012

CV1061

CV1050

CV1051

CV1053

CV1056

CV1052

CV1055

CV1059

CV1057

CV1054

CV1058

CV1060
AA21 VDD_008 VDD_083 AE36 AK16 VDD_151 VDD_225 AP30 BG52 VDD_388 VDD_471 R30 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AA22 VDD_009 VDD_084 AE37 AK17 VDD_152 VDD_226 AP31 BH44 VDD_389 VDD_472 R31
AA23 VDD_010 VDD_085 AE38 AK18 VDD_153 VDD_227 AP32 BH45 VDD_390 VDD_473 R32
AA24 VDD_011 VDD_086 AE39 AK19 VDD_154 VDD_228 AP33 BH47 VDD_391 VDD_474 R33
VDD_012 VDD_087 VDD_155 VDD_229 VDD_392 VDD_475 Under GPU
AA25 AE40 AK20 AP34 BH48 R34
AA26 VDD_013 VDD_088 AF13 AK21 VDD_156 VDD_230 AP35 BH49 VDD_393 VDD_476 R35
AA27 VDD_014 VDD_089 AF14 AK22 VDD_157 VDD_231 AP36 BH50 VDD_394 VDD_477 R36
D AA28 VDD_015 VDD_090 AF15 AK23 VDD_158 VDD_232 AP37 BH51 VDD_395 VDD_478 R37 D
1 1 1 1 1 1 1

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AA29 VDD_016 VDD_091 AF16 AK24 VDD_159 VDD_233 AP38 BH52 VDD_396 VDD_479 R38 NVVDD NVVDD

47U_0603_4V6-M

47U_0603_4V6-M

47U_0603_4V6-M
AA30 VDD_017 VDD_092 AF17 AK25 VDD_160 VDD_234 AP39 BJ44 VDD_397 VDD_480 R39
VDD_018 VDD_093 VDD_161 VDD_235 VDD_398 VDD_481 Under GPU Under GPU
AA31 AF18 AK26 AP40 BJ45 R40
AA32 VDD_019 VDD_094 AF24 AK27 VDD_162 VDD_236 AR13 BJ46 VDD_399 VDD_482 T13 2 2 2 2 2 2 2

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VDD_020 VDD_095 VDD_163 VDD_237 VDD_400 VDD_483

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
AA33 AF25 AK28 AR40 BJ47 T40

CV158

CV15

CV16

CV18

CV31
AA34 VDD_021 VDD_096 AF26 AK29 VDD_164 VDD_238 AT13 BJ48 VDD_401 VDD_484 U13

CV11

CV14
VDD_022 VDD_097 VDD_165 VDD_239 VDD_402 VDD_485 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AA35 AF30 AK30 AT14 BJ49 U14
AA36 VDD_023 VDD_098 AF31 AK31 VDD_166 VDD_240 AT15 BJ50 VDD_403 VDD_486 U15
VDD_024 VDD_099 VDD_167 VDD_241 VDD_404 VDD_487

@
AA37 AF32 AK32 AT16 BJ51 U16

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV977

CV967

CV968

CV966

CV971

CV969

CV970

CV974

CV973

CV972

CV975

CV976

CV1073

CV1063

CV1064

CV1062

CV1066

CV1065

CV1067

CV1070

CV1068

CV1069

CV1071

CV1072
AA38 VDD_025 VDD_100 AF33 AK33 VDD_168 VDD_242 AT17 BJ52 VDD_405 VDD_488 U17 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AA39 VDD_026 VDD_101 AF34 AK34 VDD_169 VDD_243 AT18 BK47 VDD_406 VDD_489 U18
AA40 VDD_027 VDD_102 AF40 AK35 VDD_170 VDD_244 AT19 BK48 VDD_407 VDD_490 U19
AB13 VDD_028 VDD_103 AG13 AK36 VDD_171 VDD_245 AT20 BK49 VDD_408 VDD_491 U20 2 2 2 2 2 2 2 2 2 2 2 2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
AB40 VDD_029 VDD_104 AG19 AK37 VDD_172 VDD_246 AT21 BK50 VDD_409 VDD_492 U21
AC13 VDD_030 VDD_105 AG20 AK38 VDD_173 VDD_247 AT22 BK51 VDD_410 VDD_493 U22
AC14 VDD_031 VDD_106 AG21 AK39 VDD_174 VDD_248 AT23 BK52 VDD_411 VDD_494 U23
AC15 VDD_032 VDD_107 AG22 AK40 VDD_175 VDD_249 AT24 BL46 VDD_412 VDD_495 U24 1 1 1 1 1 1 1 1 1 1 1 1
AC16 VDD_033 VDD_108 AG23 AL13 VDD_176 VDD_250 AT25 BL47 VDD_413 VDD_496 U25

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
NVVDD NVVDD

CV161

CV162

CV163

CV164

CV917

CV915

CV911

CV912

CV916

CV910

CV914

CV913
AC17 VDD_034 VDD_109 AG27 AL40 VDD_177 VDD_251 AT26 BL48 VDD_414 VDD_497 U26
VDD_035 VDD_110 VDD_178 VDD_252 VDD_415 VDD_498 Under GPU Under GPU
AC18 AG28 AM13 AT27 BL49 U27
AC19 VDD_036 VDD_111 AG29 AM14 VDD_179 VDD_253 AT28 BL50 VDD_416 VDD_499 U28

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AC20 VDD_037 VDD_112 AG35 AM15 VDD_180 VDD_254 AT29 BL51 VDD_417 VDD_500 U29
AC21 VDD_038 VDD_113 AG36 AM16 VDD_181 VDD_255 AY26 BL52 VDD_418 VDD_501 U30
VDD_039 VDD_114 VDD_182 VDD_321 VDD_419 VDD_502 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AC22 AG37 AM17 AY27 BM47 U31
AC23 VDD_040 VDD_115 AG38 AM18 VDD_183 VDD_322 AY28 BM48 VDD_420 VDD_503 U32 2 2 2 2 2 2 2 2 2 2 2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
VDD_041 VDD_116 VDD_184 VDD_323 VDD_421 VDD_504

@
AC24 AG39 AM19 AY29 BM49 U33

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV990

CV992

CV991

CV996

CV994

CV993

CV998

CV997

CV995

CV999
CV1001

CV1000

CV1097

CV1086

CV1088

CV1087

CV1092

CV1090

CV1089

CV1095

CV1093

CV1091

CV1094

CV1096
AC25 VDD_042 VDD_117 AG40 AM20 VDD_185 VDD_324 AY30 BM50 VDD_422 VDD_505 U34 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AC26 VDD_043 VDD_118 AH13 AM21 VDD_186 VDD_325 AY31 BM51 VDD_423 VDD_506 U35
AC27 VDD_044 VDD_119 AH14 AM22 VDD_187 VDD_326 AY32 N13 VDD_424 VDD_507 U36 1 1 1 1 1 1 1 1 1 1 1
VDD_045 VDD_120 VDD_188 VDD_327 VDD_425 VDD_508

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
AC28 AH15 AM23 AY33 N14 U37

CV32

CV33

CV37

CV41

CV76

CV77

CV78

CV79

CV80

CV81

CV82
AC29 VDD_046 VDD_121 AH16 AM24 VDD_189 VDD_328 AY34 N15 VDD_426 VDD_509 U38
AC30 VDD_047 VDD_122 AH17 AM25 VDD_190 VDD_329 AY35 N16 VDD_427 VDD_510 U39
AC31 VDD_048 VDD_123 AH18 AM26 VDD_191 VDD_330 AY36 N17 VDD_428 VDD_511 U40
AC32 VDD_049 VDD_124 AH19 AM27 VDD_192 VDD_331 AY37 N18 VDD_429 VDD_512 V13
AC33 VDD_050 VDD_125 AH20 AM28 VDD_193 VDD_332 AY38 N19 VDD_430 VDD_513 V40 NVVDD NVVDD NVVDD
AC34 VDD_051 VDD_126 AH21 AM29 VDD_194 VDD_333 AY39 N20 VDD_431 VDD_514 W13
VDD_052 VDD_127 VDD_195 VDD_334 VDD_432 VDD_515 Under GPU Under GPU Under GPU
AC35 AH22 AM30 AY40 N21 W14
AC36 VDD_053 VDD_128 AH23 AM31 VDD_196 VDD_335 AY43 N22 VDD_433 VDD_516 W15

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AC37 VDD_054 VDD_129 AH24 AM32 VDD_197 VDD_336 AY45 N23 VDD_434 VDD_517 W16
AC38 VDD_055 VDD_130 AH25 AM33 VDD_198 VDD_337 BA43 N24 VDD_435 VDD_518 W17
VDD_056 VDD_131 VDD_199 VDD_338 VDD_436 VDD_519 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AC39 AH26 AM34 BA44 N25 W18
AC40 VDD_057 VDD_132 AH27 AM35 VDD_200 VDD_339 BA45 N26 VDD_437 VDD_520 W19
VDD_058 VDD_133 VDD_201 VDD_340 VDD_438 VDD_521

@
AD13 AH28 AM36 BA46 N27 W20

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV929

CV918

CV919

CV920

CV923

CV922

CV921

CV924

CV927

CV925

CV926

CV928

CV989

CV978

CV979

CV980

CV984

CV981

CV982

CV987

CV985

CV983

CV986

CV988

CV1085

CV1075

CV1074

CV1076

CV1080

CV1077

CV1078

CV1083

CV1082

CV1079

CV1081

CV1084
AD40 VDD_059 VDD_134 AH29 AM37 VDD_202 VDD_341 BA47 N28 VDD_439 VDD_522 W21 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AE13 VDD_060 VDD_135 AH30 AM38 VDD_203 VDD_342 BB38 N29 VDD_440 VDD_523 W22
AE14 VDD_061 VDD_136 AH31 AM39 VDD_204 VDD_343 BB39 N30 VDD_441 VDD_524 W23
AE15 VDD_062 VDD_137 AH32 AM40 VDD_205 VDD_344 BB45 N31 VDD_442 VDD_525 W24
AE16 VDD_063 VDD_138 AH33 AN13 VDD_206 VDD_345 BB46 N32 VDD_443 VDD_526 W25
AE17 VDD_064 VDD_139 AH34 AN40 VDD_207 VDD_346 BB47 N33 VDD_444 VDD_527 W26
C AE18 VDD_065 VDD_140 AH35 AP13 VDD_208 VDD_347 BB48 N34 VDD_445 VDD_528 W27 C
AE19 VDD_066 VDD_141 AH36 AP14 VDD_209 VDD_348 BC38 N35 VDD_446 VDD_529 W28
AE20 VDD_067 VDD_142 AH37 AP15 VDD_210 VDD_349 BC39 N36 VDD_447 VDD_530 W29 NVVDD NVVDD NVVDD
AE21 VDD_068 VDD_143 AH38 AP16 VDD_211 VDD_350 BC40 N37 VDD_448 VDD_531 W30
VDD_069 VDD_144 VDD_212 VDD_351 VDD_449 VDD_532 Under GPU Under GPU Under GPU
AE22 AV28 AP17 BC41 N38 W31
AE23 VDD_070 VDD_286 AV29 AP18 VDD_213 VDD_352 BC45 N39 VDD_450 VDD_533 W32

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AE24 VDD_071 VDD_287 AV30 AP19 VDD_214 VDD_353 BC47 N40 VDD_451 VDD_534 W33
AE25 VDD_072 VDD_288 AV31 AP20 VDD_215 VDD_354 BC49 P13 VDD_452 VDD_535 W34
VDD_073 VDD_289 VDD_216 VDD_355 VDD_453 VDD_536 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AE26 AV32 AP21 BD39 P40 W35
AE27 VDD_074 VDD_290 AV33 AP22 VDD_217 VDD_356 BE48 R13 VDD_454 VDD_537 W36
VDD_075 VDD_291 VDD_218 VDD_369 VDD_455 VDD_538

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
AT30 AV34 BD41 BE49 R14 W37

CV941

CV930

CV932

CV931

CV935

CV933

CV934

CV937

CV938

CV936

CV939

CV940

CV1025

CV1015

CV1016

CV1014

CV1019

CV1017

CV1018

CV1022

CV1021

CV1020

CV1023

CV1024

CV1102

CV1098

CV1099

CV1100

CV1101
AT31 VDD_256 VDD_292 AV35 BD46 VDD_357 VDD_370 BE50 R15 VDD_456 VDD_539 W38 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
AT32 VDD_257 VDD_293 AV36 BD47 VDD_358 VDD_371 BE51 R16 VDD_457 VDD_540 W39
AT33 VDD_258 VDD_294 AV37 BD48 VDD_359 VDD_372 BE52 R17 VDD_458 VDD_541 W40
AT34 VDD_259 VDD_295 AV38 BD49 VDD_360 VDD_373 BF42 R18 VDD_459 VDD_542 Y13
AT35 VDD_260 VDD_296 AV39 BD50 VDD_361 VDD_374 BF44 R19 VDD_460 VDD_543 Y40
AT36 VDD_261 VDD_297 AV40 BD51 VDD_362 VDD_375 BF45 R20 VDD_461 VDD_544
AT37 VDD_262 VDD_298 AV42 BE41 VDD_363 VDD_376 BF47 R21 VDD_462
AT38 VDD_263 VDD_299 AV43 BE42 VDD_364 VDD_377 BF49 R22 VDD_463
AT39 VDD_264 VDD_300 AV44 BE43 VDD_365 VDD_378 BF51 VDD_464 NVVDD NVVDD
AT40 VDD_265 VDD_301 AW13 BE46 VDD_366 VDD_379 BG43
VDD_266 VDD_302 VDD_367 VDD_380 Under GPU Under GPU
AT42 AW40 BE47 BG44
AU13 VDD_267 VDD_303 AW42 VDD_368 VDD_381

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AU40 VDD_268 VDD_304 AW43
AU43 VDD_269 VDD_305 AW44 BK45
VDD_270 VDD_306 VDD_SENSE NVVDD_VDD_SENSE 75 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AV13 AW45 BL45
AV14 VDD_271 VDD_307 AY13 GND_SENSE NVVDD_VSS_SENSE 75
VDD_272 VDD_308

@
AV15 AY14

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV953

CV942

CV944

CV943

CV947

CV945

CV946

CV949

CV950

CV948

CV951

CV952

CV1049

CV1038

CV1040

CV1039

CV1044

CV1042

CV1041

CV1046

CV1045

CV1043

CV1047

CV1048
AV16 VDD_273 VDD_309 AY15 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
VDD_274 VDD_310 trace width: 16mils
AV17 AY16 N18E-FCBGA2228_BGA2228 N18E-FCBGA2228_BGA2228
AV18 VDD_275 VDD_311 AY17 differential voltage sensing.
@ @
AV19 VDD_276 VDD_312 AY18 differential signal routing.
AV20 VDD_277 VDD_313 AY19
AV21 VDD_278 VDD_314 AY20
AV22 VDD_279 VDD_315 AY21
AV23 VDD_280 VDD_316 AY22
AV24 VDD_281 VDD_317 AY23 NVVDD NVVDD
AV25 VDD_282 VDD_318 AY24
VDD_283 VDD_319 Under GPU Under GPU
AV26 AY25
AV27 VDD_284 VDD_320

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VDD_285
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
N18E-FCBGA2228_BGA2228

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV965

CV954

CV956

CV955

CV960

CV958

CV957

CV962

CV961

CV959

CV963

CV964

CV1037

CV1026

CV1027

CV1028

CV1032

CV1029

CV1030

CV1035

CV1033

CV1031

CV1034

CV1036
@ 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_POWER GPU CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 30 of 77
5 4 3 2 1
 5 4 3 2 1

FBVDDQ FBVDDQ
UV1L
? UV1K
? ?
COMMON ?
17A 19/22 FBVDDQ COMMON +1.8VS_AON
20/22 NC/1V8
AA10 AT43
AA11 FBVDDQ_01 FBVDDQ_32 K12 BA10
AA42 FBVDDQ_02 FBVDDQ_33 K14 1V8_AON_1 BB14
AA43 FBVDDQ_03 FBVDDQ_34 K15 1V8_AON_2 BC14
AC10 FBVDDQ_04 FBVDDQ_35 K17 1V8_AON_3
AC11 FBVDDQ_05 FBVDDQ_36 K18
AC42 FBVDDQ_06 FBVDDQ_37 K20 +1.8VS_AON
AC43 FBVDDQ_07 FBVDDQ_38 K21
AD10 FBVDDQ_08 FBVDDQ_39 K23 FP_FUSE_GPU BD14 BD24
AD11 FBVDDQ_09 FBVDDQ_40 K24 UV11 FP_FUSE_SRC NC_1 BM44
AD42 FBVDDQ_10 FBVDDQ_41 K26 CV1103 1 2 OPT@ A2 A1 FP_FUSE_GPU NC_2 BM45
FBVDDQ_11 FBVDDQ_42 VIN Vout 1 NC_3

1
D AD43 K27 2.2U_0402_6.3V6M D
AF10 FBVDDQ_12 FBVDDQ_43 K29 B1 B2 GPIO26_FP_FUSE CV1104 RV1200
FBVDDQ_13 FBVDDQ_44 GND ON GPIO26_FP_FUSE 29
AF43 K30 2.2U_0402_6.3V6M 1/16W_2.21K_1%_0402
AG10 FBVDDQ_14 FBVDDQ_45 K32 2 OPT@ OPT@
FBVDDQ_15 FBVDDQ_46

1
AG11 K33 AP22913CN4-7_X1-WLB0909-4

2
AG42 FBVDDQ_16 FBVDDQ_47 K35 RV1198
FBVDDQ_17 FBVDDQ_48 OPT@
AG43 K36 10K_0402_5% N18E-FCBGA2228_BGA2228
AJ10 FBVDDQ_18 FBVDDQ_49 K38 OPT@
FBVDDQ_19 FBVDDQ_50 @
AJ11 K39

2
AJ42 FBVDDQ_20 FBVDDQ_51 K41
AJ43 FBVDDQ_21 FBVDDQ_52 L14
AK10 FBVDDQ_22 FBVDDQ_53 L15
AK11 FBVDDQ_23 FBVDDQ_54 L18
AK42 FBVDDQ_24 FBVDDQ_55 L20
AK43 FBVDDQ_25 FBVDDQ_56 L21
AM42 FBVDDQ_26 FBVDDQ_57 L23
AM43 FBVDDQ_27 FBVDDQ_58 L24
AN43 FBVDDQ_28 FBVDDQ_59 L26
AR42 FBVDDQ_29 FBVDDQ_60 L27
AR43 FBVDDQ_30 FBVDDQ_61 L30
R42 FBVDDQ_31 FBVDDQ_62 L32
R43 FBVDDQ_76 FBVDDQ_63 L33
U10 FBVDDQ_77 FBVDDQ_64 L35
U11 FBVDDQ_78 FBVDDQ_65 L36
U43 FBVDDQ_79 FBVDDQ_66 L39
V10 FBVDDQ_80 FBVDDQ_67 M10 +1.8VS_AON TO +1.8VS_VGA
V42 FBVDDQ_81 FBVDDQ_68 M43
V43 FBVDDQ_82 FBVDDQ_69 P10
Y10 FBVDDQ_83 FBVDDQ_70 P11
Y11 FBVDDQ_84 FBVDDQ_71 P42
PLAC W ST DG
Y42 FBVDDQ_85 FBVDDQ_72 P43
Y43 FBVDDQ_86 FBVDDQ_73 R10 RV38 1 OPT@ 2 2_0402_5% FBVDDQ_VSS_SENSE +1.8VS_AON +1.8VS_VGA
FBVDDQ_87 FBVDDQ_74 FBVDDQ_VSS_SENSE 73
R11
FBVDDQ_75

PLACE NEAR GPU LOCAL SENSE 1.3A

E52 FBVDDQ_SENSE_GPU RV79 2 OPT@ 1 2_0402_5% FBVDDQ_VCC_SENSE
FBVDDQ_SENSE FBVDDQ_VCC_SENSE 73
QV10
AON7400A_DFN8-5
+5VALW V20B+
P45 FB_VREF_PROBE RV1193 1 OPT@ 2 49.9_0402_1% 1
FB_VREF 5 S1 2

0.1U_0402_25V6
1
C10246 1 2 3.9P_50V_B_NPO_0402 D S2 3
S3 1

1
RV17 @ CV61 1

G
1

1
100K_0402_1% 0.01U_50V_K_X7R_0402
RV19 CV62
10U_0603_6.3V6M

CV60
RV42 OPT@ @ 1/10W_47_5%_0603

4
R44 FB_CAL_PD_VDDQ RV47 1 OPT@ 2 40.2_0402_1% 47K_0402_5% OPT@ 2 OPT@ @
FBVDDQ

2
FB_CAL_PD_VDDQ OPT@ RV21 2

2
P44 FB_CAL_PU_GND RV93 1 OPT@ 2 40.2_0402_1% 1 2

2
C FB_CAL_PU_GND 1K_0402_5% C
R45 FB_CAL_TERM_GND RV94 1 OPT@ 2 40.2_0402_1% OPT@
FB_CAL_TERM_GND

0.033U_25V_K_X7R_0402
3

1
D

LBSS138DW1T1G_SOT363-6
+1.8VGS_PWR_EN#
Place near balls QV5B 1
OPT@ 5

OPT@
RV1004

CV63
N18E-FCBGA2228_BGA2228 G 430K_0402_1%

6
D

LBSS138DW1T1G_SOT363-6
@ S OPT@

4
RV45 1 OPT@ 2 0_0402_5% 2 QV5A 2

2
29 1V8_MAIN_EN_R
G OPT@

1
S D

1
1
+1.8VGS_PWR_EN# 2 QV12
G L2N7002KWT1G_SOT323-3

0.1U_0402_25V6
DV11
RV24 OPT@

1
3 RV1107 2 1 0_0402_5% 100K_0402_5% S

3
FBVDDQ @ OPT@

2
@
1

2
+1.8VS_AON +1.8VS_AON
Place close to GPU

CV444
2 RV1106 2 1 0_0402_5%
@
2 2 2 2 under GPU near GPU
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

LBAT54SWT1G_SOT323-3
@
1 1 1 1 1 1 1 2 1

1U_0603_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1
OPT@

OPT@

OPT@

OPT@
CV190

CV191

CV192

CV193

2 2 2 2 2 2 2 1 2

@
OPT@

OPT@

OPT@

OPT@
Reserve PD3 RV1107 RV110 CV for NV sequence requirement-Harry 10/ 0
OPT@

OPT@

OPT@
CV205

CV206

CV214

CV203

CV207

CV211

CV204

CV208

CV213
Place close to GPU

1 1 1 1 1 1 1 1 1
CV194 OPT@
22U_0603_6.3V6-M

CV195 OPT@
22U_0603_6.3V6-M

CV196 OPT@
22U_0603_6.3V6-M

CV197 OPT@
22U_0603_6.3V6-M

CV198 OPT@
22U_0603_6.3V6-M

CV199 OPT@
22U_0603_6.3V6-M

CV200 OPT@
22U_0603_6.3V6-M

CV201 OPT@
22U_0603_6.3V6-M

CV202 OPT@
22U_0603_6.3V6-M

2 2 2 2 2 2 2 2 2

FBVDDQ FBVDDQ

B
Under GPU Partition A Under GPU Partition B OPT@
B
CD@

CD@

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
@

@
@

@
OPT@
CV873

CV862

CV863

CV864

CV868

CV865

CV866

CV867

CV871

CV869

CV870

CV872

CV885

CV875

CV874

CV877

CV880

CV876

CV879

CV878

CV883

CV881

CV882

CV884

2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1
@

@
OPT@
CV91

CV99
CV184

CV100

V0 3 V0 3 V0 3
FBVDDQ FBVDDQ
Under GPU Partition C Under GPU Partition D
CD@

CD@

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 2 2
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV909

CV899

CV898

CV901

CV904

CV900

CV903

CV902

CV907

CV905

CV906

CV908

CV897

CV887

CV886

CV890

CV891

CV888

CV892

CV889

CV895

CV893

CV894

CV896

2 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 1 1
@

@
OPT@

OPT@
CV111

CV112

CV188

CV189

FBVDDQ V0 3 V0 3
Reserved Follow EMC request placement
0.1U_0201_6.3V7-K

0.1U_0201_6.3V7-K

0.1U_0201_6.3V7-K

0.1U_0201_6.3V7-K

0.1U_0201_6.3V7-K

0.1U_0201_6.3V7-K

1 1 1 1 1 1
CV1112

CV1113

CV1114

CV1115

CV1116

CV1117
OPTEMC_NS@

OPTEMC_NS@

OPTEMC_NS@

OPTEMC_NS@

OPTEMC_NS@

OPTEMC_NS@

2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_POWER VDDQ
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 2.0

Date: Friday, March 22, 2019 Sheet 31 of 77

5 4 3 2 1
 5 4 3 2 1

UV1G
?
UV1F ?
COMMON
?
? 16/22 GND_2/3 UV1H
COMMON
AR20 B52 ?
15/22 GND_1/3
GND_238 GND_361 ?
AR21 B7 COMMON
A2 AH6 AR22 GND_239 GND_362 BA48 21/22 GND_3/3
A26 GND_001 GND_122 AH8 AR23 GND_240 GND_363 BA9
D A29 GND_002 GND_123 AJ14 AR24 GND_241 GND_364 BB49 BL40 N51 D
A3 GND_003 GND_124 AJ15 AR25 GND_242 GND_365 BC13 BL43 GND_482 GND_592 N6
A32 GND_004 GND_125 AJ16 AR26 GND_243 GND_366 BC16 BL5 GND_483 GND_593 N8
A50 GND_005 GND_126 AJ17 AR27 GND_244 GND_367 BC19 BL7 GND_484 GND_594 P14
A51 GND_006 GND_127 AJ18 AR28 GND_245 GND_368 BC2 BM2 GND_485 GND_595 P15
AA49 GND_007 GND_128 AJ19 AR29 GND_246 GND_369 BC22 BM3 GND_486 GND_596 P16
AA8 GND_008 GND_129 AJ2 AR30 GND_247 GND_370 BC25 C1 GND_487 GND_597 P17
AB10 GND_009 GND_130 AJ20 AR31 GND_248 GND_371 BC28 C29 GND_488 GND_598 P18
AB14 GND_010 GND_131 AJ21 AR32 GND_249 GND_372 BC31 C33 GND_489 GND_599 P19
AB15 GND_011 GND_132 AJ22 AR33 GND_250 GND_373 BC34 C5 GND_490 GND_600 P20
AB16 GND_012 GND_133 AJ23 AR34 GND_251 GND_374 BC37 C51 GND_491 GND_601 P21
AB17 GND_013 GND_134 AJ24 AR35 GND_252 GND_375 BC4 C52 GND_492 GND_602 P22
AB18 GND_014 GND_135 AJ25 AR36 GND_253 GND_376 BC51 D10 GND_493 GND_603 P23
AB19 GND_015 GND_136 AJ26 AR37 GND_254 GND_377 BC6 D12 GND_494 GND_604 P24
AB2 GND_016 GND_137 AJ27 AR38 GND_255 GND_378 BC8 D13 GND_495 GND_605 P25
AB20 GND_017 GND_138 AJ28 AR39 GND_256 GND_379 BD26 D16 GND_496 GND_606 P26
AB21 GND_018 GND_139 AJ29 AR4 GND_257 GND_380 BD29 D19 GND_497 GND_607 P27
AB22 GND_019 GND_140 AJ30 AR52 GND_258 GND_381 BD32 D22 GND_498 GND_608 P28
AB23 GND_020 GND_141 AJ31 AR9 GND_259 GND_382 BD35 D24 GND_499 GND_609 P29
AB24 GND_021 GND_142 AJ32 AT4 GND_260 GND_383 BD38 D25 GND_500 GND_610 P30
AB25 GND_022 GND_143 AJ33 AT5 GND_261 GND_384 BD52 D28 GND_501 GND_611 P31
AB26 GND_023 GND_144 AJ34 AT51 GND_262 GND_385 BE10 D30 GND_502 GND_612 P32
AB27 GND_024 GND_145 AJ35 AT52 GND_263 GND_386 BE13 D31 GND_503 GND_613 P33
AB28 GND_025 GND_146 AJ36 AT8 GND_264 GND_387 BE15 D34 GND_504 GND_614 P34
AB29 GND_026 GND_147 AJ37 AU10 GND_265 GND_388 BE16 D37 GND_505 GND_615 P35
AB30 GND_027 GND_148 AJ38 AU14 GND_266 GND_389 BE18 D4 GND_506 GND_616 P36
AB31 GND_028 GND_149 AJ39 AU15 GND_267 GND_390 BE19 D40 GND_507 GND_617 P37
AB32 GND_029 GND_150 AJ9 AU16 GND_268 GND_391 BE21 D43 GND_508 GND_618 P38
AB33 GND_030 GND_151 AK1 AU17 GND_269 GND_392 BE22 D46 GND_509 GND_619 P39
AB34 GND_031 GND_152 AK44 AU18 GND_270 GND_393 BE24 D49 GND_510 GND_620 P51
AB35 GND_032 GND_153 AK47 AU19 GND_271 GND_394 BE25 D7 GND_511 GND_621 R49
AB36 GND_033 GND_154 AL10 AU2 GND_272 GND_395 BE27 E2 GND_512 GND_622 R52
AB37 GND_034 GND_155 AL14 AU20 GND_273 GND_396 BE28 E4 GND_513 GND_623 T10
AB38 GND_035 GND_156 AL15 AU21 GND_274 GND_397 BE30 E48 GND_514 GND_624 T14
AB39 GND_036 GND_157 AL16 AU22 GND_275 GND_398 BE31 E5 GND_515 GND_625 T15
AB4 GND_037 GND_158 AL17 AU23 GND_276 GND_399 BE33 E51 GND_516 GND_626 T16
AB43 GND_038 GND_159 AL18 AU24 GND_277 GND_400 BE34 E8 GND_517 GND_627 T17
AB45 GND_039 GND_160 AL19 AU25 GND_278 GND_401 BE36 F10 GND_518 GND_628 T18
AB47 GND_040 GND_161 AL2 AU26 GND_279 GND_402 BE37 F13 GND_519 GND_629 T19
AB49 GND_041 GND_162 AL20 AU27 GND_280 GND_403 BE39 F16 GND_520 GND_630 T2
AB51 GND_042 GND_163 AL21 AU28 GND_281 GND_404 BE40 F17 GND_521 GND_631 T20
AB6 GND_043 GND_164 AL22 AU29 GND_282 GND_405 BF2 F19 GND_522 GND_632 T21
AB8 GND_044 GND_165 AL23 AU30 GND_283 GND_406 BF4 F21 GND_523 GND_633 T22
AD14 GND_045 GND_166 AL24 AU31 GND_284 GND_407 BF41 F22 GND_524 GND_634 T23
AD15 GND_046 GND_167 AL25 AU32 GND_285 GND_408 BF6 F25 GND_525 GND_635 T24
AD16 GND_047 GND_168 AL26 AU33 GND_286 GND_409 BG10 F28 GND_526 GND_636 T25
AD17 GND_048 GND_169 AL27 AU34 GND_287 GND_410 BG13 F31 GND_527 GND_637 T26
AD18 GND_049 GND_170 AL28 AU35 GND_288 GND_411 BG16 F34 GND_528 GND_638 T27
AD19 GND_050 GND_171 AL29 AU36 GND_289 GND_412 BG19 F35 GND_529 GND_639 T28
AD20 GND_051 GND_172 AL30 AU37 GND_290 GND_413 BG22 F37 GND_530 GND_640 T29
C AD21 GND_052 GND_173 AL31 AU38 GND_291 GND_414 BG25 F40 GND_531 GND_641 T30 C
AD22 GND_053 GND_174 AL32 AU39 GND_292 GND_415 BG28 F43 GND_532 GND_642 T31
AD23 GND_054 GND_175 AL33 AU4 GND_293 GND_416 BG31 F44 GND_533 GND_643 T32
AD24 GND_055 GND_176 AL34 AU45 GND_294 GND_417 BG34 F46 GND_534 GND_644 T33
AD25 GND_056 GND_177 AL35 AU47 GND_295 GND_418 BG37 F52 GND_535 GND_645 T34
AD26 GND_057 GND_178 AL36 AU49 GND_296 GND_419 BG40 F7 GND_536 GND_646 T35
AD27 GND_058 GND_179 AL37 AU51 GND_297 GND_420 BG42 G2 GND_537 GND_647 T36
AD28 GND_059 GND_180 AL38 AU6 GND_298 GND_421 BG7 G38 GND_538 GND_648 T37
AD29 GND_060 GND_181 AL39 AU8 GND_299 GND_422 BH15 G4 GND_539 GND_649 T38
AD30 GND_061 GND_182 AL4 AV4 GND_300 GND_423 BH18 G47 GND_540 GND_650 T39
AD31 GND_062 GND_183 AL43 AV45 GND_301 GND_424 BH2 G49 GND_541 GND_651 T4
AD32 GND_063 GND_184 AL45 AV9 GND_302 GND_425 BH21 G51 GND_542 GND_652 T43
AD33 GND_064 GND_185 AL47 AW14 GND_303 GND_426 BH24 G6 GND_543 GND_653 T45
AD34 GND_065 GND_186 AL49 AW15 GND_304 GND_427 BH27 H1 GND_544 GND_654 T47
AD35 GND_066 GND_187 AL51 AW16 GND_305 GND_428 BH30 H10 GND_545 GND_655 T49
AD36 GND_067 GND_188 AL6 AW17 GND_306 GND_429 BH33 H13 GND_546 GND_656 T51
AD37 GND_068 GND_189 AL8 AW18 GND_307 GND_430 BH36 H16 GND_547 GND_657 T6
AD38 GND_069 GND_190 AM4 AW19 GND_308 GND_431 BH39 H19 GND_548 GND_658 T8
AD39 GND_070 GND_191 AM9 AW20 GND_309 GND_432 BH42 H22 GND_549 GND_659 U7
AD44 GND_071 GND_192 AN14 AW21 GND_310 GND_433 BH5 H25 GND_550 GND_660 U9
AE10 GND_072 GND_193 AN15 AW22 GND_311 GND_434 BJ10 H28 GND_551 GND_661 V14
AE2 GND_073 GND_194 AN16 AW23 GND_312 GND_435 BJ12 H31 GND_552 GND_662 V15
AE4 GND_074 GND_195 AN17 AW24 GND_313 GND_436 BJ13 H34 GND_553 GND_663 V16
AE43 GND_075 GND_196 AN18 AW25 GND_314 GND_437 BJ14 H37 GND_554 GND_664 V17
AE45 GND_076 GND_197 AN19 AW26 GND_315 GND_438 BJ15 H40 GND_555 GND_665 V18
AE47 GND_077 GND_198 AN20 AW27 GND_316 GND_439 BJ16 H43 GND_556 GND_666 V19
AE49 GND_078 GND_199 AN21 AW28 GND_317 GND_440 BJ17 J1 GND_557 GND_667 V20
AE51 GND_079 GND_200 AN22 AW29 GND_318 GND_441 BJ18 J12 GND_558 GND_668 V21
AE6 GND_080 GND_201 AN23 AW30 GND_319 GND_442 BJ19 J17 GND_559 GND_669 V22
AE8 GND_081 GND_202 AN24 AW31 GND_320 GND_443 BJ20 J20 GND_560 GND_670 V23
AF1 GND_082 GND_203 AN25 AW32 GND_321 GND_444 BJ21 J38 GND_561 GND_671 V24
AF19 GND_083 GND_204 AN26 AW33 GND_322 GND_445 BJ22 J49 GND_562 GND_672 V25
AF20 GND_084 GND_205 AN27 AW34 GND_323 GND_446 BJ23 J52 GND_563 GND_673 V26
AF21 GND_085 GND_206 AN28 AW35 GND_324 GND_447 BJ24 K13 GND_564 GND_674 V27
AF22 GND_086 GND_207 AN29 AW36 GND_325 GND_448 BJ25 K16 GND_565 GND_675 V28
AF23 GND_087 GND_208 AN30 AW37 GND_326 GND_449 BJ26 K19 GND_566 GND_676 V29
AF27 GND_088 GND_209 AN31 AW38 GND_327 GND_450 BJ27 K2 GND_567 GND_677 V30
AF28 GND_089 GND_210 AN32 AW39 GND_328 GND_451 BJ28 K22 GND_568 GND_678 V31
AF29 GND_090 GND_211 AN33 AW4 GND_329 GND_452 BJ29 K25 GND_569 GND_679 V32
AF35 GND_091 GND_212 AN34 AW46 GND_330 GND_453 BJ30 K28 GND_570 GND_680 V33
AF36 GND_092 GND_213 AN35 AW5 GND_331 GND_454 BJ31 K31 GND_571 GND_681 V34
AF37 GND_093 GND_214 AN36 AW52 GND_332 GND_455 BJ32 K34 GND_572 GND_682 V35
AF38 GND_094 GND_215 AN37 AW8 GND_333 GND_456 BJ33 K37 GND_573 GND_683 V36
AF39 GND_095 GND_216 AN38 AY10 GND_334 GND_457 BJ34 K4 GND_574 GND_684 V37
AF45 GND_096 GND_217 AN39 AY2 GND_335 GND_458 BJ35 K40 GND_575 GND_685 V38
AF5 GND_097 GND_218 AN4 AY4 GND_336 GND_459 BJ36 K45 GND_576 GND_686 V39
AG14 GND_098 GND_219 AN5 AY47 GND_337 GND_460 BJ37 K47 GND_577 GND_687 V49
AG15 GND_099 GND_220 AN8 AY49 GND_338 GND_461 BJ38 K49 GND_578 GND_688 V52
AG16 GND_100 GND_221 AP10 AY51 GND_339 GND_462 BJ39 K51 GND_579 GND_689 W10
AG17 GND_101 GND_222 AP2 AY6 GND_340 GND_463 BJ40 K6 GND_580 GND_690 W2
B AG18 GND_102 GND_223 AP4 AY8 GND_341 GND_464 BJ41 K8 GND_581 GND_691 W4 B
AG24 GND_103 GND_224 AP43 B1 GND_342 GND_465 BJ42 M52 GND_582 GND_692 W43
AG25 GND_104 GND_225 AP45 B10 GND_343 GND_466 BJ43 M6 GND_583 GND_693 Y9
AG26 GND_105 GND_226 AP47 B13 GND_344 GND_467 BJ7 N10 GND_584 GND_726
AG3 GND_106 GND_227 AP49 B16 GND_345 GND_468 BK1 N2 GND_585
AG30 GND_107 GND_228 AP51 B19 GND_346 GND_469 BL1 N4 GND_586
AG31 GND_108 GND_229 AP6 B2 GND_347 GND_470 BL10 N43 GND_587
AG32 GND_109 GND_230 AP8 B22 GND_348 GND_471 BL13 N45 GND_588
AG33 GND_110 GND_231 AR14 B25 GND_349 GND_472 BL16 N47 GND_589
AG34 GND_111 GND_232 AR15 B28 GND_350 GND_473 BL19 N49 GND_590
AG44 GND_112 GND_233 AR16 B31 GND_351 GND_474 BL2 BL37 GND_591
AH10 GND_113 GND_234 AR17 B34 GND_352 GND_475 BL22 GND_481
AH2 GND_114 GND_235 AR18 B37 GND_353 GND_476 BL25
AH4 GND_115 GND_236 AR19 B40 GND_354 GND_477 BL28 N18E-FCBGA2228_BGA2228
AH43 GND_116 GND_237 BL34 B43 GND_355 GND_478 BL31
GND_117 GND_480 GND_356 GND_479 @
AH45 BC24 B46 B5
AH47 GND_118 GND_727 B48 GND_357 GND_359 B51
AH49 GND_119 GND_358 GND_360
AH51 GND_120
GND_121 N18E-FCBGA2228_BGA2228
@
N18E-FCBGA2228_BGA2228
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 2.0

Date: Friday, March 22, 2019 Sheet 32 of 77

5 4 3 2 1
 5 4 3 2 1

UV4D
?
? UV4C
COMMON ?
?
FBVDDQ COMMON

26,34 FBA_CMD[0..33]
A11 A1 UV4B FBA_CMD0 H3 K1 +FBA_VREFC
A13 VSS_1 VDD_1 A14 UV4A FBA_CMD9 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBA_CMD8 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBA_CMD32 H12 CA2_A
VSS_4 VDD_4 26 FBA_D[0..15] NORMAL 26 FBA_D[16..31] CA3_A
B1 H13 x16 x8 FBA_CMD7 H5
B14 VSS_5 VDD_5 H2 FBA_D0 G2 FBA_D24 N2 FBA_CMD11 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBA_D1 B3 DQ7_A FBA_D25 P3 DQ6_B FBA_CMD15 J12 CA5_A
C12 VSS_7 VDD_7 L2 FBA_D2 F2 DQ2_A FBA_D26 M2 DQ4_B FBA_CMD14 J11 CA6_A
D VSS_8 VDD_8 BYTE0 FBA_D3 DQ6_A BYTE3 FBA_D27 DQ7_B FBA_CMD3 CA7_A D
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBA_D4 B4 DQ4_A FBA_D28 U3 DQ5_B FBA_CMD1 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBA_D5 B2 DQ0_A FBA_D29 V3 DQ2_B FBA_CMD6 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_D6 E2 DQ3_A FBA_D30 U4 DQ1_B FBA_CMD10 G10 CABI_n_A
D14 VSS_12 VDD_12 FBA_D7 A3 DQ5_A FBA_D31 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC0 C2 FBA_EDC3 T2 TCK
VSS_15 FBVDDQ 26 FBA_EDC0 FBA_DBI0# EDC0_A 26 FBA_EDC3 FBA_DBI3# EDC0_B
E4 D2 R2 F10
F1 VSS_16 26 FBA_DBI0# DBI0_n_A 26 FBA_DBI3# DBI0_n_B TDI N10
F12 VSS_17 FBA_WCK01 D4 FBA_WCKB23 R4 TDO
VSS_18 26 FBA_WCK01 FBA_WCK01_N WCK_t_A 26 FBA_WCKB23 FBA_WCKB23_N NC3
F14 B10 D5 R5 F5
F3 VSS_19 VDDQ_1 B5 26 FBA_WCK01_N WCK_c_A 26 FBA_WCKB23_N NC4 FBA_CMD4 L3 TMS
G1 VSS_20 VDDQ_2 C1 FBA_D16 P13 FBA_CMD12 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBA_D17 U13 DQ13_B FBA_CMD5 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBA_D8 B11 FBA_D18 M13 DQ11_B FBA_CMD13 L12 CA2_B
VSS_23 VDDQ_5 FBA_D9 DQ8_A
NC BYTE2 FBA_D19 DQ15_B FBA_CMD7 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBA_D10 E13 DQ15_A FBA_D20 U12 DQ14_B FBA_CMD11 L10 CA4_B
VSS_25 VDDQ_7 BYTE1 FBA_D11 DQ13_A
NC
FBA_D21 DQ10_B FBA_CMD15 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBA_D12 E12 DQ14_A FBA_D22 V12 DQ12_B FBA_CMD14 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBA_D13 B12 DQ12_A FBA_D23 U11 DQ9_B FBA_CMD3 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBA_D14 B13 DQ10_A DQ8_B FBA_CMD1 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBA_D15 A12 DQ11_A FBA_EDC2 T13 FBA_CMD6 K5 CA9_B J14FBA_ZQ_1_A RV1124 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 26 FBA_EDC2 FBA_DBI2# EDC1_B FBA_CMD10 CABI_n_B ZQ_A
M14 J13 R13 M10
M3 VSS_31 VDDQ_13 J2 FBA_EDC1 C13 26 FBA_DBI2# DBI1_n_B CKE_n_B K14FBA_ZQ_1_B RV1122 1 OPT@ 2 121_0402_1%
GND
VSS_32 VDDQ_14 26 FBA_EDC1 FBA_DBI1# EDC1_A FBA_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 26 FBA_DBI1# DBI1_n_A NC 26 FBA_WCK23 FBA_WCK23_N WCK_t_B
N12 K2 R10
N14 VSS_34 VDDQ_16 L1 FBA_WCKB01 D11 26 FBA_WCK23_N WCK_c_B
NC
VSS_35 VDDQ_17 26 FBA_WCKB01 FBA_WCKB01_N D10 NC1
N3 L14 NC
P11 VSS_36 VDDQ_18 N11 26 FBA_WCKB01_N NC2 FBA_CMD2 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBA_CLK0# K10
VSS_41 VDDQ_23 26 FBA_CLK0# CK_c
R3 T11 FBA_CLK0 J10
VSS_42 VDDQ_24 26 FBA_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5 @
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV588

CV589

CV590

CV591

CV592

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ

1
RV97
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 2 +FBA_VREFC
RV98 +FBA_VREFC 34
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
@ RV99 CV464

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

2
@

@
2 QV1
CV587

CV576

CV577

CV578

CV582

CV579

CV580

CV581

CV585

CV583

CV584

CV586
29 MEM_VREF
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CV234

CV235

CV236

CV237

CV238

CV563

@
CV178

CV220

CV221

CV228

CV490

CV491

3
Vgs(th)≤0.9V VR FC IS N T US D IN
1 C NFIGURATI N
FBVDDQ FBVDDQ
1K HM PULL-D WN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLAC F TH 1 33K
F R RV99
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
CD@

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV564

CV565

CV566

CV567

CV571

CV568

CV569

CV570

CV575

CV572

CV573

CV574

CV492

CV493

CV494

CV239

CV240

CV241

CV242

CV243

CV244

CV245

CV246

CV247

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_A_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 33 of 77

5 4 3 2 1
 5 4 3 2 1

UV5D
?
? UV5C
COMMON ?
?
FBVDDQ COMMON
UV5A
26,33 FBA_CMD[0..33]
UV5B
A11 A1 NORMAL FBA_CMD20 H3 K1 +FBA_VREFC
A13 VSS_1 VDD_1 A14 26 FBA_D[32..47] FBA_CMD28 G11 CA0_A VREFC +FBA_VREFC 33
NORMAL
A2 VSS_2 VDD_2 E10 FBA_D36 G2 FBA_CMD21 G4 CA1_A
VSS_3 VDD_3 DQ7_A 26 FBA_D[48..63] CA2_A 1
A4 E5 FBA_D32 B3 x16 x8 FBA_CMD29 H12 CV172
B1 VSS_4 VDD_4 H13 FBA_D37 F2 DQ2_A FBA_D63 N2 FBA_CMD23 H5 CA3_A 820P_0402_25V7
VSS_5 VDD_5 BYTE4 FBA_D34 DQ6_A FBA_D61 DQ6_B FBA_CMD27 CA4_A
B14 H2 E3 P3 H10 @
C10 VSS_6 VDD_6 L13 FBA_D39 B4 DQ4_A FBA_D62 M2 DQ4_B FBA_CMD30 J12 CA5_A 2
VSS_7 VDD_7 FBA_D38 DQ0_A BYTE7 FBA_D60 DQ7_B FBA_CMD31 CA6_A
C12 L2 B2 P2 J11
D
C3 VSS_8 VDD_8 P10 FBA_D33 E2 DQ3_A FBA_D59 U3 DQ5_B FBA_CMD19 J4 CA7_A D
C5 VSS_9 VDD_9 P5 FBA_D35 A3 DQ5_A FBA_D56 V3 DQ2_B FBA_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D57 U4 DQ1_B FBA_CMD22 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_EDC4 C2 FBA_D58 U2 DQ0_B FBA_CMD26 G10 CABI_n_A
VSS_12 VDD_12 26 FBA_EDC4 FBA_DBI4# EDC0_A DQ3_B CKE_n_A
D14 D2
VSS_13 26 FBA_DBI4# DBI0_n_A FBA_EDC7
D3 T2 N5
E11 VSS_14 FBA_WCK45 D4 26 FBA_EDC7 FBA_DBI7# R2 EDC0_B TCK
VSS_15 FBVDDQ 26 FBA_WCK45 FBA_WCK45_N WCK_t_A 26 FBA_DBI7# DBI0_n_B
E4 D5 F10
F1 VSS_16 26 FBA_WCK45_N WCK_c_A FBA_WCKB67 R4 TDI N10
VSS_17 26 FBA_WCKB67 FBA_WCKB67_N NC3 TDO
F12 R5
VSS_18 26 FBA_WCKB67_N NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1 B5 FBA_D43 B11 FBA_D51 P13 FBA_CMD16 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBA_D47 G13 DQ8_A FBA_D48 U13 DQ13_B FBA_CMD25 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBA_D40 E13 DQ15_A FBA_D55 M13 DQ11_B FBA_CMD24 M4 CA1_B
VSS_22 VDDQ_4 BYTE5 FBA_D41 DQ13_A
NC BYTE6 FBA_D54 DQ15_B FBA_CMD33 CA2_B
G14 C14 F13 NC N13 L12
G3 VSS_23 VDDQ_5 C4 FBA_D45 E12 DQ14_A FBA_D53 U12 DQ14_B FBA_CMD23 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBA_D44 B12 DQ12_A FBA_D52 P12 DQ10_B FBA_CMD27 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D42 B13 DQ10_A FBA_D50 V12 DQ12_B FBA_CMD30 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D46 A12 DQ11_A FBA_D49 U11 DQ9_B FBA_CMD31 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD19 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC5 C13 FBA_EDC6 T13 FBA_CMD17 K3 CA8_B
GND
M12 VSS_29 VDDQ_11 H14 26 FBA_EDC5 FBA_DBI5# D13 EDC1_A 26 FBA_EDC6 FBA_DBI6# R13 EDC1_B FBA_CMD22 K5 CA9_B J14FBA_ZQ_2_A RV1177 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 26 FBA_DBI5# DBI1_n_A NC 26 FBA_DBI6# DBI1_n_B FBA_CMD26 CABI_n_B ZQ_A
M14 J13 M10
M3 VSS_31 VDDQ_13 J2 FBA_WCKB45 D11 FBA_WCK67 R11 CKE_n_B K14FBA_ZQ_2_B RV1178 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 26 FBA_WCKB45 FBA_WCKB45_N D10 NC1 26 FBA_WCK67 FBA_WCK67_N WCK_t_B ZQ_B
N1 K13 NC R10
VSS_33 VDDQ_15 26 FBA_WCKB45_N NC2 26 FBA_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBA_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 FBA_CLK1# K10
R3
T10
T12
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
follow CRB bit swa 26
26
FBA_CLK1#
FBA_CLK1
FBA_CLK1 J10
CK_c
CK_t
NC5
G5

T3 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5 @
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV596

CV597

CV598

CV599

CV600

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
CD@

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

1
@

@
CV636

CV623

CV624

CV625

CV628

CV627

CV626

CV629

CV632

CV630

CV631

CV635
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV617

CV620

CV616

CV619

CV618

CV621

CV633

CV634

CV611

CV610

CV609

CV608

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV622

CV601

CV602

CV603

CV607

CV604

CV605

CV606

CV614

CV612

CV613

CV615

CV595

CV638

CV637

CV639

CV642

CV641

CV640

CV643

CV593

CV645

CV644

CV594

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_A_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 34 of 77

5 4 3 2 1
 5 4 3 2 1

UV6D
?
? UV6C
COMMON ?
?
FBVDDQ COMMON

26,36 FBB_CMD[0..33]
A11 A1 UV6B FBB_CMD0 H3 K1 +FBB_VREFC
A13 VSS_1 VDD_1 A14 UV6A FBB_CMD9 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBB_CMD8 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBB_CMD32 H12 CA2_A
VSS_4 VDD_4 26 FBB_D[0..15] NORMAL 26 FBB_D[16..31] CA3_A
B1 H13 x16 x8 FBB_CMD7 H5
B14 VSS_5 VDD_5 H2 FBB_D7 G2 FBB_D27 N2 FBB_CMD11 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBB_D2 B3 DQ7_A FBB_D25 P3 DQ6_B FBB_CMD15 J12 CA5_A
D
C12 VSS_7 VDD_7 L2 FBB_D0 F2 DQ2_A FBB_D28 M2 DQ4_B FBB_CMD14 J11 CA6_A D
C3 VSS_8 VDD_8 P10
BYTE0 FBB_D5 E3 DQ6_A BYTE3 FBB_D26 P2 DQ7_B FBB_CMD3 J4 CA7_A
C5 VSS_9 VDD_9 P5 FBB_D1 B4 DQ4_A FBB_D29 U3 DQ5_B FBB_CMD1 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBB_D4 B2 DQ0_A FBB_D30 V3 DQ2_B FBB_CMD6 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_D3 E2 DQ3_A FBB_D24 U4 DQ1_B FBB_CMD10 G10 CABI_n_A
D14 VSS_12 VDD_12 FBB_D6 A3 DQ5_A FBB_D31 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBB_EDC0 C2 FBB_EDC3 T2 TCK
E4 VSS_15 FBVDDQ 26 FBB_EDC0 FBB_DBI0# D2 EDC0_A 26 FBB_EDC3 FBB_DBI3# R2 EDC0_B F10
VSS_16 26 FBB_DBI0# DBI0_n_A 26 FBB_DBI3# DBI0_n_B TDI
F1 N10
F12 VSS_17 FBB_WCK01 D4 FBB_WCKB23 R4 TDO
F14 VSS_18 B10 26 FBB_WCK01 FBB_WCK01_N D5 WCK_t_A 26 FBB_WCKB23 FBB_WCKB23_N R5 NC3 F5
VSS_19 VDDQ_1 26 FBB_WCK01_N WCK_c_A 26 FBB_WCKB23_N NC4 FBB_CMD4 TMS
F3 B5 L3
G1 VSS_20 VDDQ_2 C1 FBB_D22 P13 FBB_CMD12 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBB_D17 U13 DQ13_B FBB_CMD5 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBB_D13 B11 FBB_D19 M13 DQ11_B FBB_CMD13 L12 CA2_B
G3 VSS_23 VDDQ_5 C4 FBB_D10 G13 DQ8_A
NC BYTE2 FBB_D23 N13 DQ15_B FBB_CMD7 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBB_D8 E13 DQ15_A FBB_D20 U12 DQ14_B FBB_CMD11 L10 CA4_B
VSS_25 VDDQ_7 BYTE1 FBB_D9 DQ13_A
NC
FBB_D18 DQ10_B FBB_CMD15 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBB_D15 E12 DQ14_A FBB_D16 V12 DQ12_B FBB_CMD14 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBB_D12 B12 DQ12_A FBB_D21 U11 DQ9_B FBB_CMD3 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBB_D11 B13 DQ10_A DQ8_B FBB_CMD1 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBB_D14 A12 DQ11_A FBB_EDC2 T13 FBB_CMD6 K5 CA9_B J14FBB_ZQ_1_A RV1179 1 OPT@ 2 121_0402_1%
NC
M14 VSS_30 VDDQ_12 J13 DQ9_A 26 FBB_EDC2 FBB_DBI2# R13 EDC1_B FBB_CMD10 M10 CABI_n_B ZQ_A
VSS_31 VDDQ_13 FBB_EDC1 26 FBB_DBI2# DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBB_ZQ_1_B RV1180 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 26 FBB_EDC1 FBB_DBI1# EDC1_A FBB_WCK23 ZQ_B
N1 K13 D13 R11
N12 VSS_33 VDDQ_15 K2 26 FBB_DBI1# DBI1_n_A NC 26 FBB_WCK23 FBB_WCK23_N R10 WCK_t_B
VSS_34 VDDQ_16 FBB_WCKB01 26 FBB_WCK23_N WCK_c_B
N14 L1 D11 NC
N3 VSS_35 VDDQ_17 L14 26 FBB_WCKB01 FBB_WCKB01_N D10 NC1
NC
VSS_36 VDDQ_18 26 FBB_WCKB01_N NC2 FBB_CMD2
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBB_CLK0# K10
VSS_41 VDDQ_23 26 FBB_CLK0# CK_c
R3 T11 FBB_CLK0 J10
VSS_42 VDDQ_24 26 FBB_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
C C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14
V11
V13
VSS_47
VSS_48
VSS_49
VSS_50 +1.8VS_AON
follow CRB bit swa
V2 +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV649

CV650

CV652

CV651

CV653

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ

1
RV1181
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 2 +FBB_VREFC
RV1182 +FBB_VREFC 36
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
@ RV1183 CV675
CD@

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

2
B B
@

@
2 QV33
CV690

CV678

CV677

CV679

CV683

CV680

CV681

CV682

CV687

CV685

CV684

CV689
29 MEM_VREF
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CV669

CV672

CV670

CV673

CV671

CV674

@
CV688

CV686

CV663

CV664

CV661

CV662

3
Vgs(th)≤0.9V VR FC IS N T US D IN
1 C NFIGURATI N
1K HM PULL-D WN IS
FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM IN PLAC F TH 1 33K
F R RV1183
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV676

CV654

CV655

CV656

CV660

CV658

CV657

CV659

CV668

CV665

CV666

CV667

CV648

CV691

CV692

CV693

CV697

CV694

CV695

CV696

CV646

CV698

CV699

CV647

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_B_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 35 of 77

5 4 3 2 1
 5 4 3 2 1

UV7D
?
? UV7C
COMMON ?
?
FBVDDQ COMMON
UV7A
26,35 FBB_CMD[0..33]
UV7B
A11 A1 NORMAL FBB_CMD20 H3 K1 +FBB_VREFC
VSS_1 VDD_1 26 FBB_D[32..47] FBB_CMD28 CA0_A VREFC +FBB_VREFC 35
A13 A14 NORMAL G11
A2 VSS_2 VDD_2 E10 FBB_D38 G2 FBB_CMD21 G4 CA1_A
VSS_3 VDD_3 DQ7_A 26 FBB_D[48..63] CA2_A 1
A4 E5 FBB_D32 B3 x16 x8 FBB_CMD29 H12 CV743
B1 VSS_4 VDD_4 H13 FBB_D37 F2 DQ2_A FBB_D60 N2 FBB_CMD23 H5 CA3_A 820P_0402_25V7
VSS_5 VDD_5 BYTE4 FBB_D39 DQ6_A FBB_D56 DQ6_B FBB_CMD27 CA4_A
B14 H2 E3 P3 H10 @
C10 VSS_6 VDD_6 L13 FBB_D35 B4 DQ4_A FBB_D58 M2 DQ4_B FBB_CMD30 J12 CA5_A 2
D VSS_7 VDD_7 FBB_D36 DQ0_A BYTE7 FBB_D61 DQ7_B FBB_CMD31 CA6_A D
C12 L2 B2 P2 J11
C3 VSS_8 VDD_8 P10 FBB_D34 E2 DQ3_A FBB_D57 U3 DQ5_B FBB_CMD19 J4 CA7_A
C5 VSS_9 VDD_9 P5 FBB_D33 A3 DQ5_A FBB_D59 V3 DQ2_B FBB_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBB_D62 U4 DQ1_B FBB_CMD22 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_EDC4 C2 FBB_D63 U2 DQ0_B FBB_CMD26 G10 CABI_n_A
VSS_12 VDD_12 26 FBB_EDC4 FBB_DBI4# EDC0_A DQ3_B CKE_n_A
D14 D2
D3 VSS_13 26 FBB_DBI4# DBI0_n_A FBB_EDC7 T2 N5
VSS_14 FBB_WCK45 26 FBB_EDC7 FBB_DBI7# EDC0_B TCK
E11 D4 R2
E4 VSS_15 FBVDDQ 26 FBB_WCK45 FBB_WCK45_N D5 WCK_t_A 26 FBB_DBI7# DBI0_n_B F10
VSS_16 26 FBB_WCK45_N WCK_c_A FBB_WCKB67 TDI
F1 R4 N10
VSS_17 26 FBB_WCKB67 FBB_WCKB67_N NC3 TDO
F12 R5
F14 VSS_18 B10 26 FBB_WCKB67_N NC4 F5
x16 x8
F3 VSS_19 VDDQ_1 B5 FBB_D42 B11 FBB_D51 P13 FBB_CMD16 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBB_D47 G13 DQ8_A FBB_D50 U13 DQ13_B FBB_CMD25 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBB_D44 E13 DQ15_A FBB_D54 M13 DQ11_B FBB_CMD24 M4 CA1_B
VSS_22 VDDQ_4 BYTE5 FBB_D46 DQ13_A
NC BYTE6 FBB_D53 DQ15_B FBB_CMD33 CA2_B
G14 C14 F13 NC N13 L12
G3 VSS_23 VDDQ_5 C4 FBB_D41 E12 DQ14_A FBB_D52 U12 DQ14_B FBB_CMD23 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBB_D40 B12 DQ12_A FBB_D49 P12 DQ10_B FBB_CMD27 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D45 B13 DQ10_A FBB_D48 V12 DQ12_B FBB_CMD30 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBB_D43 A12 DQ11_A FBB_D55 U11 DQ9_B FBB_CMD31 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBB_CMD19 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBB_EDC5 C13 FBB_EDC6 T13 FBB_CMD17 K3 CA8_B
GND
VSS_29 VDDQ_11 26 FBB_EDC5 FBB_DBI5# EDC1_A 26 FBB_EDC6 FBB_DBI6# EDC1_B FBB_CMD22 CA9_B
M12 H14 D13 R13 K5 J14FBB_ZQ_2_A RV1184 1 OPT@ 2 121_0402_1%
M14 VSS_30 VDDQ_12 J13 26 FBB_DBI5# DBI1_n_A NC 26 FBB_DBI6# DBI1_n_B FBB_CMD26 M10 CABI_n_B ZQ_A
M3 VSS_31 VDDQ_13 J2 FBB_WCKB45 D11 FBB_WCK67 R11 CKE_n_B K14FBB_ZQ_2_B RV1185 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 26 FBB_WCKB45 FBB_WCKB45_N D10 NC1 26 FBB_WCK67 FBB_WCK67_N WCK_t_B ZQ_B
N1 K13 NC R10
N12 VSS_33 VDDQ_15 K2 26 FBB_WCKB45_N NC2 26 FBB_WCK67_N WCK_c_B
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBB_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 FBB_CLK1# K10
R3
T10
T12
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
follow CRB bit swa 26
26
FBB_CLK1#
FBB_CLK1
FBB_CLK1 J10
CK_c
CK_t
NC5
G5

C T3 U10 M5 C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV747

CV749

CV748

CV750

CV751

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

B B
@

@
CV733

CV720

CV721

CV722

CV725

CV723

CV724

CV726

CV730

CV727

CV728

CV732
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV714

CV717

CV713

CV715

CV716

CV718

CV729

CV731

CV708

CV707

CV706

CV705

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV719

CV752

CV753

CV700

CV704

CV701

CV702

CV703

CV711

CV709

CV710

CV712

CV746

CV736

CV734

CV735

CV739

CV738

CV737

CV740

CV744

CV742

CV741

CV745

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_B_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 36 of 77

5 4 3 2 1
 5 4 3 2 1

UV8D
?
? UV8C
COMMON ?
?
FBVDDQ COMMON

27,38 FBC_CMD[0..33]
A11 A1 UV8B FBC_CMD0 H3 K1 +FBC_VREFC
A13 VSS_1 VDD_1 A14 UV8A FBC_CMD9 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBC_CMD8 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBC_CMD32 H12 CA2_A
VSS_4 VDD_4 27 FBC_D[0..15] NORMAL 27 FBC_D[16..31] CA3_A
B1 H13 x16 x8 FBC_CMD7 H5
B14 VSS_5 VDD_5 H2 FBC_D2 G2 FBC_D30 N2 FBC_CMD11 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBC_D5 B3 DQ7_A FBC_D26 P3 DQ6_B FBC_CMD15 J12 CA5_A
C12 VSS_7 VDD_7 L2 FBC_D0 F2 DQ2_A FBC_D27 M2 DQ4_B FBC_CMD14 J11 CA6_A
D VSS_8 VDD_8 BYTE0 FBC_D6 DQ6_A BYTE3 FBC_D24 DQ7_B FBC_CMD3 CA7_A D
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBC_D1 B4 DQ4_A FBC_D28 U3 DQ5_B FBC_CMD1 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBC_D4 B2 DQ0_A FBC_D29 V3 DQ2_B FBC_CMD6 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBC_D3 E2 DQ3_A FBC_D25 U4 DQ1_B FBC_CMD10 G10 CABI_n_A
D14 VSS_12 VDD_12 FBC_D7 A3 DQ5_A FBC_D31 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBC_EDC0 C2 FBC_EDC3 T2 TCK
VSS_15 FBVDDQ 27 FBC_EDC0 FBC_DBI0# EDC0_A 27 FBC_EDC3 FBC_DBI3# EDC0_B
E4 D2 R2 F10
F1 VSS_16 27 FBC_DBI0# DBI0_n_A 27 FBC_DBI3# DBI0_n_B TDI N10
F12 VSS_17 FBC_WCK01 D4 FBC_WCKB23 R4 TDO
VSS_18 27 FBC_WCK01 FBC_WCK01_N WCK_t_A 27 FBC_WCKB23 FBC_WCKB23_N NC3
F14 B10 D5 R5 F5
F3 VSS_19 VDDQ_1 B5 27 FBC_WCK01_N WCK_c_A 27 FBC_WCKB23_N NC4 FBC_CMD4 L3 TMS
G1 VSS_20 VDDQ_2 C1 FBC_D19 P13 FBC_CMD12 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBC_D21 U13 DQ13_B FBC_CMD5 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBC_D14 B11 FBC_D16 M13 DQ11_B FBC_CMD13 L12 CA2_B
VSS_23 VDDQ_5 FBC_D10 DQ8_A
NC BYTE2 FBC_D17 DQ15_B FBC_CMD7 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBC_D9 E13 DQ15_A FBC_D22 U12 DQ14_B FBC_CMD11 L10 CA4_B
VSS_25 VDDQ_7 BYTE1 FBC_D11 DQ13_A
NC
FBC_D18 DQ10_B FBC_CMD15 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBC_D13 E12 DQ14_A FBC_D20 V12 DQ12_B FBC_CMD14 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBC_D8 B12 DQ12_A FBC_D23 U11 DQ9_B FBC_CMD3 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBC_D12 B13 DQ10_A DQ8_B FBC_CMD1 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBC_D15 A12 DQ11_A FBC_EDC2 T13 FBC_CMD6 K5 CA9_B J14FBC_ZQ_1_A RV1186 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 27 FBC_EDC2 FBC_DBI2# EDC1_B FBC_CMD10 CABI_n_B ZQ_A
M14 J13 R13 M10
M3 VSS_31 VDDQ_13 J2 FBC_EDC1 C13 27 FBC_DBI2# DBI1_n_B CKE_n_B K14FBC_ZQ_1_B RV1187 1 OPT@ 2 121_0402_1%
GND
VSS_32 VDDQ_14 27 FBC_EDC1 FBC_DBI1# EDC1_A FBC_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 27 FBC_DBI1# DBI1_n_A NC 27 FBC_WCK23 FBC_WCK23_N WCK_t_B
N12 K2 R10
N14 VSS_34 VDDQ_16 L1 FBC_WCKB01 D11 27 FBC_WCK23_N WCK_c_B
NC
VSS_35 VDDQ_17 27 FBC_WCKB01 FBC_WCKB01_N D10 NC1
N3 L14 NC
P11 VSS_36 VDDQ_18 N11 27 FBC_WCKB01_N NC2 FBC_CMD2 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBC_CLK0# K10
VSS_41 VDDQ_23 27 FBC_CLK0# CK_c
R3 T11 FBC_CLK0 J10
VSS_42 VDDQ_24 27 FBC_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14
V11
V13
VSS_47
VSS_48
VSS_49
VSS_50 +1.8VS_AON
follow CRB bit swa
V2 +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5 @
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV757

CV758

CV759

CV760

CV761

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ

1
RV1188
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 2 +FBC_VREFC
RV1190 +FBC_VREFC 38
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
@ RV1189 CV783
CD@

CD@
22U_6.3V_M_X6S_0603

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7
1

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

2
2
@

@
2 QV34
CV798

CV786

CV785

CV788

CV791

CV787

CV789

CV790

CV795

CV792

CV793

CV797
29 MEM_VREF
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CV777

CV780

CV778

CV781

CV779

CV782

@
CV796

CV794

CV770

CV772

CV769

CV771

3
Vgs(th)≤0.9V VR FC IS N T US D IN
1 C NFIGURATI N
FBVDDQ V1 0 FBVDDQ V0 3 V0 3
1K HM PULL-D WN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLAC F TH 1 33K
F R RV1189
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV784

CV762

CV763

CV764

CV768

CV766

CV765

CV767

CV775

CV774

CV773

CV776

CV756

CV799

CV800

CV801

CV804

CV803

CV802

CV805

CV754

CV806

CV807

CV755

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 37 of 77

5 4 3 2 1
 5 4 3 2 1

UV9D
?
? UV9C
COMMON ?
?
FBVDDQ COMMON
UV9A
27,37 FBC_CMD[0..33]
UV9B
A11 A1 NORMAL FBC_CMD20 H3 K1 +FBC_VREFC
VSS_1 VDD_1 27 FBC_D[32..47] FBC_CMD28 CA0_A VREFC +FBC_VREFC 37
A13 A14 NORMAL G11
A2 VSS_2 VDD_2 E10 FBC_D37 G2 FBC_CMD21 G4 CA1_A
VSS_3 VDD_3 DQ7_A 27 FBC_D[48..63] CA2_A 1
A4 E5 FBC_D36 B3 x16 x8 FBC_CMD29 H12 CV838
B1 VSS_4 VDD_4 H13 FBC_D33 F2 DQ2_A FBC_D62 N2 FBC_CMD23 H5 CA3_A 820P_0402_25V7
VSS_5 VDD_5 BYTE4 FBC_D35 DQ6_A FBC_D60 DQ6_B FBC_CMD27 CA4_A
B14 H2 E3 P3 H10 @
D
C10 VSS_6 VDD_6 L13 FBC_D38 B4 DQ4_A FBC_D63 M2 DQ4_B FBC_CMD30 J12 CA5_A 2 D
C12 VSS_7 VDD_7 L2 FBC_D39 B2 DQ0_A BYTE7 FBC_D61 P2 DQ7_B FBC_CMD31 J11 CA6_A
C3 VSS_8 VDD_8 P10 FBC_D32 E2 DQ3_A FBC_D58 U3 DQ5_B FBC_CMD19 J4 CA7_A
C5 VSS_9 VDD_9 P5 FBC_D34 A3 DQ5_A FBC_D57 V3 DQ2_B FBC_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBC_D56 U4 DQ1_B FBC_CMD22 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBC_EDC4 C2 FBC_D59 U2 DQ0_B FBC_CMD26 G10 CABI_n_A
D14 VSS_12 VDD_12 27 FBC_EDC4 FBC_DBI4# D2 EDC0_A DQ3_B CKE_n_A
VSS_13 27 FBC_DBI4# DBI0_n_A FBC_EDC7
D3 T2 N5
E11 VSS_14 FBC_WCK45 D4 27 FBC_EDC7 FBC_DBI7# R2 EDC0_B TCK
VSS_15 FBVDDQ 27 FBC_WCK45 FBC_WCK45_N WCK_t_A 27 FBC_DBI7# DBI0_n_B
E4 D5 F10
VSS_16 27 FBC_WCK45_N WCK_c_A FBC_WCKB67 TDI
F1 R4 N10
F12 VSS_17 27 FBC_WCKB67 FBC_WCKB67_N R5 NC3 TDO
VSS_18 27 FBC_WCKB67_N NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1 B5 FBC_D40 B11 FBC_D52 P13 FBC_CMD16 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBC_D41 G13 DQ8_A FBC_D49 U13 DQ13_B FBC_CMD25 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBC_D45 E13 DQ15_A FBC_D54 M13 DQ11_B FBC_CMD24 M4 CA1_B
G14 VSS_22 VDDQ_4 C14
BYTE5 FBC_D47 DQ13_A
NC BYTE6 FBC_D55 DQ15_B FBC_CMD33 CA2_B
F13 NC N13 L12
G3 VSS_23 VDDQ_5 C4 FBC_D44 E12 DQ14_A FBC_D48 U12 DQ14_B FBC_CMD23 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBC_D46 B12 DQ12_A FBC_D53 P12 DQ10_B FBC_CMD27 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBC_D42 B13 DQ10_A FBC_D50 V12 DQ12_B FBC_CMD30 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBC_D43 A12 DQ11_A FBC_D51 U11 DQ9_B FBC_CMD31 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBC_CMD19 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBC_EDC5 C13 FBC_EDC6 T13 FBC_CMD17 K3 CA8_B
GND
M12 VSS_29 VDDQ_11 H14 27 FBC_EDC5 FBC_DBI5# D13 EDC1_A 27 FBC_EDC6 FBC_DBI6# R13 EDC1_B FBC_CMD22 K5 CA9_B J14FBC_ZQ_2_A RV1191 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 27 FBC_DBI5# DBI1_n_A NC 27 FBC_DBI6# DBI1_n_B FBC_CMD26 CABI_n_B ZQ_A
M14 J13 M10
M3 VSS_31 VDDQ_13 J2 FBC_WCKB45 D11 FBC_WCK67 R11 CKE_n_B K14FBC_ZQ_2_B RV1192 1 OPT@ 2 121_0402_1%
NC
N1 VSS_32 VDDQ_14 K13 27 FBC_WCKB45 FBC_WCKB45_N D10 NC1 27 FBC_WCK67 FBC_WCK67_N R10 WCK_t_B ZQ_B
NC
VSS_33 VDDQ_15 27 FBC_WCKB45_N NC2 27 FBC_WCK67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBC_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 FBC_CLK1# K10

C
R3
T10
T12
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
follow CRB bit swa 27
27
FBC_CLK1#
FBC_CLK1
FBC_CLK1 J10
CK_c
CK_t
NC5
G5
C
T3 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

VPP_1 A5 @
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1
V5
VPP_4
OPT@

OPT@

OPT@

OPT@

OPT@
CV842

CV843

CV844

CV845

CV846

2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

V0 3
FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM

CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
22U_6.3V_M_X6S_0603

2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

B B
@

@
CV828

CV815

CV816

CV817

CV821

CV819

CV818

CV820

CV824

CV822

CV823

CV827
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV808

CV812

CV809

CV810

CV811

OPT@
CV813

CV825

CV826

CV856

CV857

CV855

CV854

FBVDDQ V1 0 FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
CD@
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV814

CV847

CV848

CV849

CV853

CV850

CV851

CV852

CV860

CV859

CV858

CV861

CV841

CV832

CV829

CV830

CV834

CV833

CV831

CV835

CV839

CV836

CV837

CV840

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18E-G1_GDDR6_C_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 38 of 77

5 4 3 2 1
 5 4 3 2 1

LCD POWER CIRCUIT

+LCD_VDD +3VS

U9
W=60mils W=60mils V20B+ +LED_VDD
R22 1 2 0_0603_5% 1 5
OUT IN F3

4.7U_0603_6.3V6K

0.1u_0201_10V6K
2 2A 80 mil 2A 80 mil
GND 1 2
1 1
2 1 3 4
OCB EN
C7

C8
R275 1 1
D D
0_0402_5% 3A_32V_0497003PKRHF C14 C15
2 2 SY6288C20AAC_SOT23-5 4.7U_0805_25V6K 0.1U_0402_25V6
@
CD@ EMC@
2 2

EMI Request

MUX_EDP_ENVDD
57 MUX_EDP_ENVDD

1
100K_0402_5%

.1U_0402_10V6-K
1 V0

R7

C23
2 2@

Logo_led_PWM

1
D
PWR_LED2 2
49 PWR_LED2 G Q5819
2N7002KW_SOT323-3
S

3
C C
MUX_INVT_PWM EDP_HPD
1

R20 R57
100K_0201_5% 100K_0201_5%
2

MKyoceraSP0100 0700
S1HIGHSTARSP0100 0800

V0

JP6
2A 80 mil
1
EMI request +LED_VDD
2 1
3 2
DMIC_CLK_R DMIC_DATA BKOFF# MUX_INVT_PWM 4 3
V1 0 5 4
1A Inrush 2A 5
+LCD_VDD 6
R10683 1 2 0_0402_5% 7 6
1 1 1 1 +5VS 7
V0 BKOFF# 8
49 BKOFF# MUX_INVT_PWM 9 8
C11 CH19 C12 C13
100P_50V_J_NPO_0201 10P_50V_D_NPO_0201 470P_25V_K_X7R_0201 470P_25V_K_X7R_0201 57 MUX_INVT_PWM EDP_HPD 9
+3VALW R10684 1 @ 2 0_0402_5% 10
B 2 EMC@ 2 2 2 57 EDP_HPD Logo_led_PWM 10 B
EMC_NS@ EMC_NS@ EMC_NS@ 11
R10685 1 @ 2 0_0402_5% Logo_led_Power 12 11
+5VALW 12
13
MUX_EDP_TX0+ C19 1 2 0.1u_0201_10V6K EDP_TX0+ 14 13
57 MUX_EDP_TX0+ MUX_EDP_TX0- EDP_TX0- 14
C16 1 2 0.1u_0201_10V6K 15
57 MUX_EDP_TX0- 15
16
MUX_EDP_AUX# C21 1 2 0.1u_0201_10V6K EDP_AUX# 17 16
V0 57 MUX_EDP_AUX# MUX_EDP_AUX EDP_AUX 17
C20 1 2 0.1u_0201_10V6K 18
57 MUX_EDP_AUX 19 18
MUX_EDP_TX1- C18 1 2 0.1u_0201_10V6K EDP_TX1- 20 19
57 MUX_EDP_TX1- MUX_EDP_TX1+ EDP_TX1+ 20
C17 1 2 0.1u_0201_10V6K 21
57 MUX_EDP_TX1+ V1 0 22 21
R10686 1 2 0_0603_5% +3VS_DMIC 23 22
+3VS 0.5A DMIC_DATA 23
24
54 DMIC_DATA_R V0 DMIC_CLK_R 24
25
54 DMIC_CLK_R +3VS_CMOS 25
+3VS 0.5A R10688 1 2 0_0603_5% 26
27 26
R10689 1 @ 2 0_0402_5% USB20_N6_R 28 27
19 USB20_N6 USB20_P6_R 28
R10690 1 @ 2 0_0402_5% 29
+1.8VS_AON 19 USB20_P6 29
30
MUX_EDP_TX3+ C10203 1 2 0.1u_0201_10V6K EDP_TX3+ 31 30
57 MUX_EDP_TX3+ MUX_EDP_TX3- 1 2 0.1u_0201_10V6K EDP_TX3- 32 31
C10202
57 MUX_EDP_TX3- 32
33
2

RV1282 MUX_EDP_TX2- 1 2 0.1u_0201_10V6K EDP_TX2- 34 33

C10204
10K_0402_5% 57 MUX_EDP_TX2- MUX_EDP_TX2+ C10205 EDP_TX2+ 34
1 2 0.1u_0201_10V6K 35
+3VALW 57 MUX_EDP_TX2+ 35
36
For EMI GSYNC# 37 36
38 37
1

EXC24CH900U_4P 39 38 41
39 GND1
2

USB20_N6 4 3 USB20_N6_R RV1283 2 40 42

4 3 GPU_FRAME_LOCK# 29 40 GND2
+LCD_VDD 10K_0402_5% C10155
GSYNC@ 0.047U_0402_16V7K
USB20_P6 1 2 USB20_P6_R CD@ CVILU_CF69402D0R0-05-NH
3

1 2 1
ME@
1

L12 QV47B
D2
1

EMC@ 5 PJT7838_SOT363-6
RV1258 G2 GSYNC@ SVT modify by grace
A A
S2

10K_0402_5%
GSYNC@
2

4
6

V0 QV47A
D1

GSYNC# 2 PJT7838_SOT363-6
G1
S1

GSYNC@
1

Security Classification LC Future Center Secret Data Title

Vgs(th)≤1.0V
Issued Date 2018/08/02 Deciphered Date 2018/08/02 eDP/ CMOS/Touch screen
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
V1 0 DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 39 of 77

5 4 3 2 1
 5 4 3 2 1

+3VS_USB3_RE

+3VALW +3VS_USB3_RE
1 1
CW32 CW33
.1U_0402_10V6-K .1U_0402_10V6-K
D 2 2 D
@ @
+3VS RW31 1 2 0_0402_5%
USB3.0 Repeator
U124
R282 1 @ 2 0_0402_5% 1
13 VDD1
VDD2

USB_EQ1_A 15 4 USB_EQ1_B
USB_DE0_A 16 A_EQ1_SDA_CTL B_EQ1_I2C_ADDR1 3 USB_DE0_B
USB_EQ0_A 17 A_DE0_SCL_CTL B_DE0_I2C_ADDR0 2 USB_EQ0_B
USB_DE1_A 18 A_EQ0_NC B_EQ0_NC 6 USB_DE1_B
A_DE1_NC B_DE1_NC
CW30 1 2 0.1U_0201_6.3V6-K USB3_TX2+_REIN 19 12 USB30_TX_P2_B
15 TYPE-C_USB3_TX_P2 USB3_TX2-_REIN A_INp A_OUTp USB30_TX_N2_B USB30_TX_P2_B 41
CW31 1 2 0.1U_0201_6.3V6-K 20 11
15 TYPE-C_USB3_TX_N2 A_INn A_OUTn USB30_TX_N2_B 41

USB30_RX_P2_B 9 22 USB3_RX2+_REOUT CW37 1 2 0.1U_0201_6.3V6-K

41 USB30_RX_P2_B USB30_RX_N2_B B_INp B_OUTp USB3_RX2-_REOUT TYPE-C_USB3_RX_P2 15
8 23 CW36 1 2 0.1U_0201_6.3V6-K TYPE-C_USB3_RX_N2 15
41 USB30_RX_N2_B B_INn B_OUTn

RXD_EN 5
REXT 7 PD# 10
TEST 14 REXT GND1 21
24 TEST GND2 25

1
I2C_EN GPAD
RW30 PS8713BTQFN24GTR2A_TQFN24_4X4 Q & D setting B M structure
3.9K_0402_1% default setting need fine tune
PS8713@
Base on test result fine turn the resistor value

2
Location PS8713BT PI3 QX750 M

@
RW38 no need use 750 M@

C +3VS_USB3_RE RW3 C
LFPS swing adjust @
3 3V tolerant Internally ulled down at ~150KΩ @ default setting
T ST RW35 internal ull down Q_A/B: floating for Q dB
TEST RW27 1 2 4.7K_0201_5% L: Normal LFPS swing default no need e ternal resistance D _A/B: floating for D -3 5dB
H:Turn down LFPS swing need fine tune
PS8713@ RW3

RW37

@
RW30 PS8713@ floating
RW 7 without e ternal connection
+3VS_USB3_RE RW19
V0 3 RW @
qualizer control and rogram for channel A +3VS_USB3_RE qualizer control and rogram for channel B RW 3 Used for Q&D setting NC in
RXD_EN RW38 2 7502M@ 1 4.7K_0201_5% 3 3V tolerant Internally ulled down at ~150K 3 3V tolerant Internally ulled down at ~150K RW base on fine tune result no need use
[A_ Q1 A_ Q0] [B_ Q1 B_ Q0]
USB_EQ1_A RW19 1 @ 2 4.7K_0201_5% LL: rogram Q for channel loss u to 9 5dB default USB_EQ1_B RW23 1 @ 2 4.7K_0201_5% LL: rogram Q for channel loss u to 9 5dB default
LH: rogram Q for channel loss u to 13dB LH: rogram Q for channel loss u to 13dB
USB_EQ0_A RW20 1 @ 2 4.7K_0201_5% HL: rogram Q for channel loss u to 5dB USB_EQ0_B RW24 1 2 4.7K_0201_5% HL: rogram Q for channel loss u to 5dB RW 0
HH: rogram Q for channel loss u to 7 5dB HH: rogram Q for channel loss u to 7 5dB RW 1 Used for Q&D setting Used for Q&D setting
RW base on fine tune result base on fine tune result
+3VS_USB3_RE +3VS_USB3_RE RW 5
Programmable out ut de-em hasis level setting for channel A Programmable out ut de-em hasis level setting for channel B
3 3V tolerant Internally ulled down at ~150K 3 3V tolerant Internally ulled down at ~150K
USB_DE0_A RW21 1 @ 2 4.7K_0201_5% [A_D 1 A_D 0] USB_DE0_B RW25 1 2 4.7K_0201_5% [B_D 1 B_D 0]
LL: 3 5dB de-em hasis default LL: 3 5dB de-em hasis default
USB_DE1_A RW22 1 @ 2 4.7K_0201_5% LH: No de-em hasis USB_DE1_B RW26 1 2 4.7K_0201_5% LH: No de-em hasis
HL: 7dB de-em hasis HL: 7dB de-em hasis
HH: 5dB de-em hasis HH: 5dB de-em hasis

B B

only for PI3 QX750 M Q & D setting

USB_DE0_B RW34 1 @ 2 4.7K_0201_5%
USB_EQ0_B RW35 1 @ 2 4.7K_0201_5%
USB_DE0_A RW36 1 @ 2 4.7K_0201_5%
USB_EQ0_A RW37 1 @ 2 4.7K_0201_5%
RXD_EN RW39 1 @ 2 4.7K_0201_5%

V0 3

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DDI Redriver PS8330

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 40 of 77

5 4 3 2 1
 4 3 2 1

500mA 500mA
+5VALW VCONN_IN

@
R105 1 2 0_0603_5%

1 3
100mA 100mA

S
Q8 +5V_IN_RTS5455 +5VALW +5V_IN_RTS5455

1
LP2301ALT1G_SOT23-3

G
2
R2078
47K_0402_5%
R103 1 2 0_0603_5%

2
TYPEC_GPIO9

10U_0603_6.3V6M
D Low 2 D

HiZ 1

C10144
C4205
0.1U_0402_10V7K
1
2

VCONN_IN +LDO_3V3
500mA

10U_0805_10V6K

.1U_0402_10V6-K
1 2

C102

C101
2 1
1 2
C4206 C10120
4.7U_0402_6.3V6M 0.1U_0402_10V7K
2 1

+VBUS_P0 USBC_CC1_CONN USBC_CC2_CONN

10

25

26
U4
1 1

VCON_IN

5V_IN

LDO_3V3
C4212 C4214
220P_0402_50V7K 220P_0402_50V7K
1

2 2
R4208 Zdiff 90ohm No via
200K_0402_1%
40 USB30_TX_N2_B
C4230 1 2 0.22U_0201_6.3V6-K USB3P2_TXN_C
USB3P2_TXP_C
41
SSTX_1P/2N
PD Controller SBU2/MGPIO7
4 USBC_DPAUX2_CONN
USBC_DPAUX1_CONN USBC_DPAUX2_CONN 42
C4207 1 2 0.22U_0201_6.3V6-K 42 3
40 USB30_TX_P2_B USBC_DPAUX1_CONN 42
2

SSTX_1N/2P SBU1/MGPIO6
USB3P2_RXN_C VBUS_DSCHG

10Gbps MUX System Side

Type-C Port side

VMON C10183 1 2 0.22U_0201_6.3V6-K 39 8
40 USB30_RX_N2_B USB3P2_RXP_C SSRX_1P/2N C_DM/BB_DM 7 VBUS_DSCHG 42
C10182 1 2 0.22U_0201_6.3V6-K 40 1
40 USB30_RX_P2_B SSRX_1N/2P C_DP/BB_DP TP4305
1

Zdiff=90ohm 11 USBC_CC2_CONN @
TYPE-C_DP_RE_TXP3 CC2 USBC_CC1_CONN USBC_CC2_CONN 42
R4209 C10125 1 2 0.1u_0201_10V6K 38 9
25 GPU_SNK0_DP3P TYPE-C_DP_RE_TXN3 DP3_1N/2P CC1 USBC_CC1_CONN 42
10K_0402_1% C10127 1 2 0.1u_0201_10V6K 37
25 GPU_SNK0_DP3N TYPE-C_DP_RE_TXP2 DP3_1P/2N TYPEC_RXP2
C10128 1 2 0.1u_0201_10V6K 46 18
25 GPU_SNK0_DP2P TYPE-C_DP_RE_TXN2 DP2_1N/2P C_RX2_1N/2P TYPEC_RXN2 TYPEC_RXP2 42
C10126 1 2 0.1u_0201_10V6K 45 19
25 GPU_SNK0_DP2N TYPEC_RXN2 42
2

C10121 1 2 0.1u_0201_10V6K TYPE-C_DP_RE_TXP1 44 DP2_1P/2N C_RX2_1P/2N 14 TYPEC_TXP2 C4220 1 2 0.1u_0201_10V6K TYPEC_C_TXP2

C 25 GPU_SNK0_DP1P TYPE-C_DP_RE_TXN1 DP1_1N/2P C_TX2_1N/2P TYPEC_TXN2 TYPEC_C_TXN2 TYPEC_C_TXP2 42 C
C10124 1 2 0.1u_0201_10V6K 43 15 C4221 1 2 0.1u_0201_10V6K
25 GPU_SNK0_DP1N TYPE-C_DP_RE_TXP0 DP1_1P/2N C_TX2_1P/2N TYPEC_RXP1 TYPEC_C_TXN2 42
C10122 1 2 0.1u_0201_10V6K 36 16
25 GPU_SNK0_DP0P TYPE-C_DP_RE_TXN0 DP0_1N/2P C_RX1_1N/2P TYPEC_RXN1 TYPEC_RXP1 42
C10123 1 2 0.1u_0201_10V6K 35 17
25 GPU_SNK0_DP0N DP0_1P/2N C_RX1_1P/2N TYPEC_TXP1 TYPEC_C_TXP1 TYPEC_RXN1 42
12 C4215 1 2 0.1u_0201_10V6K
C_TX1_1N/2P TYPEC_TXN1 TYPEC_C_TXN1 TYPEC_C_TXP1 42
13 C4218 1 2 0.1u_0201_10V6K
C_TX1_1P/2N TYPEC_C_TXN1 42

100K_0402_5% 2 1 R39 Zdiff=100ohm

+3VS

25 GPU_SNK0_AUX_DN C10157 1 2 0.1U_0402_10V7K TYPE-C_DP_RE_AUXN 2

C10156 1 2 0.1U_0402_10V7K TYPE-C_DP_RE_AUXP 1 AUX_N/MGPIO5
25 GPU_SNK0_AUX_DP AUX_P/MGPIO4
100K_0402_5% 2 1 R38 1 MGPIO3 6 33 RTS5455_SM_INT
H_DM/DCI_CLK/MGPIO3 SM_INT/GPIO4 RTS5455_SM_INT 14,49
TP4301 5
H_DP/DCI_DATA/MGPIO2 31 RTS5455_SM_SDA
@ SM_SDA/GPIO6
VBUS_EN 27 32 RTS5455_SM_CK
+LDO_3V3 +5VALW 42 VBUS_EN
TYPEC_GPIO9 28
I2C_EN/GPIO10
RTS5455 SM_SCL/GPIO5

I2C_INT/GPIO9
TYPE_C_OCP# R10271 1 2 0_0402_5% 29 24
42 TYPE_C_OCP# I2C_SDA/GPIO8 REXT
2

1 30 20
R4210 @ R4212 TP4304 I2C_SCL/GPIO7 DB_CFG
0_0402_5% 590K_0402_1% @ 34 TYPE-C_DP_RE_HPD
@ HPD/GPIO3

1
1

R4245 R4244
LOC_PWR_MON LOC_PWR_MON 23 0_0402_5% 6.2K_0402_1%
LOC_PWR_MON
22 47

2
IMON E_PAD
1

VMON 21
R4211 R4213 VMON
10K_0402_1% 10K_0402_1%
@
2

RTS5455-GR_QFN46_6P5X4P5
+LDO_3V3

RP2
B 1 4 RTS5455_SM_INT B
2 3 RTS5455_SM_SDA

4.7K_0404_4P2R_5%

R4350 2 1 4.7K_0402_5% RTS5455_SM_CK

+3VALW
+1.8VS_AON
2

R2080
HPD

1
0_0402_5% Change EC side SMbus power level HLZ SIV 0811 RRE67
10K_0402_5%
1

2
IFPA_HPD
29 IFPA_HPD
2

Address 0xAC
G

to NV GPU QRE8
MMBT3904WH_SOT323-3

1
C
R139 1 2 0_0402_5% 1 6 RTS5455_SM_CK 2 RRE65 1 2 100K_0402_5% TYPE-C_DP_RE_HPD
S

49,58 EC_SMB_CK0
D

B
5
G

Q10A

1
2N7002KDWH_SOT363-6 RRE63
EC 100K_0402_5%
R140 1 2 0_0402_5% 4 3 RTS5455_SM_SDA
S

49,58 EC_SMB_DA0
D

Q10B
2N7002KDWH
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
ESD 2KV

TYPE-C_DP_HPD RRE70 1 2 0_0402_5% TYPE-C_DP_RE_HPD

15 TYPE-C_DP_HPD
A A

to PCH

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB TYPE-C Controller

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 41 of 77
4 3 2 1
 4 3 2 1

R63 1 @ 2 0_0402_5%

TYPE-C_USB20_P4_C
TYPE-C_USB20_N4_C
L6
TYPE-C_PCH_USB20_N4 4 3 TYPE-C_USB20_N4_C
19 TYPE-C_PCH_USB20_N4 4 3

TYPE-C_PCH_USB20_P4 TYPE-C_USB20_P4_C

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
1 2
19 TYPE-C_PCH_USB20_P4 1 2

2
D18 D4313

GND4
GND3
GND2
GND1
EXC24CH900U_4P

2
EMC@
JUSBC1
R81 1 @ 2 0_0402_5%

GND8
GND7
GND6
GND5
B12 A1
D GND4 GND1 D

1
TYPE-C_RX1_P_C B11 A2 TYPE-C_TX1_P_C EMC_NS@ EMC_NS@

1
SSRXp1 SSTXp1
TYPE-C_RX1_N_C B10 A3 TYPE-C_TX1_N_C
R84 1 @ 2 0_0402_5% SSRXn1 SSTXn1
B9 A4
+VBUS_P0 Vbus4 Vbus1 +VBUS_P0
L1 EMC@ USBC_DPAUX2_CONN B8 A5 USBC_CC1_CONN
TYPEC_C_TXN1 1 2 TYPE-C_TX1_N_C 41 USBC_DPAUX2_CONN SBU2 CC1 USBC_CC1_CONN 41
41 TYPEC_C_TXN1 1 2 TYPE-C_USB20_N4_C TYPE-C_USB20_P4_C
B7 A6
Dn2 Dp1
TYPEC_C_TXP1 4 3 TYPE-C_TX1_P_C TYPE-C_USB20_P4_C B6 A7 TYPE-C_USB20_N4_C
41 TYPEC_C_TXP1 4 3 Dp2 Dn1
EXC24CH500U_4P USBC_CC2_CONN B5 A8 USBC_DPAUX1_CONN
41 USBC_CC2_CONN CC2 SBU1 USBC_DPAUX1_CONN 41
B4 A9
+VBUS_P0 Vbus3 Vbus2 +VBUS_P0
R86 1 @ 2 0_0402_5% TYPE-C_TX2_N_C B3 A10 TYPE-C_RX2_N_C
SSTXn2 SSRXn2
TYPE-C_TX2_P_C B2 A11 TYPE-C_RX2_P_C
SSTXp2 SSRXp2
B1 A12

GND10
@ GND3 GND2

GND9
R89 1 2 0_0402_5% D21
USBC_DPAUX1_CONN 9 10 1 1 USBC_DPAUX1_CONN

USBC_DPAUX2_CONN 8 9 2 2 USBC_DPAUX2_CONN

GND5
GND6
L22 EMC@ ATOB_066-12A1-3211
TYPEC_C_TXN2 1 2 TYPE-C_TX2_N_C USBC_CC1_CONN 7 7 4 4 USBC_CC1_CONN
41 TYPEC_C_TXN2 1 2
ME@ USBC_CC2_CONN USBC_CC2_CONN
6 6 5 5
TYPEC_C_TXP2 4 3 TYPE-C_TX2_P_C
41 TYPEC_C_TXP2 4 3 3
3
EXC24CH500U_4P
8

AZ1045-04F_DFN2510P10E-10-9
R91 1 @ 2 0_0402_5% EMC_NS@
C C

R92 1 @ 2 0_0402_5% D19

TYPE-C_TX2_N_C 10 1 TYPE-C_TX2_N_C
NC1 Line-1
EMC@ TYPE-C_TX2_P_C 9 2 TYPE-C_TX2_P_C
NC2 Line-2
EXC24CH500U_4P
TYPE-C_TX1_N_C 7 4 TYPE-C_TX1_N_C
TYPEC_RXP1 4 3 TYPE-C_RX1_P C10227 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_P_C NC3 Line-3
41 TYPEC_RXP1 4 3 TYPE-C_TX1_P_C TYPE-C_TX1_P_C
6 5
NC4 Line-4
TYPEC_RXN1 1 2 TYPE-C_RX1_N C10228 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_N_C 3
41 TYPEC_RXN1 1 2 GND1
L13 8
GND2
AZ1143-04F-R7G_DFN2510P10E10

220K_0201_5%
1

220K_0201_5%
EMC_NS@

1
R98 1 @ 2 0_0402_5%
R10522

R10523
2

R100 1 @ 2 0_0402_5% 2 D20

TYPE-C_RX2_N 10 1 TYPE-C_RX2_N
NC1 Line-1
TYPE-C_RX2_P 9 2 TYPE-C_RX2_P
NC2 Line-2
EXC24CH500U_4P TYPE-C_RX1_N 7 4 TYPE-C_RX1_N
TYPEC_RXP2 4 3 TYPE-C_RX2_P C10229 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_P_C NC3 Line-3
41 TYPEC_RXP2 4 3 TYPE-C_RX1_P TYPE-C_RX1_P
6 5
NC4 Line-4
TYPEC_RXN2 1 2 TYPE-C_RX2_N C10230 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_N_C 3
B 41 TYPEC_RXN2 1 2 GND1 B
L21 EMC@ 8
GND2
AZ1143-04F-R7G_DFN2510P10E10
220K_0201_5%

@
1

R101 1 2 0_0402_5%
220K_0201_5%

EMC_NS@
1
R10525

R10524
2

modify by grace 1 /31 V0

+VBUS_P0

+VBUS_P0
1

R171 +5VALW
High enable discharge @ 470_0603_5% 3A
Low disable discharge +5VALW +VBUS_P0

AZ5725-01F.R7GR_DFN1006P2X2

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K
2

10U_0805_25V6K
U27

1
R4203 R3147 1 1 1 1 1
1

C924
D 5 1

C53
0_0402_5% Q19 10K_0402_5%

C922

C921

C920
1
IN OUT

EMC_NS@

D4316
VBUS_DSCHG 1 2 2
41 VBUS_DSCHG @ G @ 2
1

GND 2 2 2 2 2
2

S 2N7002KW_SOT323-3 VBUS_EN 4 3 TYPE_C_OCP#

41 VBUS_EN TYPE_C_OCP# 41
3

EN FLAG

2
R4204
@ 100K_0402_5% Active high R10272 G517G1TO1U_TSOT-23-5 u date by bing 05 3

2
100K_0402_5%
1

A A
+5VALW

C1333 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1
150U_B2_6.3VM_R35M

@ 2 2
2 Security Classification LC Future Center Secret Data Title
CV462

CV463

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB TYPE-C Port

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 42 of 77

4 3 2 1
 5 4 3 2 1

R43 1 2 0_0402_5%

L2
GPU_DPC_AUX_DN C34 2 1 0.1u_0201_10V6K GPU_DPC_AUX_DN_C 1 2 GPU_DPC_AUX_DN_CON
25 GPU_DPC_AUX_DN 1 2
@
GPU_DPC_AUX_DP C341 2 1 0.1u_0201_10V6K GPU_DPC_AUX_DP_C 4 3 GPU_DPC_AUX_DP_CON
25 GPU_DPC_AUX_DP 4 3
EXC24CH900U_4P
R44 1 2 0_0402_5% +5VS
D D

R45 1 2 0_0402_5%

L3
GPU_DPC_TX3_DN C342 2 1 0.1u_0201_10V6K GPU_DPC_TX3_DN_C 1 2 GPU_DPC_TX3_DN_CON
25 GPU_DPC_TX3_DN 1 2

1
@ D
GPU_DPC_TX3_DP C347 2 1 0.1u_0201_10V6K GPU_DPC_TX3_DP_C 4 3 GPU_DPC_TX3_DP_CON GPU_DIS_PWR_EN 2 Q194
25 GPU_DPC_TX3_DP 4 3 G L2N7002KWT1G_SOT323-3
EXC24CH900U_4P
R46 1 2 0_0402_5% S

3
Q186A Q186B
PJT7838_SOT363-6 PJT7838_SOT363-6
R47 1 2 0_0402_5%
GPU_DPC_AUX_DN 1 6 3 4 GPU_DPC_AUX_DN_C
L4 S1 D1 D2 S2 +3VS

1
GPU_DPC_TX2_DP GPU_DPC_TX2_DP_C GPU_DPC_TX2_DP_CON

R10238
10K_0402_5%
C349 2 1 0.1u_0201_10V6K 1 2

G1

G2
25 GPU_DPC_TX2_DP 1 2
@ Vgs(th)≤1V

5
GPU_DPC_TX2_DN C348 2 1 0.1u_0201_10V6K GPU_DPC_TX2_DN_C 4 3 GPU_DPC_TX2_DN_CON
25 GPU_DPC_TX2_DN 4 3

1
EXC24CH900U_4P
R48 1 2 0_0402_5% HD_DET

R10237
10K_0402_5%
Q193B

2
3
R49 1 2 0_0402_5% D 2N7002KDWH_SOT363-6

1
1 5

R10246
1M_0402_5%

C10149
0.01U_0201_6.3V7-K
L5 G

5
GPU_DPC_TX1_DP C351 2 1 0.1u_0201_10V6K GPU_DPC_TX1_DP_C 1 2 GPU_DPC_TX1_DP_CON
25 GPU_DPC_TX1_DP 1 2 S

G1

G2

4
@ 2

6
GPU_DPC_TX1_DN C350 2 1 0.1u_0201_10V6K GPU_DPC_TX1_DN_C 4 3 GPU_DPC_TX1_DN_CON GPU_DPC_AUX_DP 1 6 3 4 GPU_DPC_AUX_DP_C D
25 GPU_DPC_TX1_DN 4 3 S1 D1 D2 S2 HDMI_DONGLE_DETECT
2
EXC24CH900U_4P G
R50 1 2 0_0402_5% PJT7838_SOT363-6 PJT7838_SOT363-6 1
Vgs(th)≤1V Q187A Q187B S 2N7002KDWH_SOT363-6 C10150

1
Q193A 0.01U_50V_K_X7R_0402

R10221 1 2 0_0402_5% 2

L92
GPU_DPC_TX0_DP C353 2 1 0.1u_0201_10V6K GPU_DPC_TX0_DP_C 1 2 GPU_DPC_TX0_DP_CON
25 GPU_DPC_TX0_DP 1 2
@
GPU_DPC_TX0_DN C352 2 1 0.1u_0201_10V6K GPU_DPC_TX0_DN_C 4 3 GPU_DPC_TX0_DN_CON
25 GPU_DPC_TX0_DN 4 3
EXC24CH900U_4P
R10222 1 2 0_0402_5%
C C

+1.8VS_AON
1

R317
u date by Hui 10K_0402_5%

0180801
2

IFPE_HPD
29 IFPE_HPD

Q181
MMBT3904WH_SOT323-3
1

C
2 R318 1 2 100K_0402_5% R319 1 2 0_0402_5% DP_HPD_CON
B
3

1 1
R324 C366 C367
100K_0402_5% 220P_0402_50V7K 220P_0402_50V7K
2 2
2

+5VS

+3VS
2

+3VS_DP
G
3

DP_HPD DP_HPD_CON
1

R10223 1 2 0_0402_5%
15 DP_HPD
S

F1
1 3 1 2

S
Q192
2

PJA138K_SOT23-3 1.1A_8V_1206L110THYR 1 1
B R311 C369 C368 B

G
2
10K_0402_5% Q196 10U_0805_10V6K .1U_0402_10V6-K
@ LP2301ALT1G_SOT23-3
2 2
1

VCCCPUCORE_VIN +3VS
44,53,54 SUSP
1

D3
DP_HPD_CON 1 1 10 9 DP_HPD_CON R10240
100K_0402_5%

2
+3VS_DP 2 2 9 8 +3VS_DP JDP1
V0 R10410 500mA
2

GPU_DPC_TX2_DN_CON 4 4 7 7 GPU_DPC_TX2_DN_CON DP_HPD_CON 2 20

0_0402_5% Add by Bing 08 8
1

+3VS Q191 D HOT_PLUG DP_PWR 19

GPU_DPC_TX2_DP_CON 5 5 GPU_DPC_TX2_DP_CON GPU_DIS_PWR_EN 2 GPU_DPC_AUX_DP_CON GND6
6 6 16 14

1
G GPU_DPC_AUX_DN_CON 18 AUX_CH_P GND5 6 R326 1 2 1M_0402_5%
3 3 AUX_CH_N CONFIG2 4 HDMI_DONGLE_DETECT
CONFIG1
1

S L2N7002KWT1G_SOT323-3 GPU_DPC_TX3_DP_CON 10 13
3

8 GPU_DPC_TX3_DN_CON 12 ML_LANE3_P GND4 8

Modified by Bing R10334 @
R10241
10K_0402_5%

1M_0402_5% ML_LANE3_N GND3 7

20180316 GPU_DPC_TX2_DP_CON GND2
For EMC 15
ML_LANE2_P GND1
1 Add DP++ function-Harry 10/

1
AZ1045-04F_DFN2510P10E-10-9 +1.8VS_VGA GPU_DPC_TX2_DN_CON 17 Low : DP ort enable
2

ML_LANE2_N

R325
1M_0402_5%
EMC_NS@ 21
R315 1 2 100K_0402_5%GPU_DPC_AUX_DN_C GPU_DPC_TX1_DP_CON 9 GND7 High: HDMI ort enable
ML_LANE1_P
3

D GPU_DPC_TX1_DN_CON 11 22
1

5 Q190B R316 1 2 100K_0402_5%GPU_DPC_AUX_DP_C ML_LANE1_N GND8

2
G GPU_DPC_TX0_DN_CON 5 23
R10242
10K_0402_5%

LBSS138DW1T1G_SOT363-6 ML_LANE0_N GND9

D5 S GPU_DPC_TX0_DP_CON 3
4

GPU_DPC_TX3_DP_CON 1 1 GPU_DPC_TX3_DP_CON ML_LANE0_P

10 9 24
GND10
2

GPU_DPC_TX3_DN_CON 2 2 9 8 GPU_DPC_TX3_DN_CON
ALLTO_C17717-120A9-L
6

GPU_DPC_AUX_DP_CON 4 4 GPU_DPC_AUX_DP_CON D
7 7 ME@
2 Q190A
GPU_DPC_AUX_DN_CON 5 5 6 6 GPU_DPC_AUX_DN_CON G +3VS
LBSS138DW1T1G_SOT363-6
S
1

3 3

AZ1045-04F_DFN2510P10E-10-9 For EMC Q1951

EMC_NS@
D
HD_DET 2 @
G PJA138K_SOT23-3
D6 S
A GPU_DPC_TX1_DN_CON 1 1 10 9 GPU_DPC_TX1_DN_CON A
3
GPU_DPC_TX1_DP_CON 2 2 9 8 GPU_DPC_TX1_DP_CON

GPU_DPC_TX0_DN_CON 4 4 7 7 GPU_DPC_TX0_DN_CON
1

GPU_DPC_TX0_DP_CON 5 5 6 6 GPU_DPC_TX0_DP_CON
R10336 R10335
3 3 2.2K_0402_5% 2.2K_0402_5%
2

8
@ @
For EMC
AZ1045-04F_DFN2510P10E-10-9 GPU_DPC_AUX_DN_C
EMC_NS@
GPU_DPC_AUX_DP_C
Security Classification LC Future Center Secret Data Title
Issued Date 2018/08/02 Deciphered Date 2018/08/02 DP
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 43 of 77
5 4 3 2 1
 5 4 3 2 1

+1.8VS_AON

1
RRE59
10K_0402_5%
R10498 2 @ 1 0_0402_5%
u date by bing
018031

2
EMC@
HDMI1_TX0- CRE261 2 0.1u_0201_10V6K HDMI1_TX0-_C L89 1 2 HDMI1_TX0-_R IFPC_HPD
25 HDMI1_TX0- 1 2 29 IFPC_HPD

HDMI D0 HDMI1_TX0+ CRE251 2 0.1u_0201_10V6K HDMI1_TX0+_C 4 3 HDMI1_TX0+_R QRE3

25 HDMI1_TX0+ 4 3 MMBT3904WH_SOT323-3

1
EXC24CH500U_4P C
D R10505 2 @ 1 0_0402_5% 2 RRE57 1 2 100K_0402_5% RRE58 1 2 0_0402_5% HDMI1_HPD_CON D
B

3
1 1

1
CRE9 CRE10
RRE56 220P_0402_50V7K 220P_0402_50V7K
100K_0402_5% @
R10499 2 @ 1 0_0402_5% 2 2

2
EMC@
HDMI1_TX1- CRE281 2 0.1u_0201_10V6K HDMI1_TX1-_C L91 1 2 HDMI1_TX1-_R
25 HDMI1_TX1- 1 2
HDMI D1 HDMI1_TX1+ CRE271 2 0.1u_0201_10V6K HDMI1_TX1+_C 4 3 HDMI1_TX1+_R +3VS
25 HDMI1_TX1+ 4 3 V0
EXC24CH500U_4P
R10504 2 @ 1 0_0402_5%

R10500 2 @ 1 0_0402_5%

EMC@ HPD

1
HDMI1_TX2- CRE301 2 0.1u_0201_10V6K HDMI1_TX2-_C L90 1 2 HDMI1_TX2-_R
25 HDMI1_TX2- 1 2
HDMI D2 RRE61

2
1M_0402_5%
HDMI1_TX2+ HDMI1_TX2+_C HDMI1_TX2+_R

G
25 HDMI1_TX2+ CRE291 2 0.1u_0201_10V6K 4 3
4 3

3
HDMI_HPD HDMI1_HPD_CON

1
EXC24CH500U_4P
15 HDMI_HPD
R10503 2 @ 1 0_0402_5%

D
R10501 2 @ 1 0_0402_5% QRE5

1
PJA138K_SOT23-3
EMC@ RRE71
HDMI1_TXC- CRE321 2 0.1u_0201_10V6K HDMI1_CLK-_C L88 1 2 HDMI1_CLK-_R 100K_0402_5%
25 HDMI1_TXC- 1 2

2
HDMI1_TXC+ CRE311 2 0.1u_0201_10V6K HDMI1_CLK+_C 4 3 HDMI1_CLK+_R
HDMI CLK 25 HDMI1_TXC+ 4 3
EXC24CH500U_4P
R10502 2 @ 1 0_0402_5% V0
C C

HDMI1_TX0+_C R10337 1 2 499_0402_1% HDMI1_TX0+_B R10426 1 2 0_0402_5%

HDMI1_TX0-_C R10338 1 2 499_0402_1% HDMI1_TX0-_B R10427 1 2 0_0402_5%

HDMI1_TX1+_C R10339 1 2 499_0402_1% HDMI1_TX1+_B R10428 1 2 0_0402_5%

HDMI1_TX1-_C R10340 1 2 499_0402_1% HDMI1_TX1-_B R10429 1 2 0_0402_5%

HDMI1_TX2+_C R10341 1 2 499_0402_1% HDMI1_TX2+_B R10430 1 2 0_0402_5%

HDMI1_TX2-_C R10342 1 2 499_0402_1% HDMI1_TX2-_B R10431 1 2 0_0402_5%

HDMI1_CLK+_C R10343 1 2 499_0402_1% HDMI1_CLK+_B R10432 1 2 0_0402_5%

HDMI1_CLK-_C R10344 1 2 499_0402_1% HDMI1_CLK-_B R10433 1 2 0_0402_5%

V1 0

+5VS +5VS_HDMI1_F +5VS_HDMI1

1

D Q13 QRE4
+3VS 2 LP2301ALT1G_SOT23-3
G 2N7002KW_SOT323-3 F2
1 3 1 2

S
S
3

1.1A_8V_1206L110THYR
R42 1 @ 2

G
2
100K_0402_5%
43,53,54 SUSP
B B

2
D46 @ R10539 R10540 @
HDMI1_HPD_CON 1 1 10 9 HDMI1_HPD_CON 0_0805_5% 0_0805_5% 1
CRE11
HDMI1_DAT_CON 2 2 9 8 HDMI1_DAT_CON D4321 D4322 .1U_0402_10V6-K

1
RB751V-40_SOD323-2 RB751V-40_SOD323-2
HDMI1_CLK_CON 4 4 7 7 HDMI1_CLK_CON V1 0 2

+5VS_HDMI1 5 5 6 6 +5VS_HDMI1

1
3 3 NV suggestion
RRE15 RRE16
8 2.2K_0402_5% 2.2K_0402_5%

2
AZ1045-04F_DFN2510P10E-10-9 JHDMI1
HDMI1_HPD_CON 19
EMC_NS@ Hot_Plug_Detect
18
17 +5V_Power
+1.8VS_VGA +1.8VS_AON +1.8VS_VGA +1.8VS_AON HDMI1_DAT_CON 16 DDC/CEC_GND
D47 HDMI1_CLK_CON 15 SDA
HDMI1_TX0-_R 1 1 HDMI1_TX0-_R SCL
10 9 14
13 Utility 20
CEC GND1
2

HDMI1_TX0+_R 2 2 9 8 HDMI1_TX0+_R HDMI1_CLK-_R R10326 1 2 1/16W_6.8_5%_0402 HDMI1_CLK-_CON 12

R10537 R10538 R10535 R10536 11 TDMS_Clock- 21
HDMI1_CLK-_R 4 4 HDMI1_CLK-_R HDMI1_CLK+_R HDMI1_CLK+_CON TDMS_Clock_Shield GND2
7 7 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5% R10325 1 2 1/16W_6.8_5%_0402 10
HDMI1_TX0-_R R10320 1 2 1/16W_6.8_5%_0402 HDMI1_TX0-_CON 9 TDMS_Clock+ 22
HDMI1_CLK+_R 5 5 HDMI1_CLK+_R TDMS_Data0- GND3
6 6 8
1

HDMI1_TX0+_R R10319 1 2 1/16W_6.8_5%_0402 HDMI1_TX0+_CON 7 TDMS_Data0_Shield 23

3 3 AUX V1 0 V1 0 HDMI1_TX1-_R R10322 1 2 1/16W_6.8_5%_0402 HDMI1_TX1-_CON 6
5
TDMS_Data0+
TDMS_Data1-
GND4

8 HDMI1_TX1+_R R10321 1 2 1/16W_6.8_5%_0402 HDMI1_TX1+_CON 4 TDMS_Data1_Shield

TDMS_Data1+
1

NV suggestion HDMI1_TX2-_R R10324 1 2 1/16W_6.8_5%_0402 HDMI1_TX2-_CON 3

RRE55 RRE54 2 TDMS_Data2-
HDMI1_TX2+_R R10323 1 2 1/16W_6.8_5%_0402 HDMI1_TX2+_CON 1 TDMS_Data2_Shield
AZ1045-04F_DFN2510P10E-10-9 For EMC 10K_0402_5% 10K_0402_5%
TDMS_Data2+
2

EMC_NS@
ALLTO_C128AU-K1939-L
G1

ME@
HDMI1_DAT_CON 6 1
D1 S1 HDMI1_DAT 25
A D48 A
HDMI1_TX1-_R 1 1 10 9 HDMI1_TX1-_R PJT7838_SOT363-6
QRE2A
HDMI1_TX1+_R 2 2 9 8 HDMI1_TX1+_R
5

HDMI1_TX2-_R 4 4 7 7 HDMI1_TX2-_R
G2

HDMI1_TX2+_R 5 5 6 6 HDMI1_TX2+_R HDMI1_CLK_CON 3 4

D2 S2 HDMI1_CLK 25
3 3
Vgs(th)≤1V PJT7838_SOT363-6
8 QRE2B
For EMC Security Classification LC Future Center Secret Data Title

AZ1045-04F_DFN2510P10E-10-9 Issued Date 2018/08/02 Deciphered Date 2018/08/02 HDMI_CONN

EMC_NS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 2.0

Date: Friday, March 22, 2019 Sheet 44 of 77

5 4 3 2 1
 A B C D E

+3VS_WLAN

Mini-Express Card(WLAN/WiMAX)

0.1u_0201_10V6K

10U_0603_6.3V6M

4.7U_0603_6.3V6K
1 1 2 1

1U_0402_10V6K
C10184

C10185

C10235

C10236
@ @

2@ 2@ 1 2
JWLAN2 +3VS

1 2
USB20_P14 3 GND1 3.3VAUX1 4
19 USB20_P14 USB20_N14 USB_D+ 3.3VAUX2
5 6 1 @ T1
19 USB20_N14 USB_D- LED1#

49.9K_0402_1%
7 8
GND2 PCM_CLK/I2S_SCK

1
CNVI_WR_D1_N 9 10 R10381 1 2 0_0402_5%
19 CNVI_WR_D1_N CNVI_WR_D1_P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET# 16
11 12

R344
19 CNVI_WR_D1_P SDIO_CMD PCM_IN/I2S_SD_IN
13 14 R10392 1 2 0_0402_5%
CNVI_WR_D0_N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ 16
15 16 1 @ T2
19 CNVI_WR_D0_N CNVI_WR_D0_P SDIO_DATA1 LED#2
17 18
19 CNVI_WR_D0_P

2
19 SDIO_DATA2 GND11 20
CNVI_WR_CLK_N 21 SDIO_DATA3 UART_WAKE# 22 R10382 1 CNVI@ 2 22_0402_5%
19 CNVI_WR_CLK_N CNVI_WR_CLK_P SDIO_WAKE# UART_RXD CNVI_BRI_RSP 19 PCH_UART2_RXD 20
23
19 CNVI_WR_CLK_P SDIO_RESET# +3VS

1 1

49.9K_0402_1%
K Y

1
5 PIN ~PIN31 NC PIN
7

R345
9 8
31 30

2
33 32 PCH_UART2_TXD 20
GND3 UART_TXD CNVI_RGI_DT 19
35 34 R10385 1 CNVI@ 2 22_0402_5%
+3VS +3VS_WLAN 14 PCIE_PTX_C_DRX_P13 PETP0 UART_CTS CNVI_RGI_RSP 19
37 36
14 PCIE_PTX_C_DRX_N13 PETN0 UART_RTS EC_TX_RSVD EC_TX CNVI_BRI_DT 19
39 38 R2075 1 @ 2 0_0402_5%
41 GND4 VENDOR_DEFINED1 40 EC_RX_RSVD R2067 1 2 0_0402_5% EC_RX
WLAN 14 PCIE_PRX_DTX_P13
@

2
43 PERP0 VENDOR_DEFINED2 42
14 PCIE_PRX_DTX_N13 change EC_RX/TX to pin58/60 for new debug card

2
Q165 R2072 45 PERN0 VENDOR_DEFINED3 44
G
GND5 COEX3 EC_TX 48,49 2017_0802
10K_0402_5% 47 46
17 CLK_PCIE_WLAN REFCLKP0 COEX2 EC_RX 48,49
49 48
17 CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 R2076 1 2 0_0402_5%
SUSCLK 16

1
3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST# +3VS_WLAN
17 WLAN_CLKREQ# CLKREQ0# PERST0# BT_OFF# PCH_BT_OFF# PLT_RST# 18,29,49,50,51
S

D
R401 1 AOAC@ 2 0_0402_5% 55 54 R2070 1 2 1K_0402_5%
16,49 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_WLAN_OFF# PCH_BT_OFF# 20,45
L2N7002KWT1G_SOT323-3 R2071 1 @ 2 0_0402_5% 57 56 R2066 1 2 0_0402_5%
49,51 LAN_WAKE# GND7 W_DISABLE1# PCH_WLAN_OFF# 20,45
@

10K_0201_5% RH856

RH855
1
@ CNVI_WT_D1_N 59 58 EC_RX modify by Grace V0
19 CNVI_WT_D1_N RSRVD/PETP1 I2C_DATA

1
R80 1 2 0_0402_5% CNVI_WT_D1_P 61 60 EC_TX
19 CNVI_WT_D1_P RSRVD/PETN1 I2C_CLK
63 62

10K_0201_5%
CNVI_WT_D0_N 65 GND8 ALERT# 64
19 CNVI_WT_D0_N CNVI_WT_D0_P RSRVD/PERP1 RSRVD CLKIN_XTAL_LCP 17
67 66
If su ort A AC NC R80 19 CNVI_WT_D0_P

2
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN
if not su ort A AC stuff R80

2
GND9 UIM_POWER_SNK/CLKREQ1#

1
CNVI_WT_CLK_N 71 70
19 CNVI_WT_CLK_N CNVI_WT_CLK_P RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# PCH_BT_OFF#
73 72 R2073
19 CNVI_WT_CLK_P RSRVD/REFCLKN1 3.3VAUX3 PLT_RST# PCH_WLAN_OFF#
75 74 100K_0402_5%
GND10 3.3VAUX4
77 76 1

2
GND15 GND14 C381
1000P_0402_50V7K

ARGOS_NASE0-S6701-TS40 2 modify by Grace V0

ME@

1 1

1U_0402_10V6K

0.1u_0201_10V6K
C10186

C10187
2@ 2@

+3VS +3VS_WLAN

J3 Don't short
1 2
1 2 JUMP_43X79
@
+3VALW
J8 Need short
1 2
+3VALW 1 2 JUMP_43X79
@
+3VALW
1

2 R2225 U4403 2
R2234
75K_0402_5% 5 1 1 2
@ IN OUT
0.01_0603_1%
2
2

GND @
1
WLAN_PWR_EN

C2212
0.01U_0402_25V7K
4 3
EN OCB
1
1

D R2229 SY6288C20AAC_SOT23-5 2@
2 Q2202 200K_0402_5% @
15 CNVI_EN#
G 2N7002KW_SOT323-3 @
1

@
2

R2226 S
3

75K_0402_5%
@
2

R2223 1 @ 2 0_0402_5%
16 PM_SLP_WLAN#

R2233 1 @ 2 0_0402_5%
49,65,68 SUSP#

1
@
C10245
0.033U_25V_K_X7R_0402
2

M.2 SSD(SATA/PCIE)
+3VS +3.3V_NGFF

2A
R94 1 2 0_0805_5%
C239
22U_0603_6.3V6-M

V1 0 1 1 1
C240
4.7U_0402_6.3V6M

@ C241
.1U_0402_10V6-K
OPTANE@
2 2 2

JSSD1
NGFF +3.3V_NGFF

1 2
3 GND_1 3.3V_1 4
PCIE_PRX_DTX_N9 5 GND_2 3.3V_2 6
14 PCIE_PRX_DTX_N9 PERN3 N/C_2 2
PCIE_PRX_DTX_P9 7 8 C238
3 14 PCIE_PRX_DTX_P9 PERP3 N/C_3 3
9 10 .1U_0402_10V6-K
PCIE_PTX_DRX_N9 CC170 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N9_C 11 GND_3 DAS/DSS# 12
14 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 PCIE_PTX_DRX_P9_C PETN3 3.3V_3 1
CC171 2 1 0.22U_0201_6.3V6-K 13 14
14 PCIE_PTX_DRX_P9 PETP3 3.3V_4 +3.3V_NGFF
15 16
PCIE_PRX_DTX_N10 17 GND_4 3.3V_5 18
14 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PERN2 3.3V_6
19 20
14 PCIE_PRX_DTX_P10 PERP2 N/C_4
21 22
PCIE_PTX_DRX_N10 CC168 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N10_C 23 GND_5 N/C_5 24
14 PCIE_PTX_DRX_N10 PETN2 N/C_6
1

PCIE_PTX_DRX_P10 CC169 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P10_C 25 26

14 PCIE_PTX_DRX_P10 PETP2 N/C_7
27 28 R95
PCIE_PRX_DTX_N11 29 GND_6 N/C_8 30 10K_0201_5%
14 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERN1 N/C_9
31 32 @
14 PCIE_PRX_DTX_P11 PERP1 N/C_10
33 34
2

PCIE_PTX_DRX_N11 CC166 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N11_C 35 GND_7 N/C_11 36

14 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PTX_DRX_P11_C PETN1 N/C_12 DEVSLP1_R
CC167 2 1 0.22U_0201_6.3V6-K 37 38 R96 1 @ 2 0_0201_5% DEVSLP1
14 PCIE_PTX_DRX_P11 PETP1 DEVSLP DEVSLP1 15
39 40
PCIE_SATA_PRX_DTX_P12 41 GND_8 N/C_13 42
14 PCIE_SATA_PRX_DTX_P12 PCIE_SATA_PRX_DTX_N12 PERN0/SATA-B+ N/C_14
43 44
14 PCIE_SATA_PRX_DTX_N12 PERP0/SATA-B- N/C_15
1

45 46
PCIE_SATA_PTX_DRX_N12 CC39 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_N12_C 47 GND_9 N/C_16 48 R97
14 PCIE_SATA_PTX_DRX_N12 PCIE_SATA_PTX_DRX_P12 PCIE_SATA_PTX_DRX_P12_C PETN0/SATA-A- N/C_17 PLT_RST#
CC165 2 1 0.22U_0201_6.3V6-K 49 50 10K_0201_5%
14 PCIE_SATA_PTX_DRX_P12 PETP0/SATA-A+ PERST# SSD_CLKREQ#
51 52
CLK_PCIE_SSD# GND_10 CLKREQ# SSD_CLKREQ# 17
53 54 1 1
17 CLK_PCIE_SSD#
2

CLK_PCIE_SSD 55 REFCLKN PEWAKE# 56 @ C382

17 CLK_PCIE_SSD REFCLKP N/C_18
+3.3V_NGFF 57 58 TP76 1000P_0402_50V7K
GND_11 N/C_19
1

59 NC NC 0 2
R274 1 NC NC
10K_0201_5% 3 NC NC
5 NC NC
67 68 +3.3V_NGFF
2

PEDET 69 N/C_1 SUSCLK 70

71 PEDET 3.3V_7 72
73 GND_12 3.3V_8 74
GND_13 3.3V_9
0.1u_0201_10V6K

C255
22U_0603_6.3V6-M

75 1 1 1
1

GND_14
0.01U_0201_10V6K
C310

PEDET (PE_DTCT) R290 77 76

C237

10K_0201_5% PEG1 PEG2

OPTANE@

OPTANE@

OPTANE@

SATA Device GND @ 2 2 2

PCIe Device Open
2

ARGOS_NASM0-S6701-TS40
ME@
SSD_DET#
0 - SATA
1 - PCIE

+3VALW_PCH
2

RV1284
10K_0402_5%
+3.3V_NGFF @
1
2

RV1285
SSD_DET# 14
10K_0402_5%

4 @ 4
3
1

QV48B
D2

5 PJT7838_SOT363-6
G2
@
S2
4
6

QV48A
D1

PEDET 2 PJT7838_SOT363-6
G1
@
S1
1

Vgs(th)≤1.0V
R249 1 2 0_0402_5%
modify by grace 1 /
Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 NGFF WLAN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 2.0

Date: Friday, March 22, 2019 Sheet 45 of 77

A B C D E
 A B C D E F G H

SATA HDD Conn.

+5VS

V1 0
JHDD1

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201
0.1U_6.3V_K_X5R_0201
R342 1 2 0_0805_5% 1

10U_0805_10V6K

10U_0805_10V6K
1 1 1 1 1 1 1 +5VS 1

C10237

C10238

C10239

C10240

C10243

C10244
1 2 1
C77 3 2
@ @ @ 4 3
2 2 2 2 2 2 2 SATA_PRX_DTX_P4 C69 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P4 5 4
RF@ RF@ 14 SATA_PRX_DTX_P4 SATA_PRX_DTX_N4 C68 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N4 6 5
14 SATA_PRX_DTX_N4 7 6
SATA_PTX_DRX_N4 C67 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_N4 8 7 12
14 SATA_PTX_DRX_N4 8 GND2
SATA_PTX_DRX_P4 C66 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P4 9
14 SATA_PTX_DRX_P4 9
10 11
10 GND1

HIGHS_FC5AF101-2931H
ME@

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 HDD/XBOX CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 46 of 77
A B C D E F G H
 A B C D E

+USB_VCCA

C59 1 2 220U_B2_6.3VM_R35M

+
C62 1 2
1 1
@ 1U_0603_25V6M

C63 1 2
@ 470P_0402_50V7K

JUSB2
1
USB20_N1_B R71 1 @ 2 0_0402_5% USB20_N1_R 2 VBUS
USB20_P1_B R70 1 @ 2 0_0402_5% USB20_P1_R 3 D-
4 D+
USB30_RX_N3 R73 2 1 0_0402_5% USB30_RX_R_N3 5 GND1
15 USB30_RX_N3 USB30_RX_P3 2 1 0_0402_5% USB30_RX_R_P3 6 SSRX- 10
R72
15 USB30_RX_P3 SSRX+ GND3
7 11
USB30_TX_N3 C65 1 2 .1U_0402_10V6-K USB30_TX_C_N3 R69 2 1 0_0402_5% USB30_TX_R_N3 8 GND2 GND4 12
15 USB30_TX_N3 USB30_TX_P3 1 2 .1U_0402_10V6-K USB30_TX_C_P3 2 1 0_0402_5% USB30_TX_R_P3 9 SSTX- GND5 13
C64 R68
15 USB30_TX_P3 SSTX+ GND6
V1 0
ALLTO_C107MJ-10939-L
ME@

USB20_P1_R
+USB_VCCA
USB20_N1_R
3

2 2
1

D63
AZC199-02S.R7G_SOT23-3 D11
1

EMC@ AZ5725-01F.R7GR_DFN1006P2X2
EMC@

USB charger
2

2.5A
2

+5VALW
1

U3

C197 2 1 .1U_0402_16V7K 1 16 ILIM_HI R2047 1 2 20K_0402_1%

@ IN ILIM_HI
USB20_N1 2 15 ILIM_LO R2048 1 @ 2 20K_0402_1%
19 USB20_N1 DM_OUT ILIM_LO
USB20_P1 3 14
19 USB20_P1 DP_OUT GND
ILIM_SEL 4 13
ILIM_SEL FAULT USB_OC2# 19
5 12 +USB_VCCA
49 USB_CHG_EN EN OUT
D12
USB30_RX_R_N3 10 1 USB30_RX_R_N3 CHG_MOD1 6 11 USB20_N1_B
NC1 Line-1 49 CHG_MOD1 CLT1 DM_IN
USB30_RX_R_P3 9 2 USB30_RX_R_P3 CHG_MOD2 7 10 USB20_P1_B
NC2 Line-2 CLT2 DP_IN

E_PAD
USB30_TX_R_N3 7 4 USB30_TX_R_N3 CHG_MOD3 8 9 STATUS#
NC3 Line-3 49 CHG_MOD3 CLT3 STATUS STATUS# 49
USB30_TX_R_P3 6 5 USB30_TX_R_P3
NC4 Line-4 SN1702001RTER_WQFN16_3X3

17
3
GND1
8
GND2
AZ1143-04F-R7G_DFN2510P10E10
3 EMC@ 3
+5VALW

For EMC +5VALW

V0
RP3
ILIM_SEL 1 4 STATUS# R10394 2 1 10K_0402_5%
CHG_MOD2 2 3
L9 for placement optimization
EXC24CH900U_4P 10K_0404_4P2R_5% [close to EC side]
USB30_RX_P3 4 3 USB30_RX_R_P3
4 3
ILIM_SEL R2065 2 @ 1 10K_0402_5%
USB30_RX_N3 1 2 USB30_RX_R_N3
1 2 CHG_MOD2 R10356 2 @ 1 10K_0402_5%
@ CLT1 CLT2 CLT3 ILIM_SEL MOD
USB_CHG_EN R2052 2 1 10K_0402_5%
L10
EXC24CH900U_4P 0 0 0 X DCH OUT held low
USB30_TX_C_P3 4 3 USB30_TX_R_P3
4 3

USB30_TX_C_N3 1 2 USB30_TX_R_N3
* 1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active
1
@
2
* 1 1 1 0 SDP2 Data Connected

L11
EXC24CH900U_4P
* 1 1 0 X SDP1 Data Connected
USB20_P1_B 4 3 USB20_P1_R
4 3
* 0 1 0 X SDP1 Data Connected
USB20_N1_B 1 2 USB20_N1_R
1 2
EMC@ 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

For EMC 1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode
4 4

* 0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB2.0/USB3.0 PORT (LEFT)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 47 of 77

A B C D E
 5 4 3 2 1

+USB_VCCD

C55 1 2 220U_6.3V_M

+
USB3.1 PORT x1
C56 1 2
@ 1U_0603_25V6M Low Active 1.8A
+5VALW +USB_VCCD
C57 1 2
@ 470P_0402_50V7K U125
5 1
IN OUT
D D
JUSB1 2 2
USB30_TX_P1 C79 1 2 .1U_0402_10V6-K USB30_TX_C_P1 R74 2 1 0_0402_5% USB30_TX_R_P1 9 C10159 GND
15 USB30_TX_P1 StdA_SSTX+ USB_OC3#
1 1U_0402_16V6K 4 3
USB30_TX_N1 C80 1 2 .1U_0402_10V6-K USB30_TX_C_N1 R76 2 1 0_0402_5% USB30_TX_R_N1 8 VBUS ENB OCB USB_OC3# 19
15 USB30_TX_N1 USBP2+_S USBP2+_S_R StdA_SSTX- 1
R64 1 @ 2 0_0402_5% 3 G517E2T11U_SOT23-5 1
UARTA_P80_EN 7 D+ C10158
USBP2-_S R65 1 @ 2 0_0402_5% USBP2-_S_R 2 GND_DRAIN 10 1000P_0402_50V7K
USB30_RX_P1 R79 2 1 0_0402_5% USB30_RX_R_P1 6 D- GND_2 11 @
15 USB30_RX_P1 4 StdA_SSRX+ GND_3 12 2
USB30_RX_N1 R78 2 1 0_0402_5% USB30_RX_R_N1 5 GND_1 GND_4 13 USB_ON#
15 USB30_RX_N1 StdA_SSRX- GND_5 49,50 USB_ON#
ALLTO_C190DU-10939-L
V1 0 ME@

1
R537 R538

2 Debug@
100K_0402_5%
USB@

0_0402_5%
1

For USB Debug Function

2 Debug@ 1 USB_UART_SEL
20 USBDEBUG
C R531 0_0402_5% C

D24
USB30_RX_R_N1 10 1 USB30_RX_R_N1 USBP2+_S_R +USB_VCCD
NC1 Line-1
USB30_RX_R_P1 9 2 USB30_RX_R_P1 USBP2-_S_R
NC2 Line-2
U129
3

USB30_TX_R_N1 7 4 USB30_TX_R_N1

1
NC3 Line-3
USB30_TX_R_P1 6 5 USB30_TX_R_P1

1
NC4 Line-4 D62 D65 R533 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 R104562 Debug@ 1 0_0402_5%
45,49 EC_TX 1D+ VCC +3VALW
3 AZC199-02S.R7G_SOT23-3 AZ5725-01F.R7GR_DFN1006P2X2
GND1 EMC@ EMC@ R536 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL
8 45,49 EC_RX 1D- S
GND2
2
3 8 USBP2+_S
19 USB20_P0 2D+ D+
AZ1143-04F-R7G_DFN2510P10E10 NCY3958Y
2

4 7 USBP2-_S
EMC@ 19 USB20_N0 2D- D-
5 6
1

Moddify by grace on 1 /31 V0 GND1 OE#

11
GND2
for EMC

L15 NCT3958Y_DFN10_3X3
EXC24CH900U_4P Debug@
USB30_RX_N1 4 3 USB30_RX_R_N1
4 3

USB30_RX_P1 1 2 USB30_RX_R_P1
1 2
@
USB20_P0 2 USB@ 1 USBP2+_S
L16 R539 0_0402_5%
EXC24CH900U_4P
USB30_TX_C_N1 4 3 USB30_TX_R_N1 USB20_N0 2 USB@ 1 USBP2-_S
B 4 3 R541 0_0402_5%
B
USBDEBUG Kernel debug
USB30_TX_C_P1 1 2 USB30_TX_R_P1
1 2 Set in ut Set in ut
@
Set out ut Low NABL
L8
EXC24CH900U_4P
USBP2-_S 4 3 USBP2-_S_R +3VALW
4 3

USBP2+_S 1 2 USBP2+_S_R
1 2 UARTA_P80_EN POST 80

1
for EMC EMC@
Set in ut DISABL R547
Debug@ 10K_0402_5%
Set out ut Low NABL

2
USB_UART_SEL

1
D
UARTA_P80_EN 2
OE# S FUNCTION G L2N7002KWT1G_SOT323-3
Q56
H X DISABL S Debug@

3
L L D +/- to 1D +/-

L H D +/- to D +/-

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 USB2.0

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 48 of 77

5 4 3 2 1
 5 4 3 2 1

+3VALW_R 1 2 0_0603_5%
For EMI +VFSPI RE1 +3VL 0.5A

+3VALW RE75 1 @ 2 0_0402_5% RE3 1 2 0_0603_5%

+3VALW
@
2 @ 1 RE2 CLK_PCI_EC
+3VALW_R +3VALW_R +3VALW_EC
10_0402_5% RE97 2 1 0_0402_5%
1
@ V1 0For SPI ROM Mirror RE4 1 2 0_0603_5%
CE2 +3VALW_R All capacitors close to EC
10P_0402_50V8J V1 0 1 1
2 @ CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
+VFSPI .1U_0402_10V6-K CE5
EMC_NS@ 220P_0402_50V7K 2 1 CE24 LPC_FRAME# Close EC +3VS
1
CE6
1
CE7
1
CE8
1
CE9
1
CE10
1
CE11 1000P_0402_50V7K
+3VALW_EC RE6 1 2 0_0603_5% 2 EC_AGND 2 +3VS
D LPC_AD3 D
EMC_NS@ 220P_0402_50V7K 2 1 CE25 CE3 CD@ @ @
PLT_RST# 1 2 VCOREVCC 2 2 2 2 2 2
EMC_NS@ 220P_0402_50V7K 2 1 CE26 LPC_AD2
1 .1U_0402_10V6-K EC_AGND
CE1 EMC_NS@ 220P_0402_50V7K 2 1 CE27 LPC_AD1
1000P_0402_50V7K RP1
EMC_NS@ 220P_0402_50V7K 2 1 CE28 LPC_AD0 EC_FAN2_SPEED 1 4
minimum trace width 12 mil

121
127
114
106
2 EC_FAN1_SPEED 2 3

12

11

26
50
92

74
UE1
10K_0404_4P2R_5%
Reserved Cap HLZ SDV 0616

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY(PLL)5
VSTBY6
VCC

VFSPI

AVCC
VCORE
change CE1 from @ to stuff due to signal waveform abnormal EC_FAN2_PWM RE65 1 @ 2 10K_0402_5%
HLZ SIV 0811
EC_FAN1_PWM RE11 1 @ 2 10K_0402_5%
24 WRST# PWR_LED1#
KBRST# 4 24
+3VALW_R 15 KBRST# 5 KBRST#/GPB6 PWM0/GPA0 25 PWR_LED2 PWR_LED1# 50 LPC_FRAME# 1 2 10K_0402_5%
SERIRQ RE7 @
15 SERIRQ LPC_FRAME# ALERT#/SERIRQ/GPM6 PWM1/GPA1 BATT_LOW_LED# PWR_LED2 39
6 28
15 LPC_FRAME# LPC_AD3 7 ECS#/LFRAME#/GPM5 PWM2/GPA2 29 BATT_LOW_LED# 50
RE107 2 @ 1 0_0402_5% ENBKL RE9 1 @ 2 100K_0402_5%
15 LPC_AD3 LPC_AD2 EIO3/LAD3/GPM3 PWM3/GPA3 EC_FAN2_PWM LED_KB_PWM 50,58
DE1 1 2 @ 8 PWM 30
15 LPC_AD2 LPC_AD1 EIO2/LAD2/GPM2 PWM4/GPA4 EC_FAN1_PWM EC_FAN2_PWM 55
9 31
15 LPC_AD1 LPC_AD0 10 EIO1/LAD1/GPM1 PWM5/GPA5 32 EC_FAN1_PWM 55
BEEP#
RB751V-40_SOD323-2 15 LPC_AD0 CLK_PCI_EC EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 BATT_CHG_LED# BEEP# 54 +3VALW
13 LPC 34
1 2 100K_0402_5% 15 CLK_PCI_EC 14 ESCK/LPCCLK/GPM4 PWM7/RIG1#/GPA7 120 2 0_0402_5%BATT_CHG_LED# 50
RE8 WRST# RE100 1 RTS5455_SM_INT 14,41
EC_SMI# 15 WRST# GPC4 124 SUSP#
15 EC_SMI# EC_RX PLTRST#/ECSMI#/GPD4 GPC6 SUSP# 45,53,65,68
1 16 RE106 2 1 0_0402_5% AGKB_INT 58
45,48 EC_RX EC_TX 17 SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 66 NTC_V1_GPU EC_ON_1.8V 1 2
NTC_V1_GPU 55 RE98 @ 10K_0402_5%
CE12 45,48 EC_TX PLT_RST# SOUT0/LPCPD#/GPE6 ADC0/GPI0 NTC_V2_CPU V1 0
22 67 NTC_V2_CPU 55
1U_0402_6.3V6K 18,29,45,50,51 PLT_RST# EC_SCI# 23 ERST#/LPCRST#/GPD2 ADC1/GPI1 68 BATT_TEMP
2 14,20 EC_SCI# PCH_PWR_EN ECSCI#/GPD3 ADC2/GPI2 BATT_I BATT_TEMP 62,63
126 ADC 69
53 PCH_PWR_EN GA20/GPB5 ADC3/GPI3 BATT_I 63
70 PSYS V1 0
63,69 change ENBKL to PSYS on GPI4 by Bing 0717
50 RGB_PWR_EN
RE99 1 RGB@ 2 0_0402_5% IT8226E-128/BX ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
ADAPTER_ID
PSYS
ADP_I 63 57 MUX_EDP_ENBKL
R299 1 2 0_0402_5% ENBKL
62,63 Change CHG_MOD2 to NTC_V3_DIMM
58 AGKB_PWR_EN#
RE102 1 AG@ 2 0_0402_5%
58
KSI0/STB#
LQFP128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 NTC_V3_DIMM ADAPTER_ID
NTC_V3_DIMM 55
HLZ SDV 0613 R10 2 1 100K_0402_5%
59 78 CPU_PWRGD
+3VALW_R 60 KSI1/AFD# DAC2/TACH0B/GPJ2 79 CHG_MOD1 CPU_PWRGD 69
+3VL KSI2/INIT# DAC3/TACH1B/GPJ3 H_PROCHOT#_EC CHG_MOD1 47 modify by grace v0
C 61 DAC 80 C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 EC_RTCRST#_ON
KSI4 DAC5/RIG0#/GPJ5 change to CHG_MOD1 on GPJ3 by Bing 0717
RPE2 63
1 4 EC_SMB_CK1 EC_KSI6 64 KSI5 85 EC_ON_1.8V +5VALW
EC_ON_1.8V 74
1

2 3 EC_SMB_DA1 EC_KSI7 65 KSI6 PS2CLK0/TMB0/CEC/GPF0 86 PBTN_OUT#

KSI7 PS2DAT0/TMB1/GPF1 PBTN_OUT# 16,56
15P_0402_50V8J

15P_0402_50V8J

1 1 RE108 36 87 EC_SMB_CK0
37 KSO0/PD0 SMCLK0/GPF2 88 EC_SMB_DA0 EC_SMB_CK0 41,58 USB_ON#
2.2K_0404_4P2R_5% 100K_0201_5% Int. K/B PS2 RE15 1 2 100K_0402_5%
KSO1/PD1 SMDAT0/GPF3 EC_SMB_DA0 41,58 Add SMBUS0 for RTS5400
C113

C112

@ @ 38 89 EC_TP_ON SYSON_VDDQ RE64 1 @ 2 100K_0402_5%

39 KSO2/PD2 Matrix PS2CLK2/GPF4 90 VCCIO_PG EC_TP_ON 50 HLZ SIV 0811
VCCIO_PG 68
2

2 2 BoardID_ADP_LIM 40 KSO3/PD3 PS2DAT2/GPF5

+3VS 41 KSO4/PD4 96 STATUS# +3VALW_R
EXTERNAL SERIAL FLASH STATUS# 47
1

42 KSO5/PD5 GPH3/ID3 97 CPUCORE_ON

KSO6/PD6 GPH4/ID4 ME_FLASH CPUCORE_ON 6,69
RPE3 RE109 43 98
EC_SMB_CK2 KSO7/PD7 GPH5/ID5 SYS_PWROK ME_FLASH 16
1 4 100K_0201_5% 44 99
2 3 EC_SMB_DA2 45 KSO8/ACK# GPH6/ID6 SYS_PWROK 16
@ SUSP# RE18 1 @ 2 100K_0402_5%
KSO9/BUSY
15P_0402_50V8J

15P_0402_50V8J

1 1 BoardID_ADP_LIM: 46 101 EC_SPI_CS0#

2

2.2K_0404_4P2R_5% 1: N18 < 135W ada ter not su ort 51 KSO10/PE FSCE# 102 EC_SPI_SI SUSP# RE19 1 2 100K_0402_5%
KSO11/ERR# FMOSI
CE30

C117

@ @ 0: N18P < 90W ada ter not su ort 52 SPI Flash ROM 103 EC_SPI_SO
+3VALW 53 KSO12/SLCT FMISO 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
2 2 C request 11/1 54 KSO13 FSCK
BoardID_ADP_LIM 55 KSO14 CPUCORE_ON RE14 1 @ 2 100K_0402_5%
RPE4 RE103 1 2 0_0402_5% 56 KSO15 108 ACIN#
EC_SMB_CK0 58 FN_KEY KSO16/SMOSI/GPC3 AC_IN#/GPB0 LID_SW#
2 3 16,55 SMB1_ALERT# 1 @ 2 0_0402_5% 57 UART 109
EC_SMB_DA0 KSO17/SMISO/GPC5 LID_SW#/GPB1 LID_SW# 50
1 4 RE101

2.2K_0404_4P2R_5% ON/OFF 110 82 EC_MUTE#

50 ON/OFF EC_ON PWRSW/GPB3 EGAD/GPE1 EC_MUTE# 54
RE96 2 @ 1 0_0402_5% 111 83 RE92 1 2 0_0402_5%
EC_SMB_CK1 XLP_OUT/GPB4 EGCS#/GPE2 CHG_MOD3 V1 0 EC_ON 55,64,68
115 84
62,63,69,75 EC_SMB_CK1 EC_SMB_DA1 SMCLK1/GPC1 EGCLK/GPE3 CHG_MOD3 47
116
62,63,69,75 EC_SMB_DA1 2 33_0402_5% PECI_EC 117 SMDAT1/GPC2 PM_SLP_S4#
6,14 EC_PECI RE24 1 SM Bus 77 PM_SLP_S4# 16 change to CHG_MOD3 on GPE3 by Bing 0717
USB_CHG_EN 118 SMCLK2/PECI/GPF6 GPJ1 100 GPG2
47 USB_CHG_EN EC_SMB_CK2 94 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2 125 1 2 0_0402_5% VGA_AC_DET
GPIO RE30
16,29,55 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0 VGA_AC_DET 29
95 119 ENBKL
change to USB_CHG_EN on GPF7 by Bing 071716,29,55 EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 122 LAN_WAKE#
DTR1#/SBUSY/GPG1/ID7 113
CRX0/GPC0
BKOFF#
BKOFF# 39 Change R 30 to 0ohm jum
123 PCH_PWROK
112 CTX0/TMA0/GPB2 18 PM_SLP_S3# PCH_PWROK 16
+3VL VSTBY0 RI1#/GPD0 EC_ON_1V PM_SLP_S3# 16
50 NOVO# NOVO# 107 WAKE UP 21
B GPE4/BTN# RI2#/GPD1 EC_ON_1V 67 ADAPTER_ID B
76 SYSON RE105 1 2 0_0402_5% CE31 1 2 .1U_0402_10V6-K
TACH2/GPJ0 48 EC_FAN2_SPEED SYSON 53 SYSTEM_STATUS1 58
TACH1A/TMA1/GPD7 EC_FAN2_SPEED 55
47 EC_FAN1_SPEED SYSON CE13 1 2 .1U_0402_10V6-K EMC_NS@
TACH0A/GPD6 EC_FAN1_SPEED 55
USB_ON# 33 19 1 RE76@ 2 0_0402_5%
48,50 USB_ON# SYSON_VDDQ GINT/CTS0#/GPD5 L80HLAT/BAO/GPE0 CAPS_LED# 50,58
35 GPIO 20 1 RE77@ 2 0_0402_5%
EC_RSMRST# 65 SYSON_VDDQ EC_RSMRST#_R RTS1#/GPE5 L80LLAT/GPE7 EC_ON_5V NUM_LED# 50,58
RH848 1 2 1K_0201_5% 93 3
16,56 EC_RSMRST# CLKRUN#/GPH0/ID0 GPH7 EC_ON_5V 64
V0 RE104 1 2 0_0402_5%
SYSTEM_STATUS2 58
RE29 2 1 0_0402_5% 2
16,45 PCIE_WAKE# GPJ7
Clock
AC_PRESENT 128
+3VL 16 AC_PRESENT GPJ6/THERMTRIP_SHUTDOWN#

RE95 1 2 100K_0402_5% EC_ON

MIRROR@ RE34 1 2 0_0402_5% H_PROCHOT# 6,69
63 VR_HOT#
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5

RE36 1 @ 2 10K_0402_5% BKOFF#

1
EC_SMB_CK1 PAD 1 @ QE1 D 1
LID_SW# EC_SMB_DA1 IT1 H_PROCHOT#_EC
RE38 2 1 100K_0402_5% PAD 1 @ 2 CE14
IT2 PCH_RTCRST# 16
1

27
49
91
104

75

PAD 1 @ G 47P_0402_50V8J
IT3
PAD 1 @ IT8226E-128-BX_LQFP128_14X14 @
IT4

1
PAD 1 @ 2N7002KW_SOT323-3 S 2 QE3 D
IT5

3
EC_RTCRST#_ON 2
RE40 1 2 100K_0402_5% BKOFF# G

EC_KSI7 PAD 1 @ EC_AGND S 2N7002KW_SOT323-3

IT6

3
1
EC_KSI6 PAD 1 @
IT7 PECI_EC
WRST# PAD 1 @ CE15 1 2 47P_0402_50V8J EMC_NS@ RE50
IT8
10K_0402_5%
BATT_TEMP CE16 1 2 100P_0402_50V8J EMC_NS@
For factory C flash +3VL

2
ACIN# CE17 1 2 100P_0402_50V8J EMC_NS@
same net name with PCH ON/OFF CE18 1 2 1U_0402_6.3V6K EMC_NS@ +3VS

1
EC_SPI_CS0# RE45 1 @ 2 0_0402_5%
SPI_CS0#_R 18 RE42
+3VALW_R EC_SPI_SI RE47 1 2 0_0402_5% 100K_0402_5% +3VALW_R
SPI_SI_C 18,50 1
A CE19 A
EC_SPI_SO RE48 1 2 0_0402_5% NOVO# C48 1 2 .01U_0402_16V7-K @ .1U_0402_10V6-K
SPI_SO_C 18,50

1
GPG2 RE44 2 1 10K_0402_5% ACIN# RE94 1 2 0_0402_5%
EC_SPI_CLK PM_SLP_S3# 2 ACIN 63
MIRROR@ RE49 1 2 0_0402_5% CE29 1 2 .01U_0402_16V7-K @ RE5
GPG2 RE46 2 1 10K_0402_5% SPI_CLK_PCH_C 18,50 10K_0402_5%
@
NOMIRROR@ PM_SLP_S4# C135 1 2 .01U_0402_16V7-K @
Delete MOS
when mirror, GPG2 pull high

2
LAN_WAKE#
Reserved Cap HLZ SDV 0616 Reserved Cap HLZ SDV 0616 LAN_WAKE# 45,51
when no mirror, GPG2 pull low EC_SPI_CS0# CE20 1 2 .01U_0402_16V7-K @
Security Classification LC Future Center Secret Data Title
EC_SPI_SI CE21 1 2 .01U_0402_16V7-K @

EC_SPI_SO CE22 1 2 .01U_0402_16V7-K @

Issued Date 2018/08/02 Deciphered Date 2018/08/02 ITE8371LQFP
EC_SPI_CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CE23 1 2 .01U_0402_16V7-K @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 49 of 77

5 4 3 2 1
 5 4 3 2 1

+3VS

ON/OFF switch +3VL

+3VS TP_PWR_530P
LED_KB_C
No function field

1
JKB1
R82 R10497 1 7000P@ 2 0_0402_5% TP_PWR_530P R885 R90
100K_0402_5% 33 32 KB_PIN32 300_0402_5% 300_0402_5% 1
R899 1 2 0_0402_5% 34 GND1 32 31 KB_PIN31 K/B Connector D

.1U_0402_10V6-K
GND2 31 30 2 Q121
1 49,58 LED_KB_PWM

2
D15 30 29 PJA138K_SOT23-3

7000P@
G

C10226
@
NOVO# 2 29 28 PWR_NUM_LED BL@
49 NOVO# S

2
28 27 NUM_LED# KSI[0..7]
1 NOVO_BTN# 2 27 26 PWR_CAPS_LED NUM_LED# 49,58 KSI[0..7] 58 3
R116
26 25 CAPS_LED# KSO[0..16] 100K_0402_5%
1 2 R85 3 25 24 CAPS_LED# 49,58 KSO[0..16] 58
ON/OFF KSO15 BL@
24 23 KSO14 D23 AZ5725-01F.R7GR_DFN1006P2X2 KSO16 1 @ T11
0_0402_5%

1
BAT54CW_SOT323-3 23 22 KSO12
@ 22
@ 21 KSO10 1 2 EMC@

J5 1 2 @ +3VL
TP CONN FOR 530P 21
20
20
19
KSO11
KSO6
1 2

JTP2 19 18 KSO8 D35 AZ5725-01F.R7GR_DFN1006P2X2

SHORT PADS TP_PWR_530P 1 18 17 KSO4
1 17

2
PCH_TP_CLK 2 16 KSO2 1 2 EMC@
D J6 1 2 @ R111 PCH_TP_DATA 3 2 16 15 KSO5 1 2 D
100K_0402_5% 4 3 15 14 KSO13
SHORT PADS R10527 1 @ 2 0_0402_5% 5 4 14 13 KSI0
+3VL LID_SW# 5 13
R10528 1 @ 2 0_0402_5% 6 12 KSI3

1
PCH_TP_INT 7 6 12 11 KSO1 +5VS
EC_TP_ON 7 11 KB_PIN32 0.5A JKBL1
ON/OFFBTN# R119 1 2 0_0402_5% ON/OFF 8 10 KSI2 KSO9 R400 1 2 0_0402_5%
ON/OFF 49 8 10 9 1
KSI4
9 9 8 KSO3 KSI7 R418 1 @ 2 0_0402_5% KB_PIN31 LED_KB_C 2 1
@
10 GND1 8 7 KSI5 R343 1 2 0_0603_5% LED_Power_C1 3 2
GND2 7 6 KSI6 BL@ 4 3
@
6 5 KSO9 4

0.1U_0402_10V6K
5 4 KSI7 5

C316
HIGHS_FC5AF081-2931H 2
4 3 KSI1 6 GND1
PWR_LED1# ME@ 3 GND2
2 KSO0
2 1 KSO7 @
1 1 HIGHS_FC1AF041-1201H
ME@
ON/OFFBTN# HIGHS_FC8AF321-3201H
ME@

AZ5123-01F.R7GR_DFN1006P2X2
1

1
SW5
1

D1 D4320

1
1

AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@ LED2 @ 15@

@ 49 PWR_LED1#
PWR_LED1# Power LED 1 2 R9746 1 21/16W_82_1%_0402
+3VALW
B1931TX--05P-000314_WHITE
2

2
2

2
Power LED for 530P LED305
2

7000P@
7000P@
EVQPQHB55_4P PWR_LED1# 1 2 R10518 1 21/16W_82_1%_0402
+3VALW
@ B1931TX--05P-000314_WHITE
V1 0 Delete JKBL
modify by grace

+3VS TP_PWR

R141 1 2 0_0402_5% TP_PWR

Right Side USB2.0 Port X 1 (USB/B) +USB_VCCB
Charger LED
V1 0 .1U_0402_10V6-K LED301
JP1
1
C +3VALW R67 1 2 0_0402_5% 1 C
BATT_LOW_LED# 4 3 2 1
49 BATT_LOW_LED# 2
R3001 3
R104481 2 1K_0201_5% PCH_TP_CLK 2 1 2 4 3
C114

+3VS L14
R104491 2 1K_0201_5% PCH_TP_DATA USB20_P2 2 1 USB20_P2_CONN 5 4
BATT_CHG_LED# 1 19 USB20_P2 2 1 USB20_P2_CONN 5
2 150_0402_5% 6
49 BATT_CHG_LED# USB20_N2_CONN 7 6
1 1 @ 7
Modify by Grace 11/19 USB20_N2 3 4 USB20_N2_CONN 8
19 USB20_N2 3 4 USB30_RX_N4 9 8
C1940 C1941
B2972UDBS05P-000114_AMBER-WHITE
modify by Grace 15 USB30_RX_N4 USB30_RX_P4 10 9
220P_0402_50V7K 220P_0402_50V7K EXC24CH900U_4P
15 USB30_RX_P4 10
EMC_NS@ 2 2 EMC_NS@ @ EMC_NS@ 11
USB30_TX_N4 12 11
15 USB30_TX_N4 USB30_TX_P4 12
R66 1 2 0_0402_5% 13
15 USB30_TX_P4 14 13
PWR_LED1# 15 14
16 15
+3VALW 16
17
LED306 18 17
18
150P_25V_J_COG_0201

150P_25V_J_COG_0201

PCH_TP_CLK +3VALW NOVO_BTN# 19

BATT_LOW_LED# 1 20 19
C116

C115

PCH_TP_DATA R10521 21 20
1 1
TP/B Connector 2 1 2
USB3.1 PORT x1 55 NT_REMOTE1+
NT_REMOTE1+ 22 21
22
1

NT_REMOTE1- 23
BATT_CHG_LED# 3 55 NT_REMOTE1- 24 23
1K_0402_5% 1
1

2 2 C1942 24
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

7000P@
D4317 D4318 .1U_0402_10V6-K Low Active 1.8A 25
Modify by Grace 11/19 JTP1 B2102UDBS05P-000133_WHI-AMB 7000P@ +5VALW +USB_VCCB GND1
TP_PWR 1 2 26
PCH_TP_CLK 1 7000P@ GND2
2

2 U2
20 PCH_TP_CLK PCH_TP_DATA 3 2 5 1
2

20 PCH_TP_DATA 3 IN OUT
4 ELCO_046809624210846+
EMC_NS@ EMC_NS@ 4 BATT_LOW_LED#
R10441 1 2 0_0201_5% 5 2 ME@
20 PCH_TP_INT 5 GND
For EMC 49 EC_TP_ON
6
6 BATT_CHG_LED#
2
USB_OC1#
7 C58 4 3
G1 ENB OCB
2

8 1U_0402_16V6K USB_OC1# 19
10K_0201_5%

G2 G517E2T11U_SOT23-5
RG50

1 1
@ RG49 CVILU_CF31061D0R4-10-NH_6P C61

AZ5123-01F.R7GR_DFN1006P2X2
10K_0201_5% ME@ 1000P_0402_50V7K
@

AZ5123-01F.R7GR_DFN1006P2X2
1

1
2
D13 D14 USB_ON#

1
48,49 USB_ON#
EMC_NS@
+3VS +3VS

2
EMC_NS@

2
B B

+USB_VCCB

+3VALW +3VALW_TPM JP5

1
2 1
R2101 2
1 2 3
4 3
0.01_0603_1% 4
5
TPM@ USB20_P2_CONN 5
10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

2 2 2 2 6
USB20_N2_CONN 6
C2102

C2101 TPM@

C2103 TPM@

C2104

7
8 7
USB30_RX_N4 9 8
1 1 1 1@ USB30_RX_P4 10 9
@ 11 10
USB30_TX_N4 12 11
USB30_TX_P4 13 12
14 13
PWR_LED1# 15 14
16 15
+3VALW 16
17
+3VALW_TPM 18 17
NOVO_BTN# 19 18
20 19
21 20
V1 0 Delete JKBL NT_REMOTE1+ 22 21
NT_REMOTE1- 23 22
+3VALW_TPM 24 23
PCH_RGBKB_SCL 25 24
20 PCH_RGBKB_SCL 25
2

PCH_RGBKB_SDA 26
20 PCH_RGBKB_SDA
2

R2103 R2104 27 26
R2102 10K_0402_5% R10663 10K_0402_5% RGB_KB_INT 28 27
22

U2101 18 RGB_KB_INT 28
8

10K_0402_5% TPM@ 0_0402_5% @ RGB_PWR_EN 29

49 RGB_PWR_EN 30 29
TPM@ @
VHIO2

VHIO1

VSB
1

31 30
1

R2110 2 1 0_0402_5% TPM@ TPM_IRQ# 18 2 32 31

TPM_SPI_IRQ# PIRQ#/GPIO2 NC1 3 33 32 36
NC2 +5VS 33 GND2
4 34 35
R2105 2 1 49.9_0402_1% TPM@ TPM_MOSI 21 PP/GPIO6 5 34 GND1
18,49 SPI_SI_C TPM_MISOI MOSI/GPIO7 NC3
R2106 2 1 49.9_0402_1% TPM@ 24 9 ELCO_046809634310846+
18,49 SPI_SO_C MISO NC5 10
NC6 ME@
11
NC7 12
R2107 2 1 0_0402_5% TPM@ TPM_CS2# 20 NC8 13
18 SPI_CS2# SCS#/GPIO5 GPIO4 14
R2108 2 1 49.9_0402_1% TPM@ TPM_CLK 19 NC9 15
18,49 SPI_CLK_PCH_C SCLK NC10 16
NPCT750LABYX_QFN32_5X5
A PLT_RST# 17 GND1 25 A
PLTRST# NC11 26
6 NC12 27
GPIO3 NC13 28
TPM_PP 7 NC14 31 1
NC4 NC15
NC16
32 Hall Sensor C1943
29 R2111 1 @ 2 0_0402_5% 100P_0402_50V8J
PLT_RST# 18,29,45,49,51
1

SDA/GPIo0 30 2 EMC@
SCL/GPIO1 U5
GND2

GND3

R2112
0_0402_5% 1 1
@ GND
C1944 3 LID_SW#
LID_SW# 49
2

23

33

TPM@ 0.01U_50V_K_X7R_0402 OUTPUT

EMC@ 2
R1 1 2 0_0402_5% +VCC_LID 2
+3VL VCC
Security Classification LC Future Center Secret Data Title
AH9247-W-7_SC59-3
@ Issued Date 2018/08/02 Deciphered Date 2018/08/02 KBD/PWR/IO/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 50 of 77
5 4 3 2 1
 5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms＜spec＜100ms +3VALW_LAN +LAN_VDDREG
Need short
JL1 1 2 @ width : 40 mils RL7 1 2 0_0603_5% width : 40 mils
1 2

CL10

CL11
JUMP_43X79 @

CL5

0.1U_6.3V_K_X5R_0201 CL6

CL7
CL35

0.1U_6.3V_K_X5R_0201
1 1

4.7U_0402_6.3V6M
D D
8111GUL@ 8111GUL@

0.1U_6.3V_K_X5R_0201
1 1 1 1

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
+3VALW LP2301ALT1G_SOT23-3 2 2

2 2 2 2

D
Q182 3 1 @
EMC@ EMC@ V0

0.01U_0201_10V6K
1 1 1
RL2 CL8 CL9

G
2
100K_0402_5% @
@ 0.1U_6.3V_K_X5R_0201 @ V0
2 2 +3VALW_LAN
Close to Pin11 Close to Pin32
2

LAN_PWR_ON# RL3 1 @ 2
20 LAN_PWR_ON#
47K_0402_5%
Close to Pin11 Close to Pin32

2
RL19
V0 10K_0402_5%
@

1
LAN_CLKREQ#_R RL18 1 2 0_0402_5%
LAN_CLKREQ# 17
+3VALW_LAN @
UL1
2

RL27
10K_0402_5%
@ 33
C +3VALW_LAN 32 GND 16 CLK_PCIE_LAN# C
CLK_PCIE_LAN# 17
1

RL8 1 2 RSET_LAN 31 AVDD33_2 REFCLK_N 15 CLK_PCIE_LAN

PCIE_WAKE#_R +LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N14 CLK_PCIE_LAN 17
45,49 LAN_WAKE# RL28 1 2 0_0402_5% 2.49K_0402_1% 30 14
LAN_XTALO 29 AVDD10 HSIN 13 PCIE_PTX_C_DRX_P14 PCIE_PTX_C_DRX_N14 14
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P14 14
@ 28 12
TL3 @ 1 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# RL121 @ 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPO MDIN3 LAN_MDI3+ LAN_MDI3- 52
0_0402_5% TL4 @ 1 25 9
+3VS +LAN_REGOUT 24 LED2 MDIP3 8 +LAN_VDD10 LAN_MDI3+ 52
+LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 22 VDDREG MDIN2 6 LAN_MDI2+ LAN_MDI2- 52
DVDD10 MDIP2 LAN_MDI2+ 52
1

PCIE_WAKE#_R 21 5 LAN_MDI1-
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- 52
RL9 ISOLATE# 20 4
PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10 LAN_MDI1+ 52
1K_0402_1%
18,29,45,49,50 PLT_RST# PCIE_PRX_C_DTX_N14 18 PERSTB AVDD10_1 LAN_MDI0-
CL12 1 2 0.1u_0201_10V6K 2
14 PCIE_PRX_DTX_N14 PCIE_PRX_C_DTX_P14 17 HSON MDIN0 LAN_MDI0+ LAN_MDI0- 52
CL13 1 2 0.1u_0201_10V6K 1
14 PCIE_PRX_DTX_P14 LAN_MDI0+ 52
2

HSOP MDIP0

ISOLATE# RL26 1 @ 2 0_0402_5% LAN_PWR_ON#

CL12 close to Pin18
CL13 close to Pin17
V0
1

RL11 PLT_RST#
15K_0402_5%
@ RTL8111H-CG_QFN32_4X4
1
CL1
2

1000P_0402_50V7K
2

B B

LAN_XTALI

YL1 LAN_XTALO
8111H@ +LAN_VDD10
1 4 RL25 1 2 0_0805_5%
OSC1 GND2
2 3 60mil 60mil
GND1 OSC2 +LAN_REGOUT LL1 1 2
2.2UH_NLC252018T-2R2J-N_5%
1 1 8111GUL@ 1 1 1 1 1 1 1 1
25MHZ_10PF_7V25000014 1 CL36 CL40 CL17 CL18 CL19 CL20 CL21 CL22
CL15 CL14 CL39 Layout Note: LL1 must be 4.7U_0402_6.3V6M 0.1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
1U_6.3V_M_X5R_0201
@ 0.1U_6.3V_K_X5R_0201
10P_0402_50V8J 10P_0402_50V8J 0.1U_6.3V_K_X5R_0201 8111GUL@ 8111GUL@ @
2 2 8111H@ within 200mil to Pin24, 2 2 2 2 2 2 2 2
2 CL36,CL37 must be within
200mil to LL1
+LAN_REGOUT: Width =60mil Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)

modify by Grace v0
A A
V0

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 LAN_RTL8111
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 51 of 77

5 4 3 2 1
 5 4 3 2 1

DL1/DL2 TL1
1'S PN:SC300005900 1:1 24 LAN_MDO3-
LAN_MDI3- 1 T1/B MX1+
Place Close to TL1 51 LAN_MDI3- TD1+

23 LAN_MDO3+
MX1-
LAN_MDI3+ 2
51 LAN_MDI3+ TD1-
TDCT 3 22
TCT1 T1/A MCT1
DL1
D LAN_MDI3- LAN_MDI2- D
4 3 4 21
I/O3 I/O2 TCT2 1:1 MCT2 20 LAN_MDO2-
LAN_MDI2- T1/B MX2+
5
51 LAN_MDI2- TD2+
5 2
VDD GND
19 LAN_MDO2+
LAN_MDI2+ 6 MX2-
LAN_MDI3+ 6 1 LAN_MDI2+ 51 LAN_MDI2+ TD2-
I/O4 I/O1
AZ1215-04S.R7G_SOT23-6L-6 T1/A
EMC_8111H@ 1:1 18 LAN_MDO1-
LAN_MDI1- 7 T1/B MX3+
51 LAN_MDI1- TD3+

17 LAN_MDO1+
MX3-
LAN_MDI1+ 8
51 LAN_MDI1+ TD3-
DL2 9 16
LAN_MDI1- 4 3 LAN_MDI0- TCT3 T1/A MCT3
I/O3 I/O2
10 15
TCT4 1:1 MCT4 LAN_MDO0-
T1/B 14
5 2 LAN_MDI0- 11 MX4+
VDD GND 51 LAN_MDI0- TD4+
2
LAN_MDI1+ 6 1 LAN_MDI0+ CL24 13 LAN_MDO0+
I/O4 I/O1 LAN_MDI0+ 12 MX4-
0.01U_0201_25V6-K 51 LAN_MDI0+ TD4-
AZ1215-04S.R7G_SOT23-6L-6 1
EMC@
EMC_8111H@
T1/A

BOTH_NA0069R-LF
C C

1
RL17
20_0603_5%

1
DL3

1
2
BS4200N-C-LV_SMB-F2
EMC@

2
2
1 1
CL32 CL25
68P_0402_50V8J 1000P_1206_2KV7-K
EMC@ EMC_NS@
2 2

CHASSIS1_GND

B B
V1 0

RL14 1 2 0_0402_5%

RL15 1 @ 2 0_0402_5%

RL16 1 @ 2 0_0402_5%

RL24 1 @ 2 0_0402_5%

@ JRJ1

Reserve for MI go rural solution

CHASSIS1_GND LAN_MDO3- J8
BI_DD-
LAN_MDO3+ J7
BI_DD+
LAN_MDO1- J6
BI_DB-
LAN_MDO2- J5
BI_DC-
LAN_MDO2+ J4
BI_DC+
LAN_MDO1+ J3
BI_DB+
LAN_MDO0- J2
BI_DA-
LAN_MDO0+ J1 GND1
BI_DA+ GND_1
GND2
GND_2
LOTES_AJKM0044-P002A11
ME@
CHASSIS1_GND

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 LAN_Transformer

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 52 of 77

5 4 3 2 1
 A B C D E

+1.8VALW +1.8VS_AON

+5VALW to +5VS +1.8VALW to +1.8VS_AON

+5VALW
+5VLP +5VALW
Q5811
5VS_CT1 +0.6VS AON7400A_DFN8-5
1
V20B+

1000P_0402_50V7K
+5VALW

1
C121 +5VS 1 1
S1

1
U56

C125
1U_0402_16V6K R161 R157 5 2

0.1U_0402_25V6
D S2

1
2 1 14 100K_0402_5% @ 100K_0402_5% R159 3
1 1

1
2 IN1_1 OUT1_2 13 C216 47_0603_5% RV1114 @ S3 CV451
Change net to SUSP# for PWR sequence IN1_2 OUT1_1

G
1

1
.1U_0402_10V6-K 2 @ 100K_0402_1% 0.01U_50V_K_X7R_0402 RV1116 1

2
SUSP# R263 1 2 0_0402_5% 3 12 5VS_CT1 @ RV1113 OPT@ @ 1/10W_47_5%_0603 CV448

CV452
2

4
EN1 CT1 2 SUSP 47K_0402_5% OPT@ 2 OPT@ 10U_0603_6.3V6M

2
43,44,54 SUSP
4 11 OPT@ RV1119 @

2
1
VBIAS GND D 1 2 2

2
R264 1 2 0_0402_5% 5 10 3VS_CT2 +3VS 2 SUSP 1K_0402_5%
+3VALW EN2 CT2 3VS_CT2 G Q18 OPT@

0.047U_0402_25V7K
1

3
2200P_0402_25V7-K
1 V1 0 6 9 D 2N7002KW_SOT323-3 QV25B D
IN2_1 OUT2_2 +1.8VS_AON_EN#

L2N7002KDW1T1G_SOT363-6
1 7 8 SUSP# 2 S @ 5 1
1 2 1

3
C123 IN2_2 OUT2_1

C124

OPT@
C215 G Q6 G

CV450
1

1
0.01U_50V_K_X7R_0402 15 .1U_0402_10V6-K 2N7002KW_SOT323-3

6
2 C122 Thermal Pad @ S QV25A D OPT@ S RV1121

4
@ 2 1 2

L2N7002KDW1T1G_SOT363-6
1U_0402_10V6K RV1115 1 @ 2 0_0402_5% 2 430K_0402_1%
2 G2898KD1U_TDFN14P_2X3 19,29 PXS_PWREN G OPT@ OPT@

1
D
DV12

2
1
RV1216 S +1.8VS_AON_EN# 2 QV23

1
1
3 1 2 0_0402_5% CV449 RV1117 G L2N7002KWT1G_SOT323-3
0.1U_0402_25V6 100K_0402_5% OPT@
1 OPT@ OPT@ @ S

3
R1217 10K_0402_1%

2
2 1 2

LBAT54SWT1G_SOT323-3 OPT@
OPT@ V0 3

LP 301ALT1G
Rds 110mohm @
VGS 5V ID 8A
VGS th 1V Ma

+3VALW Need short +3VALW_PCH

J7
1 2
1 2
+5VALW
JUMP_43X79
1 1
@
1

C327 C328
LP2301ALT1G_SOT23-3 1U_0402_10V6K 1U_0402_10V6K
R155 2@ 2@

D
100K_0402_5% 3 1
2 @ 2
2

1 Q29 1
PCH_PWR_EN# G
2 @
C129 C130
change EN to PCH_PWR_EN by Bing 0717 .1U_0402_10V6-K 0.01U_50V_K_X7R_0402
1

D 2@ 2@
PCH_PWR_EN 2
49 PCH_PWR_EN PCH_PWR_EN#_R
G R163 1 @ 2
0_0402_5%
S Q30
3
1

L2N7002KWT1G_SOT323-3 1
R162 @ R87
100K_0402_5% 100K_0402_5% C131
@ @ .1U_0402_10V6-K
2@
2

+1.05VALW
1U_0402_16V6K

VCCSTG_CT2
1

1000P_0402_50V7K
C10168

VCCST 1
U126

C10165
2
10mA
1 14 1
2 IN1_1 OUT1_2 13 C10166
IN1_2 OUT1_1 .1U_0402_10V6-K 2
SYSON R10424 1 2 0_0402_5% 3 12 VCCST_CT1 @
EN1 CT1 2
V1 0 4 11
+5VALW VBIAS GND
R10425 1 2 0_0402_5% 5 10 VCCSTG_CT2 VCCSTG
49,65,68 SUSP# EN2 CT2 VCCST_CT1
+1.05VALW
1000P_0402_50V7K

V1 0 6 9 0mA
R104571 @ 2 7 IN2_1 OUT2_2 8
49,66 SYSON IN2_2 OUT2_1 1 1
C10170

100K_0402_5% 1 C10164
1U_0402_10V6K

3 15 .1U_0402_10V6-K 3
C10169

1 Thermal Pad @
C10167 @ 2 2
2 G2898KD1U_TDFN14P_2X3
0.01U_50V_K_X7R_0402
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 DC V TO VS INTERFACE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 53 of 77
A B C D E
 5 4 3 2 1

+3VALW DVDD_IO Digital power for digital I/O circuit Analog power for DACs, ADCs
+3VS DVDD_IO +5VD +5VA +1.8V_AUDIO
V1 0
RA227 1 2 0_0402_5% +1.8VS +1.8V_AUDIO

+5VD

+5VA
2.2U_0402_6.3V6M

0.1U_0201_6.3V6-K
Digital power for HDA link 2 2 V1 0 100P_0201_25V8J
@ @

CA187

0.1U_0201_6.3V6-K
1 2 0_0402_5% LINE2-L CA198 1 2 1U_0402_6.3V6K CA207 1 2

CA2
RA225

10U_0402_6.3V6M
2 1 2

1U_0402_6.3V6K

2.2U_0402_6.3V6M
0.1U_0201_6.3V6-K

4.7U_0603_6.3V6K
1 1 V1 0

CA180

CA179

CA202
2 1 1

CA192

CA191
HPOUT_L RA231 1 2 56_0402_5% A_HP_OUTL_R

CA4
@
1 @ 2 1
Close to Pin18 1 2 2
@ HPOUT_R A_HP_OUTR_R
RA230 1 2 56_0402_5%

18

46

41

40

20
3
UA1 @ @
LINE2-R CA199 1 2 1U_0402_6.3V6K CA206 1 2

PVDD2

PVDD1

AVDD1

CPVDD/AVDD2
DVDD-IO
DVDD
D 100P_0201_25V8J D

PDB
2 SPKR_MUTE# HP/MIC Jack
Analog power for mixers, & IO ports Power supply for full-bridge left/Right channel 14
HPOUT_L 27 BCLK PCH_HDA_BIT_CLK 16
+5VS +5VA HPOUT-L 15 JHP1

1U_0402_6.3V6M
+5VS +5VD HPOUT_R 26 SYNC PCH_HDA_SYNC 16
2 HPOUT-R
V1 0 47 LINE2-JD @1 100K_0402_1%
TC214 2 @ 1 RA205 A_RING2_CONN 3

CA196
MIC2_VREFOL JD2 +3VS A_HP_OUTL_R G/M
EMC_NS@ @ 28 R2 1 2 C10138 2 1 EMC_NS@ 1
RA7 1 2 0_0603_5% LA25 1 2 BLM15PD600SN1D_2P MIC2-VREFO-L 48 JSENSE 0_0402_5% 2 1 RA204 HPOUT_JD EMC_NS@ 0_0402_5% 1000P_0402_50V7K L
1 MIC2_VREFOR 29 JD1 HPOUT_JD 5
MIC2-VREFO-R 5
10U 6.3V M X5R 0402

RA228 1 2 0_0603_5% 1 2
0.1U_0201_6.3V6-K

1 2 2 1 CA205 @ 1U_0402_6.3V6K 6
GNDA
1U_0402_6.3V6K

MIC2_VREFOL SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN 6

10U_0603_6.3V6M
@ @ V1 0 1 RA37 2 2.2K_0402_5%
DMIC_DATA_C 0_0402_5% A_HP_OUTR_R

10U_0603_6.3V6M

CA18

CA19
4 2 1 RA19 R10270 1 2 C10139 2 1 EMC_NS@ 2
CA200

CA203

CA201

1 1 2 2 GPIO0/DMIC-DATA12 DMIC_DATA_R 39 R
A_RING2_CONN

CA194

CA178
30 EMC_NS@ 0_0402_5% 1000P_0402_50V7K
2 1 1 MIC2-L/RING2 5 DMIC_CLK 0_0402_5% 2 1 RA18 A_RING3_CONN 4
A_RING3_CONN GPIO1/DMIC-CLK DMIC_CLK_R 39 M/G

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
31
2 2 1 1 MIC2-R/SLEEVE 6 7
MIC2_VREFOR PC_BEEP I2C-DATA GNDA MS
1 RA229 2 2.2K_0402_5% 34
PCBEEP 7 1 1 SINGA_2SJ3095-140111F
I2C-CLK GNDA
CA 00 CA 01 CA 03 ME@

1000P_0402_50V7K

1000P_0402_50V7K
EMC@
C10140

C10141
close to PIN 0 1
8

EMC@
CA195

1U_0402_6.3V6M
RA203 1 2 10K_0402_5% VDD_STB 33 NC1 2 2
+5VA 5VSTB 9
2 LINE2-R 35 NC2
@ LINE2-R 10
LINE2-L 36 NC3
LINE2-L 11
NC4
12 GNDA
NC5

23 45 SPK_R+
CBP SPK-OUT-R+
SPK_R- F R SD Close to Connector
CA48 1 2 1U_0402_6.3V6K 24 44
CBN SPK-OUT-R-
43 SPK_L- A_RING2_CONN
SPK-OUT-L-
42 SPK_L+ A_RING3_CONN
RA1 1 2 0_0402_5% CA403 1 2 2.2U_0402_6.3V6M 32 SPK-OUT-L+
EMC_NS@ MIC2-CAP 13 A_HP_OUTL_R
RA4 1 2 0_0402_5% CA190 1 2 2.2U_0402_6.3V6M 38 DC DET/EAPD
EMC_NS@ VREF A_HP_OUTR_R
CA1 2 1 2.2U_0402_6.3V6M 19 16 SDATA_IN 33_0402_5% 2 1 RA16
LDO3-CAP SDATA-IN PCH_HDA_SDIN0 16 HPOUT_JD
RA9 2 1 0_0402_5% CA189 2 1 2.2U_0402_6.3V6M HD_LDO2 21 17
LDO2-CAP SDATA-OUT PCH_HDA_SDOUT 16
RA12 1 2 0_0402_5% CA188 2 1 2.2U_0402_6.3V6M LDO1_CAP 39
C EMC_NS@ LDO1-CAP 25 C

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2

AZ5425-01F.R7GR_DFN1006P2E2
1

1
CPVEE

Thermal Pad
D25 D2 D26 D4 D27

56P 50V J NPO 0402

2 1

1
AVSS1

AVSS2
CA193

EMC_NS@
GND GNDA

C10143
1U_0402_6.3V6K
1 2

2
ALC3287-CG_MQFN48_6X6

37

22

49
EMC_NS@

2
EMC_NS@ EMC_NS@ EMC_NS@ EMC@

GNDA

RA15 1 2 0_0201_5% SPKR_MUTE#

49 EC_MUTE#
1

V1 0 RA23
@ 10K_0201_5%
2

PCH_HDA_SYNC
DMIC_CLK_R EMC_NS@ PCH_HDA_SDOUT
RA27 1 2 27_0402_5% PCH_HDA_BIT_CLK
JSPK1 SPK_L+ 1 2 EMC_NS@ 1 2 EMC_NS@ DMIC_DATA_R PCH_HDA_SDIN0
SPK_R+ LA931 2 BLM15PD800SN1D_2P SPK_R+_CONN 1 RA194 15_0402_5% CA173 220P_0201_25V7-K
SPK_R- LA941 2 BLM15PD800SN1D_2P SPK_R-_CONN 2 1

CA38

CA39

CA23

CA24

CA25

CA26
100P_0201_25V8J

100P_0201_25V8J
SPK_L- LA951 2 BLM15PD800SN1D_2P SPK_L-_CONN 3 2 SPK_L- 1 2 EMC_NS@ 1 2 EMC_NS@ EMC_NS@ 1 EMC_NS@
1

22P_0201_258J

22P_0201_258J

33P_0201_50V8-J

33P_0201_50V8-J
SPK_L+ LA961 2 BLM15PD800SN1D_2P SPK_L+_CONN 4 3 RA195 15_0402_5% CA174 220P_0201_25V7-K
4 1 1 EMC_NS@1 EMC_NS@1 EMC_NS@
5 EMC_NS@
B 6 G1 SPK_R+ 1 2 EMC_NS@ 1 2 EMC_NS@ B
2200P_25V_K_X7R_0402

2200P_25V_K_X7R_0402

2200P_25V_K_X7R_0402

2200P_25V_K_X7R_0402

G2 RA196 15_0402_5% CA175 220P_0201_25V7-K 2 2

HIGHS_WS32040-S0471-HF 2 2 2 2
SPK_R- 1 2 EMC_NS@ 1 2 EMC_NS@
CA31

CA32

CA33

CA34

1 1 1 1 ME@
RA197 15_0402_5% CA176 220P_0201_25V7-K For EMI
Place Close To Codec
AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2

AZ5725-01F.R7GR_DFN1006P2X2
1

2 2 2 2
MC request 11/13 V0 D4314 D39 D40 D41
1

1
2

2
2

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@

+1.8VS
+1.8VALW

RA39
1 2 CA404 1 2 0.1U_0201_6.3V6-K
+3VS +3VS
RA232 1 2 0_0402_5% +3VS +3VS +VCCPRIM_1P05 +VCCPRIM_1P05
4.7K_0402_5%

PC-BEEP LP2301ALT1G_SOT23-3
Q183 1 1 1 1
DA1 1 1
S

D
BEEP# 2 3 1 C10223 @ C10231 @ C10232 @ C10234
49 BEEP# CA35 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K
@ C10218 C10220
1 RA10 1 2 0_0402_5% PC_BEEP_C 1 2 PC_BEEP 0.1U_0201_6.3V7-K 0.1U_0201_6.3V7-K 2 @ 2 2 2
1 1 2 2
C8473
0.1u_0201_10V6K

C8475
0.1u_0201_10V6K
@ @
G
2

PCH_BEEP 3 @
16 PCH_BEEP @
1

0.1U_0402_10V7K
BAT54CW_SOT323-3 RA11 2@ 2@
@ 10K_0402_5% R10068 +3VS +3VS

C8472
4.7U_0402_6.3V6M
@ SUSP 1 2 0_0402_5% 1 1 1 +3VALW
43,44,53 SUSP

C8471
0.1u_0201_10V6K

C8470
0.1u_0201_10V6K
2

1 2 2 2
C8474
0.1u_0201_10V6K

R10070
A @ 470K_0402_5% @ @ @ A
RA38
1 2 CA204 1 2 0.1U_0201_6.3V6-K 2@
2

4.7K_0402_5%

V0

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Codec_CX20752
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
D 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 54 of 77
5 4 3 2 1
 5 4 3 2 1

Fintek(1 Local+2 Remote) thermal sensor +3VS +3VS

placed near DIMM

REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

2
+3VS Near CPU FAN R881 R882
U1 4.7K_0402_5% 4.7K_0402_5% REMOTE1+
Near GPU&VRAM REMOTE2+
Near CPU core
@ @ 1 1

1
C C

1
1 10 EC_SMB_CK2 C45 2 Q15 C46 2 Q16
D VCC SCL EC_SMB_CK2 16,29,49 B B D
3300P_0402_50V7-K MMBT3904WH_SOT323-3 3300P_0402_50V7-K MMBT3904WH_SOT323-3
1 REMOTE1+ 2 9 EC_SMB_DA2 @2 @ 2
EC_SMB_DA2 16,29,49

3
DP1 SDA REMOTE1- REMOTE2-
C47 REMOTE1- 3 8 THEM_ALERT# R301 1 2 0_0402_5%
.1U_0402_10V6-K DN1 ALERT# SMB1_ALERT# 16,49
2 THERM_L @
REMOTE2+ 4 7
@ DP2 THERM#
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10

Near GPU&VRAM
Near CPU

+5VLP +5VLP +3VALW

+5VLP +3VALW

HW thermal sensor

1
2

C254 R29 R36 R10351

1
0.1U_0603_25V7-M 21.5K_0402_1% 21.5K_0402_1% 13.7K_0402_1%
@ @ @ @ R10353
1

13.7K_0402_1%

2
@
U18 NTC_V1_GPU
49 NTC_V1_GPU

2
1 8 TMSNS1 R88 1 @ 2 0_0402_5% NTC_V1_GPU

1
VCC TMSNS1 NTC_V2_CPU
49 NTC_V2_CPU
2 7 PHYST1 R175 1 @ 2 10K_0402_5% RT2
GND RHYST1 @ 100K_0402_1%_TSM0B104F4251RZ
3 6 TMSNS2 R176 1 @ 2 0_0402_5% NTC_V2_CPU
OT1 TMSNS2
C C

1
4 5 PHYST2 R177 1 @ 2 10K_0402_5%
49,64,68 EC_ON OT2 RHYST2 RT3
G718TM1U_SOT23-8 @ 100K_0402_1%_TSM0B104F4251RZ

2
@
R10352

2
0_0402_5%
over temperature threshold:
RSET=3*RTMH

1
92+/-30C @
Hysteresis temperature threshold.
RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

for layout optimized, change the EC_AGND to GND

Nuvoton(1 Local+1 Remote) thermal sensor Near DIMM

placed near TBD +3VALW
+3VS +3VS

1
R10355
2

13.7K_0402_1%
+3VS R443 R441 @
4.7K_0402_5%
Near PCH 4.7K_0402_5%

2
@ @
U134 NTC_V3_DIMM
49 NTC_V3_DIMM
1

1 8 EC_SMB_CK2
B VDD SCL B
NT_REMOTE1+ 2 7 EC_SMB_DA2
1 D+ SDA

1
C363 NT_REMOTE1- 3 6 R442 1 2 0_0402_5% SMB1_ALERT# RT4
.1U_0402_10V6-K D- ALERT# @
@ 100K_0402_1%_TSM0B104F4251RZ
@ 2 4 5
T_CRIT# GND

2
NCT7718W_MSOP8
SMBus Address: 1001_100xb
JFAN3

2
+5VS_FAN2 1
EC_FAN2_SPEED 2 1 R10354 R188
NT_REMOTE1+ EC_FAN2_PWM 3 2 0_0402_5% 0_0402_5%
NT_REMOTE1- NT_REMOTE1+ 50 3
4 @
NT_REMOTE1- 50 4
5

1
6 G1
Thermal Diode Near GPU FAN(DB) G2 @
HIGHS_WS32040-S0471-HF
NT_REMOTE1+/-:
ME@
Trace width/space:10/10 mil EC_AGND
Trace length:<8" V1 0

FAN Conn
Address 1001_101xb
+5VS +5VS
JFAN1 JFAN2
R52 1 2 0_0603_5% +5VS_FAN1 1 R75 1 2 0_0603_5% +5VS_FAN2 1
2 1 2 1
49 EC_FAN1_SPEED 2 49 EC_FAN2_SPEED 2
1 @ 1 49 EC_FAN1_PWM 3 1 @ 1 49 EC_FAN2_PWM 3
C50 4 3 C60 4 3
C49 .1U_0402_10V6-K 5 4 C81 .1U_0402_10V6-K 5 4
10U_0805_10V6K @ 6 G1 10U_0805_10V6K @ 6 G1
A A
2 2 G2 2 2 G2
HIGHS_WS32040-S0471-HF HIGHS_WS32040-S0471-HF
ME@ ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Thermal sensor/FAN CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 55 of 77

5 4 3 2 1
 5 4 3 2 1

18 SPI_WP#

1
TABLE : CPU ITP DEBUG REPORT R597
1K_0402_1%
Individual DCI 2.0 VCCSTG
@
No use

2
Port w/o connector

R591 NO ASM NO ASM ASM

D D

2
R593 NO ASM NO ASM ASM R93 R55 R56
51_0402_1% 51_0402_1% 51_0402_1%
R594 NO ASM NO ASM ASM DCI@ @ @
R595 NO ASM NO ASM ASM

1
PCH_TDO R596 1 DCI@ 2 0_0201_5% XDP_TDO PAD 1 @
R596 NO ASM NO ASM ASM 16 PCH_TDO IT9
PCH_TDI R594 1 DCI@ 2 0_0201_5% XDP_TDI PAD 1 @
R657 NO ASM NO ASM ASM 16 PCH_TDI IT10
PCH_TMS R593 1 DCI@ 2 0_0201_5% XDP_TMS PAD 1 @
R658 NO ASM NO ASM ASM 16 PCH_TMS IT11
PCH_TCK R99 1 @ 2 0_0201_5% PCH_TCK1 PAD 1 @
16 PCH_TCK IT12
R102 NO ASM ASM NO ASM JTAGX R591 1 DCI@ 2 0_0201_5% XDP_TCK0 PAD 1 @
16 JTAGX IT13
R597 NO ASM ASM NO ASM
R9907 NO ASM ASM ASM

2
R58
JXDP1 NO ASM ASM NO ASM 51_0402_1%
@
C70 NO ASM ASM NO ASM

1
R96 NO ASM ASM NO ASM
R101 NO ASM ASM NO ASM
R9909 NO ASM ASM ASM R224 1 DCI@ 2 0_0201_5% XDP_TDO
6 PROC_TDO
R9910 NO ASM ASM ASM R222 1 DCI@ 2 0_0201_5% XDP_TDI
6 PROC_TDI
R9916 NO ASM ASM ASM R221 1 DCI@ 2 0_0201_5% XDP_TMS
6 PROC_TMS
R99 NO ASM ASM ASM R219 1 DCI@ 2 0_0201_5% XDP_TCK0
6 PROC_TCK
R9912 NO ASM ASM ASM
C C
R9934 NO ASM ASM ASM

2
DCI@
RC176
R9930 NO ASM ASM ASM 51_0402_1%
R9931 NO ASM ASM ASM Mount RC17 to enable
DCI function

1
+3VALW +3VALW_PCH
R9932 NO ASM ASM ASM +3V_SPI +1.05VALW

R9933 NO ASM ASM ASM

2
R225 R226 R228 R229
LOGIC 2.2K_0402_5% 2.2K_0402_5% 1K_0402_5% 1K_0402_5%
@ @ @ @
TABLE : PCH ITP DEBUG REPORT

1
@
R233 1 2 1K_0402_5% PAD 1 @
16,49 EC_RSMRST# 1 IT14
PAD @
No use Individual DCI 2.0 18 SPI_SI_XDP
PAD 1 @
IT15
16 ITP_PMODE IT16
Port w/o connector 16,49 PBTN_OUT#
PAD 1 @
IT17
PAD 1 @
16 SYS_RESET# IT18
R230 1 DCI@ 2 0_0402_5% PAD 1 @
R93 NO ASM ASM NO ASM 6 CFG3 IT19
need change to 1 5K refer CRB
JXDP1 NO ASM ASM NO ASM lace within 500mil of T-connection
R9917 NO ASM ASM NO ASM
R101 NO ASM ASM NO ASM
R9908 NO ASM ASM NO ASM
R9911 NO ASM ASM NO ASM
B R9913 NO ASM ASM NO ASM B

R9915 NO ASM ASM NO ASM R220 1 DCI@ 2 0_0402_5% R595 1 @ 2 0_0402_5% XDP_TRST# PAD 1 @
22 CPU_TRST# IT20
PCH_PRDY# R657 1 @ 2 0_0402_5% XDP_PRDY# PAD 1 @
22 PCH_PRDY# IT21
PCH_PREQ# R658 1 @ 2 0_0402_5% XDP_PREQ# PAD 1 @
GTTw
P
P
_
BDE

8
_

O
_
R
E¨ 
B 
O 
OR T
TR P

22 PCH_PREQ# IT22
LOGIC +3VS


 fP
 




 
 
( T
P h
(C 
DH 

fw 

 
 
 c
) 

〃
*
O
 
 
 y
 
 
¨

 
 
 
 
 
 
 
 
h 
 f

PROC_TRST#
〃 6 PROC_TRST#
Ch






/







)




TABLE : Functional Strap R223 1 DCI@ 2 0_0402_5%

6 PROC_PRDY#




g

I

X
D

1

GPP_B18/GSPI0_MOSI (No Reboot) R563 R217 1 DCI@ 2 0_0402_5%

6 PROC_PREQ#
R563
HIGH Enable "No Reboot" Mode ASM 1K_0402_5% Place near PCH
@
LOW Disable "No Reboot" Mode (Default ) NO ASM LOGIC
2

GPP_B18_NO_REBOOT
GPP_B18_NO_REBOOT 20

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 XDP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540 2.0

Date: Friday, March 22, 2019 Sheet 56 of 77

5 4 3 2 1
 5 4 3 2 1

SA0000 0U00 S IC PS8331BQFN 0GTR-A QFN 0P DP SWITCH symbol & foot rint a ly
U4405
VDD33 +3VS
V1 0
CPU_EDP_TX0+ C10247 1 2 0.1u_0201_10V6K IN1D0P IN1D1N 5 50 PD
8 CPU_EDP_TX0+ IN1_D1n PD
VDD33 21 49 R10705 1 2 0_0603_5%
CPU_EDP_TX0- C10248 1 2 0.1u_0201_10V6K IN1D0N IN2AUX 30 VDD33_1 VDD33_4 47
8 CPU_EDP_TX0- IN2_PEQ 51 IN2_AUXp CEXT 46 MUX_EDP_TX0+
CPU_EDP_TX1+ C10252 1 2 0.1u_0201_10V6K IN1D1P 57 IN2_PEQ/SCL_CTL OUT_D0p 45 MUX_EDP_TX0-
8 CPU_EDP_TX1+ GND_5 OUT_D0n 1
44 EDP_HPD
CPU_EDP_TX1- C10250 1 2 0.1u_0201_10V6K IN1D1N OUT_HPD 42 MUX_EDP_TX1- C10273
D 8 CPU_EDP_TX1- PCH_EDP_HPD RM863 IN1_HPD OUT_D1n 2.2U_0402_6.3V6M D
1 2 0_0201_5% 3 41
CPU_EDP_TX2+ 15 PCH_EDP_HPD IN1_HPD GND_4 2
C10255 1 2 0.1u_0201_10V6K IN1D2P IN1D1P 4
8 CPU_EDP_TX2+ IN1_D1p
CPU_EDP_TX2- C10256 1 2 0.1u_0201_10V6K IN1D2N V1 0 IN1D2P 6 40 MUX_EDP_TX2+
8 CPU_EDP_TX2- IN1_D2p OUT_D2p MUX_EDP_TX2-
IN1D2N 7 39
CPU_EDP_TX3+ C10253 1 2 0.1u_0201_10V6K IN1D3P IN1D3P 9 IN1_D2n OUT_D2n 37 MUX_EDP_TX3+ VDD33
8 CPU_EDP_TX3+ 10 IN1_D3p OUT_D3p 36 MUX_EDP_TX3-
IN1D3N
CPU_EDP_TX3- C10254 1 2 0.1u_0201_10V6K IN1D3N IN2D0N 12 IN1_D3n OUT_D3n 35 VDD33
8 CPU_EDP_TX3- IN2_HPD 13 IN2_D0n VDD33_3 34 MUX_REXT R7700 1 21/20W_4.99K_+-1%_0201
IN2D1N 15 IN2_HPD REXT 32 MUX_EDP_AUX
IN2_D1n OUT_AUXp_SCL 2
CPU_EDP_AUX C10249 1 2 0.1u_0201_10V6K IN1AUX IN2D2P 16 31 MUX_EDP_AUX#
8 CPU_EDP_AUX IN2_D2p OUT_AUXn_SDA C10272
CPU_EDP_AUX# C10251 1 2 0.1u_0201_10V6K IN1AUX# 27 IN1AUX# 0.1u_0201_10V6K
8 CPU_EDP_AUX# 24 IN1_AUXn 26 1
VDD33
25 IN2_SDA VDD33_2 29 IN2AUX#
IN2_SCL IN2_AUXn 28 IN1AUX
22 IN1_AUXp
23 IN1_SDA
IN1_SCL 48 CA_DET R10681 1 2 1M_0402_5%
CA_DET 38 PC0
GPU_EDP_TX0+ C10257 1 2 0.1u_0201_10V6K IN2D0P IN1D0N 2 PC0
25 GPU_EDP_TX0+ VDD33 IN1_D0n 43 MUX_EDP_TX1+
GPU_EDP_TX0- C10258 1 2 0.1u_0201_10V6K IN2D0N IN1D0P 1 OUT_D1p 33
25 GPU_EDP_TX0- 60 IN1_D0p GND_3
VDD33
GPU_EDP_TX1+ C10259 1 2 0.1u_0201_10V6K IN2D1P VDD33_5
25 GPU_EDP_TX1+ MUX_EDP_TX0+
56 PI0

C10268

C10275

C10269

C10274

0.1u_0201_10V6K
0.01U_0201_10V6K

0.01U_0201_10V6K
GPU_EDP_TX1- PI0 MUX_EDP_TX0+ 39
C10260 1 2 0.1u_0201_10V6K IN2D1N IN2D2N 17 55 PC1

0.1u_0201_10V6K
25 GPU_EDP_TX1- IN2_D2n PC1 EDP_MUX_SW MUX_EDP_TX0-
2 1 1 2 IN2D3N 20 54
GPU_EDP_TX2+ IN2_D3n SW I2C_CTL_EN MUX_EDP_TX0- 39
C10261 1 2 0.1u_0201_10V6K IN2D2P 53
25 GPU_EDP_TX2+ IN1_AEQ# I2C_CTL_EN MUX_EDP_TX1+
59 8
GPU_EDP_TX2- IN2_AEQ# IN1_AEQ# GND_1 MUX_EDP_TX1+ 39
C10262 1 2 0.1u_0201_10V6K IN2D2N 58
25 GPU_EDP_TX2- 1 2 2 1 IN2_AEQ# 11 MUX_EDP_TX1-
IN2D0P
GPU_EDP_TX3+ IN2_D0p MUX_EDP_TX1- 39
C10263 1 2 0.1u_0201_10V6K IN2D3P 19 IN2D3P
25 GPU_EDP_TX3+ 14 IN2_D3p 52 IN1_PEQ MUX_EDP_TX2+
IN2D1P
GPU_EDP_TX3- Place near to PIN 0 1 9 IN2_D1p IN1_PEQ/SDA_CTL MUX_EDP_TX2+ 39
C10264 1 2 0.1u_0201_10V6K IN2D3N 18 61
25 GPU_EDP_TX3- GND_2 GND_6 MUX_EDP_TX2-
MUX_EDP_TX2- 39
C MUX_EDP_TX3+ C
GPU_EDP_AUX MUX_EDP_TX3+ 39
C10266 1 2 0.1u_0201_10V6K IN2AUX PS8331BQFN60GTR-A1_QFN60_5X9
25 GPU_EDP_AUX MUX_EDP_TX3-
GPU_EDP_AUX# MUX_EDP_TX3- 39
C10265 1 2 0.1u_0201_10V6K IN2AUX#
25 GPU_EDP_AUX# MUX_EDP_AUX#
MUX_EDP_AUX# 39
MUX_EDP_AUX
MUX_EDP_AUX 39
MUX_EDP_AUX# R10682 1 2 100K_0201_5%
VDD33
+1.8VS_AON MUX_EDP_AUX R10707 1 2 100K_0201_5%
@
IN1_AEQ# R7718 1 21/20W_4.7K_5%_0201 VDD33
@

1
IN2_AEQ# R7717 1 21/20W_4.7K_5%_0201
+5VS VDD33
R10680
10K_0201_5% IN2AUX# R10716 1 @ 2 100K_0201_5%
VDD33
@
1 IN2AUX R10717 1 2 100K_0201_5%

2
C10276 V0
1U_0402_10V6K IFPD_HPD
2 29 IFPD_HPD VDD33
U4406
16 Q5822
Vcc 4 MMBT3904WH_SOT323-3
MUX_EDP_ENBKL 49

1
2 1A 7 C
14 PCH_EDP_ENBKL GPU_EDP_ENBKL_B 1B1 2A MUX_EDP_ENVDD 39 IN2_HPD
3 9 2 R10709 1 2 100K_0201_5% R10710 1 2 0_0201_5% R350
1B2 3A MUX_INVT_PWM 39 10K_0201_5%
5 12 B
14 PCH_EDP_ENVDD GPU_EDP_ENVDD_B 6 2B1 4A
1

3
2B2

2
11 15 1 1

2
14 PCH_EDP_PWM GPU_EDP_PWM_B 10 3B1 OE 1 EDP_MUX_SW C10401 R10711 C10400 PD
14 3B2 S 470P_25V_K_X7R_0201 C10399
4B1 100K_0201_5%
13 8 L: B1 2 EMC_NS@ 220P_25V_K_X7R_0201 220P_25V_K_X7R_0201

1
4B2 GND 17 H:B 2 2 @ V0

1
T-PAD V0 R351

1
CBT3257ABQ_DHVQFN16_2P5X3P5 1/20W_499_+-1%_0201 D Q5821
2 EDP_HPD
B
V0 MC request G EDP_HPD 39,57 B

2
1 S

3
L2N7002KWT1G_SOT323-3
C392
1U_6.3V_M_X5R_0201
2
+3VS
+3VS
U4408
1 5
OE Vcc
GPU_EDP_PWM 2 V0
29 GPU_EDP_PWM
2

IN_A
3 4 GPU_EDP_PWM_B RV1263
GND OUT_Y
4.7K_0402_5%
+3VALW
M74VHC1GT125DF2G_SC70-5
1

EDP_MUX_SW
1

RV1264
+3VS 10K_0201_5% VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
U4409

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
3

1 5

R7727

R7721

R7709

R7711

R7713

R7715
2

1
OE Vcc QV38B
D2

1
GPU_EDP_ENBKL 2 5 PJT7838_SOT363-6
29 GPU_EDP_ENBKL IN_A G2 @ @ @
3 4 GPU_EDP_ENBKL_B @ @ @
S2

GND OUT_Y

2
4

2
6

M74VHC1GT125DF2G_SC70-5 PI0 I2C_CTL_EN PC0 PC1 IN2_PEQ IN1_PEQ

QV38A

R7722

R7712

R7714
D1

1/20W_4.7K_5%_0201
EDP_SW 2

R7728

R7710

R7716
20 EDP_SW G1 PJT7838_SOT363-6

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
1

1
+3VS

0_0201_5%
S1

@ @ @ @ @
U4410
A A
1

1 5 Vgs(th)≤1.0V

2
OE Vcc
GPU_EDP_ENVDD 2
29 GPU_EDP_ENVDD IN_A
3 4 GPU_EDP_ENVDD_B
GND OUT_Y @
RM866 1 2 0_0201_5%
M74VHC1GT125DF2G_SC70-5

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 EDP MUX

DP_SW :Port switching control configuration Internal ull down
at ~150KΩ 3 3V I/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
L: In ut Port1 is selected default
H: In ut Port is selected
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 57 of 77

5 4 3 2 1
 5 4 3 2 1

+3VALW_AG AVCC3.3V_AG
KSI[0..7] +3VALW_AG AVCC3.3V_AG
50 KSI[0..7]
KSO[0..16] +3VALW_AG L24 1 2 HCB1608KF-181T20
50 KSO[0..16]
1 1 AG@

0.1U_0402_10V7K

0.1U_0402_10V7K
C272

C273

1000P_0402_50V7K
1 1

0.1U_0402_10V7K
1

C274

C275
R374
1.5K_0402_5% AG@ 2 AG@ 2
@ AG@ 2 AG@ 2 +3VALW_AG

2
USB20_P9_AGKB U22 R107081 2 0_0603_5%
D D
IT8176FN-56A-BX_QFN48_6X6 R10678 1 2 AG_SMCLK

17

18

32
7

8
1 5K Reserve for USB @ 2.2K_0402_5%
+3VALW_AG slave mode use V1 0

VCOREB2

VCOREB

VSTBY33_1
VSTBY33_2

AVCC33
D44 AG_AGND R10679 1 2 AG_SMDAT
1 2 2.2K_0402_5%

RB751V-40_SOD323-2 R10677 1 2 AGKB_INT

AG@ 1 2.2K_0402_5%
SMCLK0/PWM0/GPA0 2 CAPS_LED# 49,50 +3VALW_AG
AG_WRST# SMDAT0/PWM1/GPA1 AG_SMCLK NUM_LED# 49,50
R376 2 1 10K_0402_5% 3
AG@ SMCLK1/PWM2/GPA2 4 AG_SMDAT
SMDAT1/PWM3/GPA3
1
C276 PAD 1 @ 1 1

0.1U_0402_10V7K

0.1U_0402_10V7K
T8

C277

C278
1U_0402_6.3V6K
AG@
2
48 AG@ 2 AG@ 2
WRST#
5
PWM5/GPA5 47 SYSTEM_STATUS2 49
L23
19 USB20_N9
USB20_N9 1
1 2
2 USB20_N9_AGKB
IT8176FN-56A/BX PWM4/GPA4 LED_KB_PWM 49,50
+3VALW_AG

QFN48
USB20_P9 4 3 USB20_P9_AGKB
19 USB20_P9 4 3 19
EXC24CH900U_4P 20 DM
DP
AG@
R379 1 @ 2 0_0402_5%

2
G
R380 1 @ 2 0_0402_5% 45
C FN_KEY 49 C
TXD/GPA7 46
37 RXD/GPA6 SYSTEM_STATUS1 49
KSI0
KSI1 38 KSI0/ADC16/STB#/GPD0 AG_SMCLK 1 6 EC_SMB_CK0

S
KSI1/ADC17/AFD#/GPD1 EC_SMB_CK0 41,49

D
KSI2 39

5
KSI3 40 KSI2/ADC18/INIT#/GPD2

G
KSI4 41 KSI3/ADC19/SLIN#/GPD3 Q5820A
KSI5 42 KSI4/ADC20/GPD4 2N7002KDWH_SOT363-6
KSI6 43 KSI5/ADC21/GPD5
KSI7 44 KSI6/ADC22/GPD6 AG_SMDAT 4 3 EC_SMB_DA0

S
KSI7/ADC23/GPD7 EC_SMB_DA0 41,49

D
KSO0 9 34 KB_BL_CONFIG
KSO1 10 KSO0/PD0/GPE0 ADC0/GPC0 35 R106731 2 0_0402_5% Q5820B 2N7002KDWH
KSO2 11 KSO1/PD1/GPE1 ADC1/GPC1 36 F2_KEY 20 Vth= min 1V, max 2.5V
2N7002KDWH_SOT363-6
KSO2/PD2/GPE2 ADC2/GPC2 AGKB_INT 49
KSO3 12 ESD 2KV
KSO4 13 KSO3/PD3/GPE3
KSO5 14 KSO4/PD4/GPE4
KSO6 15 KSO5/PD5/GPE5
KSO7 16 KSO6/PD6/GPE6 SA000081L30 S IC IT817 FN-5 A/BX-L0 C NTR L Y5 0 for SVT bom
KSO8 22 KSO7/PD7/GPE7
KSO9 23 KSO8/ACK#/GPF0
KSO10 24 KSO9/BUSY/GPF1
KSI7 PAD 1 @ KSO11 25 KSO10/PE/GPF2
1 IT7604 26 KSO11/ERR#/GPF3
KSI6 PAD @ KSO12
IT7603 27 KSO12/SLCT/GPF4
KSO13
KSO17 1 @ T12 KSO14 28 KSO13/GPF5
KSO15 29 KSO14/GPF6
KSO15/GPF7
SYST M_STATUS1 SYST M_STATUS
KSO16 30
KSO17 31 KSO16/SMCLK2/GPG0
KSO17/SMDAT2/GPG1

AVSS
VSS1
VSS2
L L S5

PAD
B B
L H S3
6
21

33

49
AG@ +3VALW

H L S0

2
R381
AG_AGND 0_0603_5%
KSI0

1
KSI1 +3VALW_AG +3VALW_AG
KSI2 R382
KSI3 +3VALW_IN 1 2
2

KSI4 @
KSI5 R384 0_0603_5%

10U_0603_25V6-M
KSI6 10K_0402_5% 1

2
KSI7 KB_BL_C NFIG KB Backlight @ C280
R383
1

KB_BL_CONFIG U23 AG@ 100K_0402_5%

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

1 1 1 1 1 1 1 1
5 1 2
C282

C283

C284

C285

C286

C287

C288

C289

L Red @
2

IN OUT

1
R385 2
AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 GND
H RGB 10K_0402_5%
4 3 AGKB_PWR_OCB
49 AGKB_PWR_EN# ENB OCB
1

0.1U_0402_10V7K
C281
SY6288D20AAC_SOT23-5
AG@
AG@ 2
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Anti-ghost KB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 2.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Friday, March 22, 2019 Sheet 58 of 77
5 4 3 2 1
 5 4 3 2 1

HDMI Logo PCB MB GPU

ZZZ2 UV1 UV1
ZZZ1 HDMI@

S IC N18E-G1-KD-A1 BGA 2228 GPU, A.2 S IC N18E-G0-A1 BGA 2228 GPU 12 !

D
HDMI Logo PCB FY515 NM-C221 NS-C225/C226/C227 SA00009QU00 SA00009V300 D
RO00000040J DAZ1DG00101 N18EG1@ N18EG0@

CPU
UC1 i5@ UC1 i7@ UC1 i9@
PCH
UH1

S IC CL8068404121905 SRF6X U0 2.4G BGA 1440 S

12IC! CL8068404100301 QQLT P0 2.4G BGA
SA0000A0P10 SA0000A0N10 SA00009PG00 S IC FH82HM370 SR40B B0 BGA 874P PCH 12!
SA00009AG00

Samsung 6GB VRAM Micron 6GB VRAM SW5 15@ D1 15@ U5 15@ LED2 15@ LED301 15@ LED301 17@

ZZZ4 S6GX6@ ZZZ5 M6GX6@

SW EVQPQHB55 AZ5725-01F AH9247-W-7 B1931TX--05P-000314 B2972UDBS05P-000114 B2972UDBS05P-000114

SN100006P00 SC400008K00 SA00007RN00 SC50000DA00 SC50000FR00 SC50000FR00
SAMSUNG_6GB_VRAM MICRON_6GB_VRAM
X7646K12001 X7646K12002

SW5 7000P@ D1 7000P@ U5 7000P@

R3001 15@ R3001 17@
C C

SKU ID SW EVQPQHB55 AZ5725-01F AH9247-W-7

SN100006P00 SC400008K00 SA00007RN00 150_0402_5% 150_0402_5%
SD02815008J SD02815008J

RH157 15@ RH158 15@ RH153 N18EG1@ RH195 N18EG1@

modify by Grace

S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201 10K_0201_5% 10K_0201_5%
SD04310028J SD04310028J SD04310028J SD04310028J

RH157 7000P@ RH155 7000P@

RH159 N18EG0@ RH163 N18EG0@

S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201
SD04310028J SD04310028J
10K_0201_5% 10K_0201_5%
SD04310028J SD04310028J

RH152 17@ RH158 17@

B
S RES 1/20W 10K +-5% 0201 S RES 1/20W 10K +-5% 0201 B
SD04310028J SD04310028J

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Virtual symbol

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 59 of 77

5 4 3 2 1
 5 4 3 2 1

H1 H3 H5 NH6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_CT8P0B6P0D2P3 PAD_CT8P0D2P5 PAD_CT8P0B6P0D2P3 PAD_C5P0D5P0N PAD_ST8P0CB6P0D2P3
D D

H8 H9 H10 NH11 H12 H13 H14

HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_ST8P0D2P5

PAD_ST8P0D2P5 PAD_ST8P0CB8P0D2P5 PAD_O2P5X3P1D2P5X3P1N PAD_ST8P0D2P5 PAD_ST8P0D2P5 PAD_CB6P0D2P3

CHASSIS1_GND

H15 H16 H17 H18 H19 H20 H21 H22 NH23 NH24 H23 H24
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1

1
PAD_CT5P5D3P2 PAD_CT5P5D3P2 PAD_CT5P5D3P0 PAD_CT5P5D3P0 PAD_CT5P5D3P2 PAD_CT5P5D3P2 PAD_CT5P5D3P2 PAD_C8P0D4P5 PAD_C2P5D2P5N PAD_O2P5X3P1D2P5X3P1N PAD_CT8P0D2P5 PAD_CT8P0D2P5

add by Bing 04/08

C C
SH9 ME@ SH13 ME@ SH16 ME@

1 1 1
1 1 1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH10 ME@ SH14 ME@

1 1 SH17 ME@
1 1
1
1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH11 SHIELDING_SUL-35A2M_9P2X3P3_1P
ME@
SH15 ME@
1
1 1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P
SHIELDING_SUL-35A2M_9P2X3P3_1P

SH12 ME@

1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P

B SO-DIMM Shielding B

FD1 FD2 FD3 FD4 FD5 FD6 FD7

1

V1 0

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Blank

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
C
Y540 2.0

Date: Friday, March 22, 2019 Sheet 60 of 77

5 4 3 2 1
 5 4 3 2 1

B+ +5VLP/ 100mA
Richtek Silergy
Adaptor RT6585B +5VALW/10A SY8032 +1.0VGS/2A
D
C_ N_5V N1 Switch Mode Converter
D

FOR SYS ALW_PWRGD 1V0_MAIN_ N N

230W/20V PG D FOR GPU PG D
Page 0
Page 70
C_ N N +3VLP/ 100mA

+3VALW/ 8A GMT
G9661 +2.5V/600mA
SYS N N LDO
FOR DDR PG D

Richtek Page
+1.2V/10A
RT8231
Switch Mode +0.6VS/1A
SYS N S5 FOR DDR Silergy
SM_PG_CTRL S3 Page 1 PG D +1.8VALW/3.4A
SY8033
C_ N_1 8V N Converter
FOR GPU PG D

Silergy Page 70
TI SY8286 +1.05VALW/ 6A
C
BQ24780SRUYR Converter C

C_ N_1V N FOR PCH PG D

Battery Charger Page 3

Switch Mode
Page 59 AOS
RT8237E FBVDDQ/ 20A
Converter
VRAM_VDDQ_ADJ N PG D VDDQPWR K
FOR GPU
Page 9
SMBus

Silergy
SY8286 VCCIO/ 6A
Converter
SUSP# N FOR CPU PG D VCCI _PG
Page

MPS VCC_CORE/80A/124A

B
MP2949 VCCGT/25A/32A B
Switch Mode
FOR CPU Core VCCSA/10A
CPUC R _ N N
Page 5- 8 PG D
CPU_PWRGD

Battery Richtek
Li-ion RT8813D NVVDD/60A/127A
3S1P/57WH Switch Mode
NVVDD_ N N FOR GPU NVVDD PG D NVVDD_PWRGD
Page 71

Richtek
NCP81278 NVVDDS/18A/30.7A
Switch Mode
NVVDDS_ N N FOR GPU NVVDD PG D NVVDDS_PWRGD
Page 71

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Power Diagram

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 2.0

Date: Friday, March 22, 2019 Sheet 61 of 77

5 4 3 2 1
 5 4 3 2 1

PL101 EMC@
HCB2012KF-121T50_0805 +3VL
7 31 change PF101 from 1 A T 5A for 30W ada tor SP0 000 900 1 2

1
PL102 EMC@ VIN
HCB2012KF-121T50_0805
1 2
PR101 @
0_0603_5%
VCCRTC
JDCIN1
PL103 EMC@
RTC_VCC

2
1 PF101 HCB2012KF-121T50_0805 PR103
GND_1 2 1 2 1 2 PR102 PD101
APDIN 47K_0402_1%
POWER_1 VCCRTC_D_R 0_0603_5% VCCRTC_D
3 2 1 2 1 3
DETECT(ID) 4 25A_24V_F1206HB25V024TM
POWER_2 @
5 @ 1

0.1U_0402_25V6
GND_2

0.1U_0402_25V6
D D
6

1000P_0402_50V7K

1000P_0402_50V7K
EMC_NS@
GND_3

EMC_NS@
RTC_VCC_R

PC101 EMC@

PC104 EMC@
7 1 2 2
GND_4 For 15"

PC103
1

1
PC102
JRTC1 PR104
HIGHS_PJSSS56-B4000-1H ADAPTER_ID 49,63 BAT54CW_SOT323-3
1K_0603_5%

2
ME@ 1
1 2
2

1
3 PC105
GND1 4
GND2
1U_0402_10V6K
@

2
HIGHS_WS33021-S0351-HF
ME@

GND4 16
GND3 15
GND2 14
13
GND1
12 12
VMB BATT+
11 11 PL104 EMC@
C 10 10 HCB2012KF-121T50_0805 C
9 9 1 2
8 8 EC_SMCA
7 7 EC_SMDA
6 PL105 EMC@
6 5 HCB2012KF-121T50_0805
3

1
5 4 PC106 1 2 PC107
4 3 1000P_0402_50V7K 0.01U_0402_25V7K
3 2 EMC@ EMC@
2

2
2 1
1
1

JBATT1
100_0402_1%

SUYIN_125022HB012M200ZL
PR105
1

ME@
100_0402_1%
PR106

2
2

PD103 EC_SMB_CK1 49,63,69,75

AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 49,63,69,75

PR107 1 2 100K_0402_1%
+3VALW

BATT_TEMP_IN 1 2
BATT_TEMP 49,63 A/D
PR108
10K_0402_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-DCIN/BATT/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size Document Number
Y540 Rev
2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Friday, March 22, 2019 Sheet 62 of 77
5 4 3 2 1
 5 4 3 2 1

7 31 change PQ 01 from A N 3 to PSMN R0-30YL for 30W ada tor 7 31 change PQ 0 from A N 1 to A N 3 for 30W ada tor

PQ201
SMN2R0-30YLE PQ202
AON6366E_DFN8-5 7 31 change PR 01 from 10mohm to 5mohm for 30W ada tor
P2 PR201 V20B+
VIN 1 1 P3 0.005_1206_1%
2 2
5 3 3 5 1 4

2 3

EMC_NS@

EMC_NS@
0.01U_0402_25V7K

0.01U_0402_25V7K
4

4
1

1
D D

PC203

PC204
1

1
PC202
PC201 0.022U_0402_25V7K

2
470P_0402_50V7K PR202

2
4.7_0603_5% PQ203

5
AONS32314_DFN8-5

2
1 2

PC205 780s_BATDRV 4

1
PC206 0.1U_0402_25V6 PC207
0.1U_0402_25V6 0.1U_0402_25V6

BQ24780_ACN
BQ24780_ACP
2

3
2
1
1
PR203
499K_0402_1% PC208
VIN BATT+ 0.01U_0402_25V7K

2
2
780s_ACDRV_R

3
PD201 V20B+
BAT54CW_SOT323-3

1780s_VCC_R
1

0.1U_0402_25V6
VIN

10U_0805_25V6K

10U_0805_25V6K
1

2
EMC@
8 1 add 10mohm resistor for ower test

PC211
4.02K_0603_1%

4.02K_0603_1%

ACN
ACP
PR206

PR207

PC212
BQ24780S_VDD

PC209
2

1
1

5
PR209
2

1
PR210 PR208 PC213 10_1206_5% PQ205

D
6.2K_0603_1% 39K_0603_1% 1U_0603_25V6K AON7408L_DFN8-5

ACN
ACP
C 1 2 C

2
1 2 780s_VCC 28 24 1 2

2
VCC REGN 2.2U_0603_10V6-K PC214 4
2 1 780s_ACDET 6 PC216 G
PC215 ACDET 0.047U_0603_16V7K

S3
S2
S1
0.01U_0402_25V7K 25 780s_BS
1 2780s_BS_R
2 1
BTST PR211 PR213
BATT+

3
2
1
2.2_0603_5% 0.01_1206_1%
780s_CMSRC 3 26 780s_HG PL201
CMSRC HIDRV 1 2 1 4
780s_ACDRV 4 4.7UH_PCMB063T-4R7MS_5.5A_20%
ACDRV 2 3

0.1U_0402_25V6
27 780s_LX

10U_0805_25V6K

10U_0805_25V6K
PHASE

EMC@
@ PR216