Ex. No.

: 4 Date:02-11-2023
Design of full adders circuits
Aim: To show the design of half adder circuit in and its truth
table on PSpice Simulator.
Apparatus/Tool required:
ORCAD / PSpice simulator - > 7400 Library – 7408, 7432 &
7486
Source Library - Digclock
Simulation Settings: Analysis Type - Time Domain
Run to time: 8ms (for Full Adder)
Circuit Diagram:
Full – Adder Circuit:
Theory:
Full Adder Circuit
A full adder circuit is a combinational logic circuit that adds
three binary digits (bits) and produces two binary digits as
output. The three input bits are A, B, and Cin, where A and B
are the two operand bits and Cin is the carry bit from the
previous addition stage. The two output bits are Sum (S) and
Carry Out (Cout).
Truth Table:
Model Timing
Diagram: Full – Adder:
Procedure:
1) Open PSpice and create the circuit diagram using
Source library and 7400 library.
2) Now, Create a new simulator under Pspice tab.
3) Now, click on analysis type and choose time-
Transient Domain.
4) Now, make sure to enter the time delay value
as 4ms(denotes 4miliseconds) and
then click on apply.
5) Apply the suitable voltage markers and run the program
to get the desired graphs.
Results:
Inference:
Full Adder is the adder that adds three inputs and produces
two outputs. The first two inputs are A and B and the third
input is an input carry as C-IN. The output carry is designated
as C-OUT and the normal output is designated as S which is
SUM.
The C-OUT is also known as the majority 1’s detector, whose
output goes high when more than one input is high.
A full adder logic is designed in such a manner that can
take eight inputs together to create a byte-wide adder and
cascade the carry bit from one adder to another. we use a
full adder because when a carry-in bit is available, another 1-
bit adder must be used since a 1-bit half-adder does not take
a carry-in bit.
A 1-bit full adder adds three operands and generates 2-bit
results.
The output waveform of half adder is verified.

02-11-2023