AP4111 Manual Electronic System Design

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AP4111 Manual
Electronics & Communication Engineering (Anna University)
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EXP. NO: 1 Design of a 4-20 mA transmitter for a bridge type

transducer.
DATE :
AIM:
To design an Instrumentation amplifier with the bridge type transducer and
convert the amplified voltage from the instrumentation amplifier to 4 – 20 mA current
using op-amp.
APPARATUS REQUIRED:
S.No Name of the Apparatus Range Quantity
1 Operational Amplifier IC741 4
10KΩ 10
2 Resistor 1kΩ 4
150Ω 1
3 DRB - 1
4 Dual Power Supply (0-24V) 1
5 Rheostat (0-100Ω) 1
6 Ammeter (0-250µA) 1
7 Multimeter - 1
THEORY:
INSTUMENTATION AMPLIFIER:
Instrumentation amplifier is generally required in any measurement system using

electrical transducers to enhance signal levels often in low voltage less than mV. Also it
is required to provide impedance matching and isolation. When the desired input rides
over a common mode signal special amplifier are needed so that difference signals get
amplified to an acceptable level while the common mode signals get attenuated.
The physical quantities can be converted into electrical quantities by using

transducer. The output of the transducer needs to be amplified to get the meter
readings. This amplification is done by using instrumentation amplifier. The output of
instrumentation amplifier drives of indicator or display system. The important features
of an instrumentation amplifier are high gain accuracy, high CMRR, high gain stability
with low temperature co-efficient, low dc offset, low output impedance.
Low input impedance may load the signal source heavily. Therefore high
resistance buffer is used preceding each input to avoid this loading effect. For V1 =V2
under common mode condition. If V’2 =V2 and V’1 =V1 both the operational amplifiers
act as voltage follower. If V1 V2 the circuit has differential gain by the formula VO/ (V2-
V1)=1+(2R/R‘).

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CIRCUIT DIAGRAM:
BRIDGE CIRCUIT:
INSTRUMENTATION AMPLIFIER:

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DESIGN:
Output voltage VO = (1 + ( 2R / R‘)) (V2 -V1)
Differential gain Ad = VO / (V2 - V1)
= 1 + (2R / R‘)
Choose R = 10kΩ
For Ad max = 100
100 = 1 + (20k/R‘)
R’ = 20K Ω / 99
R’ max = 200Ω.
For Ad min = 10
10 = 1 + (20k/R‘)
R’ min = 2.2KΩ.
IL = I1+I2
I1 = (V-(V0/2)) / R
I2 = (V0-(V0/2)) / R
IL = (V-(V0/2) + (V0-(V0/2)) / R
= (V-V0+V0) / R = V/R
IL is independent of RL. If R is constant, then IL αV
PROCEDURE:
1. The connections are made as per the circuit diagram.
2. The bridge circuit was balanced by varying 100Ω Rheostat.
3. The output voltage V1 and V2 of balanced circuit were given as input to the op-amp
A1 and A2.
4. Varying the resistance R1 the bridge circuit the voltage V1 and V2 were varied.
5. Varying the R’ the output voltage was measured then the differential gain was
calculated using formula,
=20 log (VO/(V2 -V1)).
V to I CONVERTER:

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PIN DIAGRAM:
MODEL GRAPH:
TABULAR COLUMN:
Displacement
Output Voltage Output Voltage
from initial Gain (dB)
(V) (mA)
place (cm)

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RESULT:
Thus the Instrumentation amplifier was designed with the bridge type transducer and
the output was verified successfully.

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EXP. NO: 2 DESIGN OF AC/DC VOLTAGE REGULATOR USING SCR
DATE :
AIM:
(i)To design, construct and test a AC voltage regulator using SCR.
(ii)To design, construct and test a DC voltage regulator using SCR.
APPARATUS REQUIRED:
AC VOLTAGE REGULATOR:

1 Transformer 230V/12V 1
2 SCR 2P4M 2
3 Diode BY 127 2
100kΩ 2
4 Resistor
12K 1
5 Bread Board 1
6 Connecting Wires As Required
7 CRO 1
8 DRB 1
DC VOLTAGE REGULATOR:

1 Transformer 230V/24V 1
2 SCR TYN 604 2
3 Diode IN4001 2
4 Resistor 10k 2
5 Bread Board 1
6 Connecting Wires As Required
7 CRO 1
8 DRB 1
9 IC 7812 1
1000uf 1
10 Capacitors
100uf 1

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CIRCUIT DIAGRAM:

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THEORY:
The SCR is switched ON and OFF to regulate the output voltage in AC and DC voltage
regulator.
If the SCR is connected to AC supply and load, the power flow can be controlled
by varying the RMS value of AC voltage applied to the load and this type of power circuit
is caused as AC voltage regulator. Applications of AC voltage regulator are in heating on
load transformers for changing light controls, speed controls and polyphase controls,
induction motors and AC magnet controls for power transfer. Two types of power control
are normally used.
i)ON-OFF control
ii)Polyphase Angle control
AC regulators are those converter which converts fixed ac voltage directly to

variable ac voltage of the same frequency. The load voltage is regulated by controlling
the firing angle of SCRs. AC voltage controllers are thyristor based devices. The most
common circuit is the inverse parallel SCR pair in which two isolated gate signals are
applied. Each of the two SCRs are triggered at alternate half cycles of the supply and
the load voltage is part of input sine wave. The SCR is an unidirectional device like
diode, it allows current flow in only one direction but unlike diode, it has built-in feature
to switch ON and OFF. The switching of SCR is controlled by gate and biasing condition.
This switching property of SCR allows to control the ON periods thus controlling average
power delivered to the load.
In this circuit SCR1 is forward biased during positive half cycle and SCR2 is
forward biased during negative half cycle. SCR1 is triggered at the firing angle ωt=α and
supply voltage is impressed on the load resistance(RL). It conducts from the remaining
positive half cycle, turning OFF when the anode voltage becomes zero at ωt=π.
SCR2 is triggered at the firing angle ωt=α+π and conducts till ωt=2π. Hence the
load is alternating in polarity and is part of sine wave. The firing angle of both SCRs is
controlled by gate circuit. The conduction period of SCR is controlled by varying gate
signals within specified values of maximum and minimum gate currents.
For gate triggering, a signal is applied between the gate and cathode of the device.
AC sources are normally used as gate signals. This provides proper isolation
between power.

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PIN DETAILS:
MODEL GRAPH:

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If SCR’s are used to convert an AC voltage into DC voltage then they are known
as DC voltage regulators. Eg. Battery changes for high current capacity batteries in DC
voltage control only phase control is used. The transformer is used to step down the
voltage from 230V to 24V. This is given as input to bridge rectifier. The bridge rectifier
converts incoming ac signal to unidirectional wave. Therefore we get full wave rectifier
output at the output of bridge rectifier. This is given as input to SCR. The gate of SCR
is triggered with firing angle of α. During positive half cycle, diode D1 and D2 conducts
and during negative half cycle, diode D3 and D4 conducts. The full wave rectified output
is given to capacitive filter. The output of capacitor is dc that it eliminates ripple contents
of bridge rectifier output. The dc input is given to regulator IC. The unregulated output
must be 2V greater than regulated output voltage. The load current may vary from 0 to
rated maximum output current. The output voltage is regulated dc.
DESIGN:
AC VOLTAGE REGULATOR USING SCR:
Triggering circuit for SCR:
12 V ac is rectified by diode BY 127. SCR 2P4M is used to trigger.
Let the current be 1mA. R=V/I=12V/1mA=12KΩ.
DC VOLTAGE REGULATOR USING SCR:
Triggering circuit for SCR:
24 V ac is rectified by diode 1N4001. SCR TYN604 is used to trigger.
Let the current be 1mA. R=V/I=12V/1mA=12KΩ
PROCEDURE:
AC VOLTAGE REGULATOR USING SCR:

1. Connections are made as shown in the circuit diagram.
2. The supply is given by means of step down transformer.
3. Anode terminal of SCR1 is connected to the anode terminal of diode, is connected
to cathode of SCR1 by means of resistor as the load.
4. Hence the voltage regulation is verified at load terminal.
DC VOLTAGE REGULATOR USING SCR:

1. Connect the two terminals at the top of bridge rectifier.
2. The positive terminal of the bridge rectifier is connected to one terminal at the
load and at the other terminal to anode terminal of SCR.
3. The pin 15 connected from the power supply to the load.
4. Then the DC voltage regulation is checked and verified.

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TABULAR COLUMN:
DRB 1 value(KΩ) Amplitude (V) TON(ms)
DRB value(KΩ) Amplitude (V) TON(ms)

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RESULT:
Thus AC and DC voltage regulators were designed, constructed and the output
waveforms were drawn.

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CIRCUIT DIAGRAM:
Full Wave Rectifier Circuit
PCB LAYOUT TOP LAYER:
PCB LAYOUT BOTTOM LAYER:

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EXP. NO: 3 PCB LAYOUT DESIGN USING CAD
DATE :
AIM:
To design a PCB layout using CAD software for a Simple Electronic Circuit.
COMPONENTS REQUIRED:
1. Personal Computer
2. NI Multisim Software
PROCEDURE:
Multisim:- It is a schematic capture and simulation application that assists you in

carrying out the major steps in the circuit design flow. Multisim can be used for both
analog and digital circuits and also includes mixed analog/digital simulation capability,
and microcontroller co-simulation. Simulating the circuits before building them,
catches errors early in the design flow, saving time and money.
Ultiboard:- Ultiboard is fed from Multisim, is used to design printed circuit boards,
perform certain basic mechanical CAD operations, and prepare them for manufacturing.
Ultiboard also provides automated parts placement and layout
Steps:
1. In this exercise, you will place and wire the components in the circuit
2. Double click on the component and select ‘Edit footprint’.
3. Then click on ‘Select from Data base’.
4. Now Select the footprint [RES1300 – 7000C2500], and click [Select].
5. Transfer the schematic design to Ultiboard 10 by selecting Transfer » Transfer
to Ultiboard 10.
6. Select [Transfer] / [Transfer to Ultiboard 10]. A standard Windows Save As
dialog box appears. Specify the name and location of the files to be created and
click [Save]. Multisim creates files that can then be loaded into Ultiboard.
7. Enter the desired parameters and click [OK].
8. After click [OK] new window will pop-up
9. The dialog should appear after select [Transfer] / [Transfer to Ultiboard 10].
Change the width to 10 mils, and the clearance to 10 mils. Click [OK] to close
dialog box.

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10. Make sure all fields are selected in Import Netlist Action selection and click
[OK].
11. A board outline (a yellow rectangular) is placed on the workplace with the
components (above the board outline) ready to be placed
12. Working with the Board Outline. Right-click the edge of yellow rectangle
and select Properties from the menu. This launch a Rectangular Properties
dialog.
13. Under the rectangular tab, set the Units to mil, the Width to 1000 and the
Height to 900. Click OK to close the dialog box and the board outline becomes
much smaller
14. Now u can see the board outline becomes much smaller
15. Select the components and drag them until they are above the board
outline.
16. Select ‘view’ and click on ‘3D preview’.
17. Now you can see the 3D view dialog box
18. Select ‘Auto route’ and then select ‘Start/Resume Auto router’
19. Now the circuit become auto routed.
20. Place the components in preferred location and then check the design rule.
21. Select ‘start auto router trace optimisation’
22. After ‘start auto router trace optimisation’ the board will appear
23. Ultiboard Configuration. Select [Options] >> [Global Preferences], and then
select the General Settings tab. Make sure it matches below settings.
24. Select PCB Design tab and make sure you choose Auto trace narrowing and
Auto add teardrop. Click OK to close the dialog box.
25. Select [Options] >> [PCB Properties], and then go to Copper Layers tab.
Change Board thickness to 59.00 mil.
26. Next, go to the Pad/Vias tab, and modify the settings as shown. How to
calculate annular ring? For example, a 50 mil drill hole (radius of 25 mils) with
a relative value of .6 (60%) will create an annular ring of 15 mils (60% of 25
mils).
27. Go to Design Rules tab, and the “Use multiple clearances” checkbox must
be selected. Otherwise, only clearance to traces will be operational. Set the
“Clearance to Traces” parameter to 40.000000 mils; “Clearance to Pads”,
“Clearances to Vias” and Clearance to” Copper Areas” parameters to
32.000000 mils. Click OK to close dialog box.

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28. Power and Ground Planes. Select [Place] >> [Power plane]. Select net 0 for
Copper Bottom Layer. Click [OK] to close the dialog box. The bottom layer fills
in red color plane.
29. Now select ‘File’» ‘Print’ and then this dialog window will pop-up
30. Select ‘copper top’ alone then select ‘preview’.
31. Select ‘Tool’» view 3D. Then select full screen option.
RESULT:
Thus the schematic of simple electronic circuit and design of PCB layout using
CAD was done successfully.

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EXP. NO: 4 HDL based design entry and simulation of Parameterizable

cores of Counters, Shift registers, State machines, 8-bit Parallel
adders and 8 –Bit multipliers.
DATE :
4.1 SIMPLE COUNTER
AIM:
To design and verify its output of 4-bit Counter in Verilog HDL Code.
TOOLS REQUIRED:
i) PC
ii) Xilinx ISE 9.1i
PROCEDURE:
 Go to xilinx ISE 9.1i software

 Go to File -> New project -> Project name-> next -> New source -> Verilog
module -> File name -> next -> set i/p & o/p ports -> Finish
 Type the program in the space
 After the program is written go to Synthesis XST -> Check Syntax
 If the syntax is correct, proceed
 Go to Project -> New source -> Test bench waveform -> Save
 Click on combinational internal clock -> Set the input -> Save
 Towards left hand side change the source for behavioral simulation -> Click
on the file name which you saved for test bench waveform
 Go to Processes -> Xilinx ISE simulator -> Simulator behavioral mode ->
Generate Self checking test bench
 Go to (or) click on Simulate Behavioral mode
 Now the output waveform is displayed in the simulation dialog box

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COUNTER DIAGRAM:
4 BIT COUNTER GRAPH:
4 BIT COUNTER TRUTH TABLE:

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PROGRAM CODING:
module cnt
(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)
begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule
SIMULATION GRAPH:
RESULT:
Thus the design of 4-bit counter in Verilog HDL Code is done and its output is
verified successfully.

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4.2 Universal Shift Register
AIM:
To design and implement FPGA based Universal Shift Register using

VHDL.
TOOLS REQUIRED:
i) PC
ii) Xilinx ISE 9.1i
PROCEDURE:

THEORY:
Universal shift register is capable of converting input data to parallel or
serial which also does shifting of data bidirectional, unibirectional (SISO, SIPO,
PISO, PIPO) and also parallel load this is called Universal shift register.
Shift Register are used as: Data storage device, Delay element,
Communication lines, Digital Electronics devices (Temporary data storage, data
transfer, data manipulation, counter), etc.
PROCEDURE:
 The ALU circuit is designed and the Boolean function is found out.
 The Verilog Module Source for the circuit is written.
 It is implemented in Model Sim and Simulated.
 Signals are provided and Output Waveforms are viewed.

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CIRCUIT DIAGRAM
TABLE:
MODE CONTROL REGISTER
S1 S0 OPERATION
0 0 NO CHANGE
0 1 SHIFT LEFT
1 0 SHIFT RIGHT
PARALLEL
1 1
LOAD

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PROGRAM
module uni_shift_8b(op,clk,rst_a, load,sh_ro_lt_rt,ip);

output reg [7:0] op;
input load;
input [1:0] sh_ro_lt_rt;
input [7:0] ip;
input clk, rst_a;
reg [7:0]temp;
always @(posedge clk or posedge rst_a)

begin
if (rst_a)
op = 0;
else
case(load)
1'b1:
begin //Load Input
temp = ip;
end
1'b0: //Operation
case (sh_ro_lt_rt)
2'b00: op = temp<<1; //Left Shift
2'b01: op = temp>>1; //Right Shift
2'b10: op = {temp[6:0],temp[7]}; //Rotate Left
2'b11: op = {temp[0], temp[7:1]}; //Rotate Right
default: $display("Invalid Shift Control Input");
endcase
default: $display("Invalid Load Control Input");

endcase
end
endmodule

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OUTPUT
RESULT
Thus the Verilog programs for universal shift register were written,
synthesized, simulated and implemented using Xilinx tools and FPGA.

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4.3 FINITE STATE MACHINE
AIM:
To design a Finite State Machine and to verify its simulation results.
TOOLS REQUIRED:
iii) PC
iv) Xilinx ISE 9.1i
PROCEDURE:


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PROGRAM CODING:
modulefsm(input wire clk,rst,

input wire a,b,
output wire y0,y1 );
localparam [1:0] s0 = 2'b00,
s1 = 2'b01,
s2 = 2'b10;
reg [1:0]state_reg,state_next;
always @ (posedgeclk,posedgerst)
if (rst)
state_reg<=s0;
else
state_reg<= state_next;
always @ *
case (state_reg)
s0: if(a)
if(b)
state_next =s2;
else
state_next =s1;
,else
state_next =s0;
s1:if (a)
state_next =s0;
else
state_next = s1;
s2:state_next = s0;
default:state_next =s0;
endcase
//Mealy state machine
assign y1 = (state_reg ==s0)||(state_reg ==s1);
//Moore state machine
assign y0 = (state_reg==s0) & a & b;
endmodule

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SIMULATION OUTPUT:
RESULT:
Thus the design of finite state machine in Verilog HDL Code is done and its
output is verified successfully.

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4.4 ADDER 8-BIT
AIM:
To design and verify its output of a 8-bit adder in Verilog HDL Code.
TOOLS REQUIRED:
i) PC
ii) Xilinx ISE 9.1i
PROCEDURE:


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FULL ADDER CIRCUIT:
FULL ADDER TRUTH TABLE:
8-BIT ADDER:

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PROGRAM CODING:
module adder(a, b, ci, sum, co);

input ci;
input [7:0] a;
input [7:0] b;
output [7:0] sum;
output co;
wire [8:0] tmp;
assign tmp = a + b + ci;
assign sum = tmp [7:0];
assign co = tmp [8];
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the design of 8-bit adder in Verilog HDL Code is done and its output is
verified successfully.

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4.4 MULTIPLIER (4-Bit)
AIM:
To design a 4 Bit Multiplier and to verify its simulation results.
TOOLS REQUIRED:
i) PC
ii) Xilinx ISE 9.1i
PROCEDURE:

 Go to File New project -> Project name-> next -> New source -> Verilog

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BLOCK DIAGRAM:
TRUTH TABLE:

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PROGRAM CODING:
module fg(a, b, res);

input [3:0] a;
input [3:0] b;
output [7:0] res;
reg [7:0] res;
always @(a or b )
begin
res=a * b;
end
endmodule
SIMULATION OUTPUT:
RESULT:
Thus the simulation of 4 –bit Multiplier is done and the output is verified.

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Simple Distributed Arithmetic System

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EXP. NO: 5 HDL based design entry and simulation of Parameterizable cores
on the simple Distributed Arithmetic system. Test vector
generation and timing analysis.
DATE :
AIM:
To design and implement HDL based Distributed Arithmetic System using
Verilog and to obtain timing analysis report.
TOOLS REQUIRED:
i) PC
ii) Xilinx ISE 9.1i
PROCEDURE:

 Go to File New project -> Project name-> next -> New source -> Verilog
Distributed Arithmetic System
 Distributed Arithmetic (DA) is a technique that is bit serial in nature. It can

therefore appear to be slow
 It turns out that when the number of elements in a vector is nearly the same as
the word size, DA is quite fast
 DA `replaces’ the explicit multiplications by ROM look-ups Æ an efficient
technique to implement on Field Programmable Gate Arrays (FPGAs)
 In DA, multiplications are reordered and mixed such that the arithmetic
becomes “distributed” through the structure rather than being “lumped”
 Area savings from using DA can be up to 80% in DSP hardware designs
 While distributed arithmetic technique itself has been around for more than 30
years (Peled and Liu, 1974), interest in this has been revived by the use of Field
Programmable Gate Arrays (FPGAs) for DSP
 When DA is implemented in FPGAs, one can take advantage of memory in
FPGAs to implement the Multiply and Accumulate (MAC) operation

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Program:
module da (clk_80, rst_80, x_in_80, y_out_80);

input clk_80,rst_80;
input [3:0] x_in_80;
output [5:0] y_out_80;
reg [3:0] x0_80, x1_80, x2_80, x3_80, x4_80, x5_80;

wire [5:0] a0,a1,a2,a3;
reg [5:0] y_out_80;
wire cout0_80, cout1_80, cout2_80, cout00_80, oflow00_80, oflow0_80,
oflow1_80, oflow2_80;
wire [6:0] result0_80, result1_80, a3_comp_80, a3_sat_80;
wire [6:0] sat_result0_80, sat_result1_80;
wire [8:0] result2_80, sat_result2_80;
wire [5:0] y_rounded_80;
always @(posedge clk_80 or posedge rst_80)

begin
if (rst_80) begin
x0_80 <= 0;
x1_80 <= 0;
x2_80 <= 0;
x3_80 <= 0;
x4_80 <= 0;
x5_80 <= 0;
end
else begin
x0_80 <= x_in_80;
x1_80 <= x0_80;
x2_80 <= x1_80;
x3_80 <= x2_80;
x4_80 <= x3_80;
x5_80 <= x4_80;
end
end
//LookUp Table
lut l3
(.in_80({x5_80[3],x4_80[3],x3_80[3],x2_80[3],x1_80[3],x0_80[3]}),.out_80(a3));
lut l2
(.in_80({x5_80[2],x4_80[2],x3_80[2],x2_80[2],x1_80[2],x0_80[2]}),.out_80(a2));
lut l1
(.in_80({x5_80[1],x4_80[1],x3_80[1],x2_80[1],x1_80[1],x0_80[1]}),.out_80(a1));
lut l0
(.in_80({x5_80[0],x4_80[0],x3_80[0],x2_80[0],x1_80[0],x0_80[0]}),.out_80(a0));

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add a_1 (.dataa({a1,1'b0}), .datab({{a0[5]},a0}), .cout(cout0_80), .overflow(oflow0_80),

.result(result0_80));
add a_00 (.dataa({~a3[5:0],1'b1}), .datab({7'b1}), .cout(cout00_80),
.overflow(oflow00_80), .result(a3_comp_80));
add a_2 (.dataa(a3_sat_80), .datab({{a2[5]},a2}), .cout(cout1_80),
.overflow(oflow1_80), .result(result1_80));
add9 a (.dataa({sat_result1_80,2'b00}),
.datab({{2{sat_result0_80[6]}},sat_result0_80}), .cout(cout2_80), .overflow(oflow2_80),
.result(result2_80));
//Saturation Logic
saturation_logic s0 ( .sum_saturated_80(sat_result0_80), .sum_80(result0_80),
.carry_80(cout0_80), .oflow_80(oflow0_80) );
saturation_logic s00 ( .sum_saturated_80(a3_sat_80),
.sum_80({(rst_80)?7'b0:a3_comp_80}), .carry_80(cout00_80), .oflow_80(oflow00_80) );
defparam
s0.WIDTH_SUM = 7;
defparam
s00.WIDTH_SUM = 7;
defparam
s1.WIDTH_SUM = 7;
defparam
s2.WIDTH_SUM = 9;
rounding_logic r1( .prod_rounded_80(y_rounded_80), .prod_80(sat_result2_80) );
defparam
r1.WIDTH_PROD = 9,
r1.WIDTH_PROD_ROUNDED = 6;
always @(posedge clk_80 or posedge rst_80)
begin
if (rst_80) begin
y_out_80 <= 0;
end
else begin
y_out_80 <= y_rounded_80;
end
end
endmodule

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Result:
Thus the design and implementation of HDL based Distributed Arithmetic
System using Verilog was done and iming analysis was done successfully. .

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EXP. NO: 6 HDL based design entry and simulation of Parameterizable

cores on memory design and 4 – bit ALU. Synthesis, P&R and
post P&R simulation, Critical paths and static timing analysis
results to be identified. FPGA real time programming and I/O
interfacing
DATE :
AIM:
To design and implement FPGA based ALU using Verilog and to obtain
Synthesis, P&R and post P&R simulation, Critical paths and static timing
analysis synthesis report.
APPARATUS REQUIRED:
Synthesis Tools : Xilinx ISE.
Simulation Tools : Model sim Simulator.
Kit : FPGA Board- Spartan 3E
General : Personal Computer (PC).
THEORY:
It is a digital circuit that performs arithmetic and logical operations. The
ALU is a fundamental building block of the CPU of a computer and even the
simplest microprocessors contain of for purposes such as maintaining timers.
The processors found inside modern CPU’s and graphic processing units
accommodate very powerful and very complex ALU’s.
PROCEDURE:
 Go to xilinx ISE 9.1i software
 Go to File New project -> Project name-> next -> New source -> Verilog
 Type the program in the space
 After the program is written go to Synthesis XST -> Check Syntax
 If the syntax is correct, proceed
 Go to Project -> New source -> Test bench waveform -> Save
 Click on combinational internal clock -> Set the input -> Save
 Towards left hand side change the source for behavioral simulation -> Click
 Go to Processes -> Xilinx ISE simulator -> Simulator behavioral mode ->
 Go to (or) click on Simulate Behavioral mode
 Now the output waveform is displayed in the simulation dialog box

lOMoARcPSD|35477619
CIRCUIT DIAGRAM
OUTPUT

lOMoARcPSD|35477619
PROGRAM
module alu(y,a,b,cin,s);
output [7:0]y;
input [7:0]a,b;
input cin;
input [3:0]s;
reg [7:0]y;
always@(a,b,s)
begin
case(s)
4'b0000:y=a;
4'b0001:y=a+1;
4'b0010:y=a-1;
4'b0011:y=b;
4'b0100:y=b+1;
4'b0101:y=b-1;
4'b0110:y=a+b;
4'b0111:y=a+b+cin;
4'b1000:y=~a;
4'b1001:y=~b;
4'b1010:y=a&b;
4'b1011:y=a/b;
4'b1100:y=~(a&b);
4'b1101:y=~(a/b);
4'b1110:y=a^b;
4'b1111:y=~(a^b);
endcase
end
endmodule

lOMoARcPSD|35477619
SYNTHESIS REPORT:
====================================================
* Final Report *
====================================================
Final Results
RTL Top Level Output File Name : alu.ngr
Top Level Output File Name : alu
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 29
Cell Usage :
# BELS : 208
# GND :1
# INV :1
# LUT1 :7
# LUT2 : 27
# LUT3 : 41
# LUT4 : 28
# MUXCY : 21
# MUXF5 : 34
# MUXF6 : 16
# MUXF7 :8
# VCC :1
# XORCY : 23
# IO Buffers : 29
# IBUF : 21
# OBUF :8
====================================================
Device utilization summary:
---------------------------
Selected Device : 3s250epq208-4
Number of Slices : 54 out of 2448 2%
Number of 4 input LUTs : 104 out of 4896 2%
Number of IOs : 29
Number of bonded IOBs : 29 out of 158 18%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
====================================================
TIMING REPORT
Clock Information:
------------------

lOMoARcPSD|35477619
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -4
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 11.772ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
====================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 708 / 8
-------------------------------------------------------------------------
Delay : 11.772ns (Levels of Logic = 9)
Source : b<1> (PAD)
Destination: y<7> (PAD)
Data Path : b<1> to y<7>
Gate Net
Cell : in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF : I->O 12 1.218 1.136 b_1_IBUF
(Madd_y_addsub00022)
LUT4 : I0->O 3 0.704 0.566
Madd_y_addsub0002_xor<4>111 (N172)
LUT3 : I2->O 2 0.704 0.482
Madd_y_addsub0002_xor<6>111 (N6)
LUT3 : I2->O 1 0.704 0.499 Madd_y_addsub0002_xor<7>11
LUT3 : I1->O 1 0.704 0.000 Mmux_y_722 (N55)
MUXF5 : I0->O 1 0.321 0.000 Mmux_y_5_f5_14
(Mmux_y_5_f515)
MUXF6 : I1->O 1 0.521 0.000 Mmux_y_4_f6_6
(Mmux_y_4_f67)
MUXF7 : I0->O 1 0.521 0.420 Mmux_y_2_f7_6 (y_7_OBUF)
OBUF : I->O 3.272 y_7_OBUF (y<7>)
----------------------------------------
Total 11.772ns (8.669ns logic, 3.103ns route)
(73.6% logic, 26.4% route)
====================================================
CPU : 5.67 / 6.31 s | Elapsed : 5.00 / 6.00 s

lOMoARcPSD|35477619
PLACE AND ROUTE ANALYSIS:

lOMoARcPSD|35477619
POWER ANALYSIS:
Power summary: I(mA) P(mW)

----------------------------------------------------------------
Total estimated power consumption : 52
---
Vccint 1.20V : 15 19
Vccaux 2.50V : 12 30
Vcco25 2.50V : 2 4
---
Inputs : 0 0
Logic : 0 0
Outputs:
Vcco25 0 0
Signals : 0 0
---
Quiescent Vccint 1.20V : 15 19
Quiescent Vccaux 2.50V : 12 30
Quiescent Vcco25 2.50V : 2 4
Thermal summary:
----------------------------------------------------------------
Estimated junction temperature : 27C
Ambient temp : 25C
Case temp : 26C
Theta J-A : 37C/W
STATIC TIMING ANALYSIS:
Data Sheet report:

-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
a<0> |y<0> | 12.114|
a<0> |y<1> | 13.434|
a<0> |y<2> | 13.182|
a<0> |y<3> | 13.898|
a<0> |y<4> | 13.927|
a<0> |y<5> | 13.342|
a<0> |y<6> | 13.354|
a<0> |y<7> | 14.080|
a<1> |y<1> | 12.826|
a<1> |y<2> | 12.811|
a<1> |y<3> | 13.524|

lOMoARcPSD|35477619
a<1> |y<4> | 13.592|

a<1> |y<5> | 13.114|
a<1> |y<6> | 13.054|
a<1> |y<7> | 13.729|
a<2> |y<2> | 11.459|
a<2> |y<3> | 12.349|
a<2> |y<4> | 12.650|
a<2> |y<5> | 12.065|
a<2> |y<6> | 12.125|
a<2> |y<7> | 12.803|
a<3> |y<3> | 11.963|
a<3> |y<4> | 12.691|
a<3> |y<5> | 12.149|
a<3> |y<6> | 12.197|
a<3> |y<7> | 12.764|
a<4> |y<4> | 13.375|
a<4> |y<5> | 12.800|
a<4> |y<6> | 13.327|
a<4> |y<7> | 13.555|
a<5> |y<5> | 12.420|
a<5> |y<6> | 12.953|
a<5> |y<7> | 13.679|
a<6> |y<6> | 12.856|
a<6> |y<7> | 13.258|
a<7> |y<7> | 12.448|
b<0> |y<0> | 11.869|
b<0> |y<1> | 13.658|
b<0> |y<2> | 13.406|
b<0> |y<3> | 14.122|
b<0> |y<4> | 14.151|
b<0> |y<5> | 13.566|
b<0> |y<6> | 13.578|
b<0> |y<7> | 14.304|
b<1> |y<1> | 12.136|
b<1> |y<2> | 12.121|
b<1> |y<3> | 12.834|
b<1> |y<4> | 13.040|
b<1> |y<5> | 12.651|
b<1> |y<6> | 12.759|
b<1> |y<7> | 13.368|
b<2> |y<2> | 11.375|
b<2> |y<3> | 12.545|
b<2> |y<4> | 13.065|
b<2> |y<5> | 12.316|
b<2> |y<6> | 12.571|
b<2> |y<7> | 12.799|
b<3> |y<3> | 12.111|
b<3> |y<4> | 12.661|
b<3> |y<5> | 12.371|

lOMoARcPSD|35477619
b<3> |y<6> | 12.509|

b<3> |y<7> | 13.295|
b<4> |y<4> | 11.862|
b<4> |y<5> | 11.375|
b<4> |y<6> | 11.814|
b<4> |y<7> | 12.342|
b<5> |y<5> | 11.194|
b<5> |y<6> | 11.970|
b<5> |y<7> | 12.198|
b<6> |y<6> | 11.576|
b<6> |y<7> | 12.064|
b<7> |y<7> | 12.238|
cin |y<0> | 12.673|
cin |y<1> | 13.026|
cin |y<2> | 13.635|
cin |y<3> | 14.631|
cin |y<4> | 14.879|
cin |y<5> | 14.130|
cin |y<6> | 14.385|
cin |y<7> | 14.613|
s<0> |y<0> | 11.005|
s<0> |y<1> | 10.529|
s<0> |y<2> | 10.972|
s<0> |y<3> | 12.755|
s<0> |y<4> | 11.764|
s<0> |y<5> | 12.522|
s<0> |y<6> | 11.937|
s<0> |y<7> | 11.965|
s<1> |y<0> | 10.323|
s<1> |y<1> | 10.524|
s<1> |y<2> | 10.508|
s<1> |y<3> | 11.030|
s<1> |y<4> | 11.779|
s<1> |y<5> | 11.269|
s<1> |y<6> | 11.811|
s<1> |y<7> | 11.822|
s<2> |y<0> | 10.556|
s<2> |y<1> | 10.144|
s<2> |y<2> | 10.121|
s<2> |y<3> | 10.643|
s<2> |y<4> | 11.222|
s<2> |y<5> | 10.714|
s<2> |y<6> | 10.783|
s<2> |y<7> | 11.038|
s<3> |y<0> | 9.914|
s<3> |y<1> | 9.231|
s<3> |y<2> | 9.254|
s<3> |y<3> | 9.763|
s<3> |y<4> | 10.134|

lOMoARcPSD|35477619
s<3> |y<5> | 9.301|

s<3> |y<6> | 10.120|
s<3> |y<7> | 10.374|
---------------+---------------+---------+
Analysis completed Mon Mar 21 10:57:12 2022
--------------------------------------------------------------------------------
Peak Memory Usage: 112 MB

lOMoARcPSD|35477619
RESULT
Thus the design and implement FPGA based ALU using VHDL was done
successfully and Synthesis, P&R and post P&R simulation, Critical paths and
static timing analysis synthesis report was obtained.

lOMoARcPSD|35477619

lOMoARcPSD|35477619
EXP. NO :7 DESIGN OF FPGA BASED MEMORIES (RAM)

DATE :
AIM
To design and implement FPGA based memories (RAM) using Verilog.
APPARATUS REQUIRED
Synthesis Tools : Xilinx ISE.
Simulation Tools : Model sim Simulator.
Kit : FPGA Board- Spartan 3E
General : Personal Computer (PC) with Parallel to JTAG
cable.
THEORY
Random Access Memory (RAM) is a type of computer data storage. Its
mainly used as main memory of a computer. RAM allows to access the data
in any order, i.e random. The word random thus refers to the fact that any
piece of data can be returned in a constant time, regardless of its physical
location and whether or not it is related to the previous piece of data. You
can access any memory cell directly if you know the row and column that
intersect at that cell. Most of the RAM chips are volatile types of memory,
where the information is lost after the power is switched off. There are some
non-volatile types such as, ROM, NOR-Flash.
PROCEDURE
 Go to xilinx ISE 9.1i software
 Go to File New project -> Project name-> next -> New source -> Verilog
 Type the program in the space
 After the program is written go to Synthesis XST -> Check Syntax
 If the syntax is correct, proceed
 Go to Project -> New source -> Test bench waveform -> Save
 Click on combinational internal clock -> Set the input -> Save
 Towards left hand side change the source for behavioral simulation ->
Click on the file name which you saved for test bench waveform
 Go to Processes -> Xilinx ISE simulator -> Simulator behavioral mode ->
 Go to (or) click on Simulate Behavioral mode
 Now the output waveform is displayed in the simulation dialog box

lOMoARcPSD|35477619
CIRCUIT DIAGRAM
PROGRAM
module rammod (clk, we, addr, din, dout);
input clk;
input we;
input [4:0] addr;
input [3:0] din;
output [3:0] dout;
reg [3:0] ram [31:0];
reg [3:0] dout;
always @(clk)
begin
if (we)
ram[addr] <= din;
else
dout <= ram[addr];
end
endmodule

lOMoARcPSD|35477619
OUTPUT
RESULT
Thus the Verilog programs for memories (RAM) were written, synthesized,
simulated and implemented using Xilinx tools and FPGA.

lOMoARcPSD|35477619

lOMoARcPSD|35477619
EXP. NO: 8 Realization of Discrete Fourier transform/Fast Fourier

Transform algorithm in HDL and observing the spectrum in
simulation.
DATE :
AIM:
To realize a Fast Fourier Transform algorithm in HDL and observe the spectrum
in simulation.
TOOLS REQUIRED:
iii) PC
iv) Xilinx ISE 9.1i
PROCEDURE:

Fast Fourier Transform:
The FFT is a fast algorithm for computing the DFT. If we take the 2-point DFT and 4-
point DFT and generalize them to 8-point, 16-point, ..., 2r -point, we get the FFT
algorithm. To compute the DFT of an N-point sequence using equation (1) would take
O(N2 ) multiplies and adds. The FFT algorithm computes the DFT using O(N log N)
multiplies and adds.
Below is a diagram of an 8-point FFT, where W = W8 = e−iπ/4 = (1 − i)/√2

lOMoARcPSD|35477619
PROGRAM:
module four_fft( a,b,c,d,A,Ai,B,Bi,C,Ci,D,Di);

input [3:0] a;
input[3:0] b;
input[3:0] c;
input[3:0] d;
output [5:0] A;
output [5:0] Ai;
output[5:0] B;
output [5:0] Bi;
output[5:0] C;
output [5:0] Ci;
output[5:0] D;
output [5:0] Di;
assign A = a+b+c+d;
assign Ai=0;
assign B=a-c;
assign Bi=b-d;
assign C= a+c-b-d;
assign Ci=0;
assign D=a-c;
assign Di= b-d;
endmodule

lOMoARcPSD|35477619
WAVEFORM:
RESULT:
Thus a Fast Fourier Transform algorithm in HDL was realized and the spectrum
was observed successfully.

lOMoARcPSD|35477619
Program:
module sdpll(i_clk, i_ld, i_step, i_ce, i_input, i_lgcoeff, o_phase, o_err);

parameter PHASE_BITS = 32;
parameter [0:0] OPT_TRACK_FREQUENCY = 1'b1;
localparam MSB=PHASE_BITS-1;
//
input wire i_clk;
//
input wire i_ld;
input wire [(MSB-1):0] i_step;
//
input wire i_ce;
input wire i_input;
input wire [4:0] i_lgcoeff;
output wire [PHASE_BITS-1:0] o_phase;
output reg [1:0] o_err;
endmodule

lOMoARcPSD|35477619
EXP. NO: 9 Invoke PLL module and demonstrate the use of the PLL for clock
generation in FPGAs. Verify design functionality implemented in
FPGA by capturing the signal in Oscilloscope
DATE :
AIM:
To Invoke PLL module and demonstrate the use of the PLL for clock generation in
FPGAs
TOOLS REQUIRED:
 PC
 Xilinx ISE 9.1i
 FPGA Kit
 CRO
PROCEDURE:

Phase Locked Loop (PLL)
A phase-locked loop (PLL) is an electronic circuit with a voltage or voltage-driven

oscillator that constantly adjusts to match the frequency of an input signal. PLLs are
used to generate, stabilize, modulate, demodulate, filter or recover a signal from a
"noisy" communications channel where data has been interrupted. At its simplest, a
phase-locked loop is a closed-loop feedback control circuit that's both frequency- and
phase-sensitive
The main goal of a PLL is to synchronize the output oscillator signal with a
reference signal. Even if the two signals have the same frequency, their peaks and
troughs may not occur in the same place.

lOMoARcPSD|35477619
Output Waveform:

lOMoARcPSD|35477619
A PLL reduces phase errors between output and input frequencies. When the
phase difference between these signals is zero, the system is said to be "locked." And
this locking action depends on the PLL's ability to provide negative feedback
A PLL consists of three key components:
 Phase detector (also known as a phase comparator or mixer) - It compares the

phases of two signals, and generates a voltage according to the phase difference.
It multiplies the reference input and the voltage-controlled oscillator output.
 Voltage-controlled oscillator - Generates a sinusoidal signal, whose frequency
closely matches the center frequency provided by the low-pass filter.
 Low-pass filter - A kind of loop filter that attenuates the high-frequency
alternating current (AC) component of the input signal to smoothen and flatten
the signal to make it more DC-like.
PLLs are used in dozens of applications; among them are:

•telecommunications systems
•computers
•radio
•other electronic systems

lOMoARcPSD|35477619

lOMoARcPSD|35477619
Results:
Thus the PLL module designed and use of the PLL for clock generation in FPGAs
was demonstrated successfully.

lOMoARcPSD|35477619
Flowchart:
START
Include header file
Define DIP switch
EXECUTE
NO
If LED turns
on when
switch on
YE
END

lOMoARcPSD|35477619
EX.NO: 10 INTERFACING DIP SWITCH WITH ARM 7 PROCESSOR
DATE:
Aim:
To write an embedded C program for interfacing DIP switch with ARM Processor
using Keil-C.
Apparatus Required:
1. PC
2. Keil – C Software
3. Flash Magic Software
4. ARM Processor Kit
Algorithm:
1. Start the program.
2. Include LPC2148 header file.
3. Define GPIO
4. Define DIP Switch
5. Define Delay
6. Execute the program
7. End the program.

lOMoARcPSD|35477619
Program:
#include<LPC214x.h> // Define LPC2148 Header File
#define LED 16 // Define LED to Port1 // LED start @ p1.16 ( total led -> 8 no.
#define Switch 24 // Define SWITCH TO Port1 // SWITCH start @ p1.23 (total switch -> 8 no.
Void delay (int x);
int main(void)
{
unsigned char Status=1;
PINSEL2 = 0x00000FF0; // Define p1.16... P1.31 port lines as GPIO (DIP SW - I/O))
IO1DIR = 0x00 << Switch; //Configure P1.24 - P1.31 as Input -> (0)
IO1DIR|= 0xFF << LED; //Configure P1.16 - P1.23 as Output -> (1)
While (1) // Loop forever
{
Status = 1;
IOSET1 = 0xFF << LED;
delay (10);
IOCLR1 = 0xFF << LED;
delay (30);
while (~Status)
{
Status = ((IO1PIN & (0xFF << Switch)) >> Switch);
IO1PIN = ((~Status) << LED);
}
}
}
Void delay (int x) // Delay function
{
Unsigned int y, z;
For(y = x; y > 0; y--)
For (z = 0; z < x; z++);
}
PIN DETAILS:
Connect J15 & J16 using 10 pin FRC cable
SWITCH PORT PIN CONFIGURATION
Sw 1 P1.24 uC PIN -> 32
Sw 2 P1.25 uC PIN -> 28
Sw 3 P1.26 uC PIN -> 24
Sw 4 P1.27 uC PIN -> 64
Sw 5 P1.28 uC PIN -> 60
Sw 6 P1.29 uC PIN -> 56
Sw 7 P1.30 uC PIN -> 52
Sw 8 P1.31 uC PIN -> 20
OUTPUT:

lOMoARcPSD|35477619
Inference:
With this experiment, concept of interfacing the DIP Switch with LPC 2148
ARM Processor kit can be understood.
Result:
Thus embedded C program for interfacing of Buzzer were written and it was
executed in LPC2148 ARM Processor and its output was verified successfully.

lOMoARcPSD|35477619
Flowchart:
START
Include header file
Define Buzzer
Set Delay
EXECUTE
NO
If motor
rotates
YE
END

lOMoARcPSD|35477619
EX.NO: 11 INTERFACING BUZZER WITH ARM 7 PROCESSOR
DATE:
Aim:
To write an embedded C program for interfacing Buzzer with ARM Processor using
Keil-C.
Apparatus Required:
1. PC
Algorithm:
3. Define GPIO
4. Define Buzzer pin
6. End the program.

lOMoARcPSD|35477619
PROGRAM:
void delay(int x);
int main(void)
{
PINSEL0 = 0x00021000; // Define port lines as GPIO
IO0DIR = 0x00000400; // IOPIN0 Define P0.10 as dirction -> o/p
IOPIN0 = 0x00000000; // IOPIN0 Define P0.10 as zero
while(1) // Loop forever
{
IOPIN0 = 0x00000400; // Turn ON P0.10
delay(2000); // delay(2000) ; 2000 -> means delay time, if you want you have to change delay
time
IOPIN0 = 0x00000000; // Turn OFF P0.10
delay(2000); // delay(2000) ; 2000 -> means delay time, if you want you have to change
delay time
}
}
void delay(int x) // Delay function
{
unsigned int y,z;
for(y = x;y > 0;y--)
for(z = 0;z < x;z++);
}
PIN DETAILS:
PIN DETAILS: connect J17 & J19 using 10 pin FRC cable
PORT PIN CONFIGURATION
Buzzer P0.10 uC PIN -> 35
OUTPUT:

lOMoARcPSD|35477619
Inference:
With this experiment, concept of interfacing the Buzzer with LPC 2148 ARM
Processor kit can be understood.
Result:
Thus embedded C program for interfacing of DIP Switch were written and
it was executed in LPC2148 ARM Processor and its output was verified successfully.

lOMoARcPSD|35477619
Flowchart:
START
SET integer int x;

SET GPIO PINS NO
YES
If DELAY
value is set
EXECUTION
END

lOMoARcPSD|35477619
EX.NO : 12 INTERFACING OF LED WITH ARM 7 PROCESSOR

DATE :
Aim:
To write an embedded C program for Blinking LED in LPC2148 ARM Processor using
Keil-C.
Apparatus Required:
1. PC
Algorithm:
3. Define GPIO pins
4. Define port lines
5. Set delay value for ON and OFF.
7. End the program.

lOMoARcPSD|35477619
Program:
void delay(int x);
int main (void)
{
PINSEL2 = 0x00000000; // Define port lines as GPIO
IO1DIR = 0x00FF0000; // Define P1.16 - P1.23 as O/P
IOPIN1 = 0x00000000; // Define P1.16 - P1.23 as zero
While (1) // Loop forever
{
IOPIN1 = 0x000FF000; // Turn ON P1.16 - P1.23
Delay (2000); // delay (2000); 2000 -> means delay time, if you want
you have to change delay time
IOPIN1 = 0x00000000; // Turn OFF P1.16 - P1.23
Delay (2000); // delay (2000); 2000 -> means delay time, if you want you
have to change delay time
}
}
Void delay (int x) // Delay function

{
Unsigned int y, z;
For(y = x;y > 0;y--)
For (z = 0; z < x; z++);
}
PIN DETAILS:
PIN DETAILS: connect J8 & J9 using 10 pin FRC cable
LED PORT PIN CONFIGURATION
LED1 P1.16 uC PIN -> 16
LED2 P1.17 uC PIN -> 12
LED3 P1.18 uC PIN -> 8
LED4 P1.19 uC PIN -> 4
LED5 P1.20 uC PIN -> 48
LED6 P1.21 uC PIN -> 44
LED7 P1.22 uC PIN -> 40
LED8 P1.23 uC PIN -> 36
Output:

lOMoARcPSD|35477619
Inference:
With this basic LED Blinking experiments, basic steps in LPC2148 ARM
Processor can be understood easily. And concept of setting delay value for blinking LED
can be understood.
Result:
Thus embedded C program for Blinking LED were written and it was
executed in LPC2148 ARM Processor and its output was verified successfully.

lOMoARcPSD|35477619

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AP4111 Manual Electronic System Design

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lOMoARcPSD|35477619

Electronics & Communication Engineering (Anna University)

Studocu is not sponsored or endorsed by any college or university

EXP. NO: 1 Design of a 4-20 mA transmitter for a bridge type

Instrumentation amplifier is generally required in any measurement system using

The physical quantities can be converted into electrical quantities by using

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IL is independent of RL. If R is constant, then IL αV

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EXP. NO: 2 DESIGN OF AC/DC VOLTAGE REGULATOR USING SCR

(i)To design, construct and test a AC voltage regulator using SCR.

(ii)To design, construct and test a DC voltage regulator using SCR.

S.No Name of the Apparatus Range Quantity

S.No Name of the Apparatus Range Quantity

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AC regulators are those converter which converts fixed ac voltage directly to

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AC VOLTAGE REGULATOR USING SCR:

Triggering circuit for SCR:

12 V ac is rectified by diode BY 127. SCR 2P4M is used to trigger.

Let the current be 1mA. R=V/I=12V/1mA=12KΩ.

DC VOLTAGE REGULATOR USING SCR:

Triggering circuit for SCR:

24 V ac is rectified by diode 1N4001. SCR TYN604 is used to trigger.

Let the current be 1mA. R=V/I=12V/1mA=12KΩ

AC VOLTAGE REGULATOR USING SCR:

DC VOLTAGE REGULATOR USING SCR:

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DRB 1 value(KΩ) Amplitude (V) TON(ms)

DRB value(KΩ) Amplitude (V) TON(ms)

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Full Wave Rectifier Circuit

PCB LAYOUT TOP LAYER:

PCB LAYOUT BOTTOM LAYER:

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EXP. NO: 3 PCB LAYOUT DESIGN USING CAD

Multisim:- It is a schematic capture and simulation application that assists you in

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EXP. NO: 4 HDL based design entry and simulation of Parameterizable

4.1 SIMPLE COUNTER

 Go to xilinx ISE 9.1i software

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4 BIT COUNTER GRAPH:

4 BIT COUNTER TRUTH TABLE:

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4.2 Universal Shift Register

To design and implement FPGA based Universal Shift Register using

 Go to xilinx ISE 9.1i software

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