19ec401 - Ec1 - 2021 - 2022 Lab Manual PDF

19EC401-ELECTRONICSCIRCUITS-I LAB
LAB EXPERIMENTS
EXPT DATE EXPERIMENT NAME MARKS SIGN

NO
1 Regulated DC Power supply
2 Frequency Response of Common Emitter Amplifier
3 Frequency Response of Common Base Amplifier
4 Frequency Response of Common Drain Amplifier
5 Frequency Response of Common Source FETAmplifier
6 Frequency Response of Darlington Amplifier
7 Frequency Response of Cascode Amplifier
8 Frequency Response of Cascade Amplifier
9 Transfer Characteristics of Differential Amplifier
10 Frequency Response of Common Drain FET Amplifier

EX.NO. 1 DATE:
REGULATED POWER SUPPLY
AIM:
To design a +5 V DC regulated power supply. Also to determine the load regulation and
efficiency of the regulated power supply.
APPARATUS REQUIRED:
S.NO NAME RANGE QUANTITY
1 DSO 50MHz 1
2 Multi meter - 1
3 Diode 1N4007 4
4 Transformer 230V/12-0-12; 500mA 1
5 Decade Resistance Box - 1

6 Regulator IC 7805 1
7 Capacitor 10μf, 1
0.1μf 2
8 Bread board - 1
9 Connecting Wires Single strand As required
THEORY
Every electronic circuit is designed to operate off of supply voltage, which is usually
constant. A regulated power supply provides this constant DC output voltage and continuously
holds the output voltage at the design value regardless of changes in load current or input
voltage. The power supply contains a rectifier, filter, and regulator. The rectifier changes the AC
input voltage to pulsating DC voltage. The filter section removes the ripple component and
provides an unregulated DC voltage to the regulator section. The regulator is designed to deliver
a constant voltage to the load under varying circuit conditions. The two factors that can cause the
voltage across the load to vary are fluctuations in input voltage and changes in load current
requirements.Load regulation is a measurement of power supply, showing its capacity to
maintain a constant voltage across the load with changes in loadcurrent.
BLOCK DIAGRAM
CIRCUIT DIAGRAM
AC INPUT WAVEFORM
SIGNAL OUTPUT (WITHOUT FILTER)
OUTPUT WITH FILTER
MODEL GRAPH (LOAD REGUALTION)
TABULATION
FWR WITHOUT FILTER
For RL=1 K
Vm Vrms=Vm/√2 Vdc=Vm/π P 2=V
/RDLCDC P=V
AC AC
2/R
L EFFICIENCY=
(V) (V) (V) (W) (W) P P
DC/ AC
FWR WITH FILTER
For RL=1 K
P P =VAC2/R
Vm Vrms=Vm/√2 Vdc=Vm/π 2=V
/RDLCDC EFFICIENCY=
LAC
(V) (V) (V) (W) (W) P P
DC/ AC
LOAD REGULATION
S.NO RL(Ohms) Output voltage(V)
PROCEDURE
➢ Connect the circuit as per the circuitdiagram
➢ Apply 230V AC from the mains supply.
➢ Observe the following waveforms usingoscilloscope
(i) Waveform at the secondary of thetransformer
(ii) Waveform after rectification. Change DSO to AC mode as well as DC mode and note down
DC Voltage in the output.
(iii) Waveform after filtercapacitor
(iv) Voltage of Regulated DC output, using DC mode ofDSO.
Load Regulation
➢ Change the resistance value (load) and measure the varying outputvoltage.
➢ Observe the No load voltage and Full loadvoltage
➢ Calculate the loadregulation.
➢ Load Regulation = ((VNL – VFL)/VFL) x 10
RESULT
Thus the regulated power supply was designed and the following results were determined.
1. Output at the secondary ofthe transformer -------------- V
2. Outputafterrectification ------------------------ V
3. Output afterfiltercapacitor--------------------- V
4. Voltage of RegulatedDC output ------------------- V
5. Efficiency ------------------ %
EXP NO: 2 DATE:15.8.2020
FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER
AIM
To Design and Construct a Common Emitter Amplifier and to determine its:
➢ Q-Point
➢ Maximum signal handling capacity
➢ Gain of theamplifier
➢ Bandwidth of theamplifier
➢ Gain –BandwidthProduct
APPARATUS REQUIRED
1 Transistor BC 107 1
2 Resistor 33 KΩ, 2.2 KΩ, 10 KΩ, 1 KΩ Each 1
3 Capacitor 4.7 µF 2
100µf 1
4 Function Generator 0-1 MHz 1
5 DSO 50MHz 1
Regulated DC power
6 (0-30)V 1
supply
THEORY
A common emitter amplifier is type of BJT amplifier which increases the voltage level
of the applied input signal Vinat output of collector. The CE amplifier typically has a relatively
high input resistance (1 - 10 KΩ) and a fairly high output resistance. Therefore it is generally
used to drive medium to high resistance loads. It is typically used in applications where a small
voltage signal needs to be amplified to a large voltage signal as in radioreceivers.
The input signal Vinis applied to base emitter junction of the transistor and amplifier
output Vo is taken across collector terminal. Transistor is maintained at the active region by
using the resistors R1, R2 and Rc. A very small change in base current produces a much larger
change in collector current. The output Voof the common emitter amplifier is 180 degrees out of
phase with the applied the input signalVin.
MAXIMUM SIGNAL HANDLING (MSH) CAPACITY
➢ It is the amplitude of input for which the output is not distorted. Designed circuit can’t
handle any input more than this amplitude (output start toclipp)
➢ For the safer side the half of the amplitude of MSH will be given as input to thecircuit
➢ Apply a sine wave input signal of any amplitude to the amplifier using the signal
generator to common emitter amplifier. Monitor the sinusoidal output using DSO across
RL.
➢ Vary the amplitude of the input measure from signal generator. Find the amplitude of
the input for which the amplifier output starts to clip/distort. The maximum amplitude of
an input which produces the output without any distortion is maximum signal handling
capacity.
V MSH= volts
PROCEDURE
➢ Connect the circuit as per the circuitdiagram.
DC ANALYSIS
➢ Set Vin = 0 by reducing the amplitude of the input signal from signalgenerator.
➢ Open circuit the capacitors, since it blocks DCvoltage.
➢ Set VCC= +12v and measure Ic, VCE by connecting voltmeter between collector and
emitter and VBE, by connecting voltmeter between base andemitter
Q-P OINTCONDITION
ICQ -------------------------- mA
VCEQ ------------------ V
RL.
➢ Vary the amplitude of the input from signal generator. Find the amplitude of the input
for which the amplifier output starts to clip/distort. The maximum amplitude of an input
which produces the output without any distortion is maximum signal handlingcapacity.
V MSH= volts
FREQUENCY RESPONSE
➢ From the value of VMSH, calculate the input signal amplitude as Vin=V MSH/2
➢ Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 20Hz
to 3MHz in incremental steps and note down the corresponding output voltageVo
➢ The voltage gain is calculated as Av = 20log (VO/VIN)dB
➢ Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph takingfrequency
on X-axis and gain in dB onY-axis.
➢ Bandwidth, BW = f2-f1 where f1and f2is 3dB lower and upper cut-offfrequencies.
CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION
Vin=1V
GAIN=20log(VO/Vin)
S.NO FREQUENCY (HZ) VO (V) VO/Vin (V)
(dB)
RESULT:
The Common Emitter Amplifier was constructed and the following results were
observed.
1. Maximum signalhandlingcapacity ----------------- V
2. Q-point:ICQ ------------------------- mA
VCEQ ------------------ V
3. Gain ofthe amplifier -------------------- dB
4. Bandwidth oftheamplifier --------------------Hz
5. Gain –Bandwidth Product-------------------------
EXP NO: 3 DATE:
FREQUENCY RESPONSE OF COMMON BASE AMPLIFIER

AIM
To Design and Construct a Common Base Amplifier and to determine its:
➢ Q-Point
➢ Maximum signal handlingcapacity
APPARATUS REQUIRED
10 KΩ, 33 KΩ, 4.7 KΩ,

2 Resistor Each 1
1 KΩ
3 Capacitor 1µF 3
4 Signal Generator (0-1)MHz 1
5 DSO 50MHz 1
6 Regulated DC power supply (0-30)V 1
THEORY
A common base amplifier is type of BJT amplifier which increases the voltage
level of the applied input signal Vin at output of collector.
The Common base amplifier typically has good voltage gain and relatively high output
impedance. But the Common base amplifier unlike CE amplifier has very low input
impedance which makes it unsuitable for most voltage amplifier. It is typically used as
an active load for a cascode amplifier and also as a current follower circuit.
CIRCUIT OPERATION
A positive-going signal voltage at the input of a CB pushes the transistor emitter
in a positive direction while the base voltage remains fixed, hence VBE reduces. The
reduction in VBE results in reduction in VRC, consequently VCE increases. The rise in
collector voltage effectively rises the output voltage. The positive going pulse at the
input produces a positive-going output, hence the there is no phase shift from input to
output in CB circuit. In the same way the negative-going input produces a negative-
going output.

RL.
capacity.
V MSH= volts
PROCEDURE
DC ANALYSIS
Q-P OINTCONDITION
ICQ -------------------------- mA
VCEQ ------------------ V
RL.
V MSH= volts
FREQUENCY RESPONSE
➢ the input voltage Vin=V MSH /2 and vary the input signal frequency from 20Hz to 3MHz
in incremental steps and note down the corresponding output voltageVo
CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION
Vin=
GAIN=20log(VO/Vin)
(dB)
RESULT
The common base amplifier was constructed and the following results were
observed.
1. Maximum signalhandlingcapacity ------------------ V
2. Q-point:ICQ ------------------------- mA
VCEQ -------------------V
3. Gain ofthe amplifier--------------------- dB
4. Bandwidth oftheamplifier -------------------- Hz
EXP NO: 4 DATE:
FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER
AIM
To Design and Construct a Common collector Amplifier and to determine its:
➢ Q-Point
APPARATUS REQUIRED
2 Resistor 33 KΩ, 6 KΩ, 10 KΩ Each 1
3 Capacitor 4.7 µf 2
4 Function Generator (0-1)MHz 1
5 DSO 50MHz 1
6 Regulated power supply (0-30)V 1
THEORY
A common collector amplifier is a unity gain BJT amplifier used for impedance
matching and as a buffer amplifier.
Circuit Operation
When a positive half-cycle of the input signal is applied to Base emitter junction of
transistor the forward bias voltage Vbe is increased, which in turn increases the base current
IBof transistor. Since emitter current IE is directly proportional to Ib the voltage drop across
the Emitter VE= IERE is increased, hence, output voltage Vo is increased, thus, we get
positive half- cycle of the output. It means that a positive-going input signal results in a
positive going output signal and, consequently, the input and output signals are in phase
with each other. Similarly the negative half cycle of input signal produces negative going
outputsignal.
Characteristics of a CC Amplifier
1. high input impedance (20-500KΩ)
2. low output impedance(50-1000Ω)
3. high current gain of (1 + β) i.e. 50–500
4. voltage gain of less than1(unity)
5. power gain of 10 to20dB
6. No phase reversal of the inputsignal.

RL.
capacity.
V MSH= volts
PROCEDURE
DC ANALYSIS
Q-Q OINTCONDITION
ICQ -------------------------- mA
VCEQ ------------------ V

RL.
V MSH= volts
FREQUENCY RESPONSE
CIRCUIT DIAGRAM
MODEL GRAPH:
TABULATION
Vin=
GAIN=20log(VO/Vin)
(dB)
RESULT
The common collector amplifier was constructed and the following results were
observed.
2. Q-point:ICQ ------------------------- mA
VCEQ ------------------ V
3. Gain ofthe amplifier -------------------- dB
EXP NO: 5 DATE:
FREQUENCY RESPONSE OF COMMON SOURCE FET AMPLIFIER
AIM
To Design and Construct a Common source amplifier and to determine its:
APPARATUS REQUIRED
1 FET BFW1O 10
2 Resistor 1MΩ, 2.2 KΩ, 10 KΩ, Each 1

1 KΩ
3 Capacitor 1 µF 2
10 µF 1
5 DSO 30MHz 10
THEORY
There are three basic types of FET amplifier or common source amplifier,common
gate amplifier and source follower amplifier.The common-source (CS) amplifier may be
viewed as a transconductance amplifier or as a voltageamplifier.
i) As a transconductance amplifier, the input voltage is seen as modulating thecurrent
going to theload.
ii) As a voltage amplifier, input voltage modulates the amount of current flowingthrough
the FET, changing the voltage across the output resistance according to Ohm'slaw.
However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier (ideally infinite), nor low enough for a decent voltage amplifier
(ideally zero). Another major drawback is the amplifier's limited high-frequency response.
Therefore, in practice the output often is routed through either a voltage follower (common-drain
or CD stage), or a current follower (common-gate or CG stage), to obtain more favorable output
and frequency characteristics
➢ Apply a sine wave input signal of any amplitude to the amplifier using the signalgenerator to
common emitter amplifier. Monitor the sinusoidal output using DSO acrossRL.
➢ Vary the amplitude of the input from signal generator. Find the amplitude of the input for which
the amplifier output starts to clip/distort. The maximum amplitude of an input which produces
the output without any distortion is maximum signal handlingcapacity.
VMSH= volts
PROCEDURE
DC ANALYSIS
➢ Open circuit the capacitors since it blocks DCvoltage.
➢ Set VDD= +12v and measure ID, VGS,VGD.
Q-QOINT CONDITION
IDQ -------------------------------- mA
VDSQ -------------------V
FREQUENCY RESPONSE
➢ Determine the Q-point for the CS amplifier using DCanalysis.
➢ Determine Maximum signal handling (VMSH ) capacity of the CSamplifier.
CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION
Vin=
GAIN=20log(VO/Vin)
(dB)
RESULT
The Common Source amplifier was constructed and the following resultswere
observed.
2. Gain of the amplifier ------------------- dB
EXP NO: 6 DATE:
FREQUENCY RESPONSE OF DARLINGTON AMPLIFIER
AIM
To Design and Construct a BJT amplifier using Darlington pair and to determine,

APPARATUS REQUIRED
S.No Name Range Quantity
2 Resistor 47 kΩ, 10 kΩ, 1 kΩ Each 1
4.7 kΩ 2
3 Capacitor 4.7 µF 2
100 µF 1
5 DSO 50MHz 1
7 Bread Board - 1
8 Connecting Wires Single strand As

Required
THEORY
The Darlington transistor (often called a Darlington pair) is compound structure

consisting of two bipolar transistors connected in such a way that the First transistor
does current amplification of input signal and then it will be fed to the second
transistor which performs voltageamplification.
This configuration gives a much higher gain than each transistor taken separately
and, in the case of integrated devices, can take less space than two individual
transistors because they can use a shared collector. The Darlington amplifier typically
has a relatively high input resistance (1 - 10 KΩ) and a fairly high output resistance.
Therefore it is generally used to drive medium to high resistance loads. It is typically
used in applications where a small voltage signal needs to be amplified to a large
voltage signal like radioreceivers.

RL.
V MSH= volts
FREQUENCY RESPONSE
CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION
VIN =
GAIN= 20 log
S.NO FREQUENCY (HZ) VO (V) VO/Vin (V) (VO/Vin)
(dB)
RESULT
The Darlington amplifier was constructed and the following

resultswere observed.
1. Maximum signalhandlingcapacity ------------------ V
2. Gain of the amplifier ------------------- dB
3. Bandwidth oftheamplifier -------------------- Hz
EXP NO: 7 DATE:
FREQUENCY RESPONSE OF CASCODE AMPLIFIER

AIM
To Design and Construct a Cascode Amplifier and to determine its:
➢ DC Characteristics
➢ Gain of the amplifier

➢ Bandwidth of the amplifier
➢ Gain –Bandwidth Product
APPARATUS REQUIRED
S.No. Name Range Quantity

1. Transistor BC107 2
47K Ω, 8.2K Ω, 1K Ω, 2.2K Ω
Each 1
2. Resistor
4.7K Ω 2
1µF 2
3. Capacitor
100µF 1
Regulated power
3. (0-30)V 1
Supply
4. Signal Generator (0-3)MHz 1
5. DSO 30 MHz 1
As
6. Bread Board
Required
THEORY
A cascode amplifier consists of a common emitter amplifier stage in series with a common
base amplifier stage. It is one approach to solve the low impedance problem of a common
base circuit. Transistor Q1 and its associated components operate as a common emitter
amplifier, while the circuit of Q2 functions as a common base output stage. The cascode
amplifier gives the high input impedance of a common emitter amplifier, as well as the good
voltage gain and frequency performance of a common basecircuit.
The cascode configuration has one of two configurations of multistage amplifier. In each
case the collector of the leading transistor is connected to the emitter of the following
transistor. The arrangement of the two transistors is shown in the circuit diagram. The
cascode amplifier consists of CE stage connected in series with CB stage. The arrangement
provides a relatively high input impedance with low voltage gain for the first stage to ensure
the input miller capacitance is at a minimum, whereas the following CB stage provides an
excellent high frequency response.
PROCEDURE
DC ANALYSIS
➢ Set Vin = 0 by reducing the amplitude of the input signal from signal generator.
➢ Open circuit the capacitors since it blocks DC voltage.
➢ Set VCC= +12v and measure the voltage drop across the resistor 𝑉𝑅𝐶, voltage across
Collector- Emitter Junction 𝑉𝐶𝐸and voltage drop across base emitter junction.𝑉𝐵𝐸.
Q-P OINT CONDITION
= 𝑰𝑪 => =𝑉𝐶𝐶−𝑉𝐶𝐸
𝑰𝑪 (𝑸) 𝒎𝒂𝒙 𝑰 𝑪 𝒎𝒂𝒙 𝑹𝑪+𝑹𝑬
𝑉 𝟐
=𝑉𝐶𝐶
𝐶𝐸(𝑄) 𝟐

➢ It is the amplitude of input for which the output is not distorted. Designed circuit
can’t handle any input more than this amplitude (output start to clipp)
➢ For the safer side the half of the amplitude of MSH will be given as input to the circuit
generator to common emitter amplifier. Monitor the sinusoidal output using CRO
across RL.
which produces the output without any distortion is maximum signal handling capacity.
VMSH = volts
FREQUENCY RESPONSE
➢ Connect the circuit as per the circuit diagram

➢ Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 20Hzto
3MHz in incremental steps and note down the corresponding output voltage Vo
➢ Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency
on X-axis and gain in dB on Y-axis.
➢ Bandwidth, BW = f2-f1 where f1 and f2 is 3dB lower and upper cut-offfrequencies
CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION Input voltage constant VIN= V
Frequency Output Voltage Gain = 20 log (Vo / Vin)

S.No.
(in Hz) (in volts) in dB
RESULT
The Cascode amplifier was constructed and the following results were determined.
a) Gain of the amplifier:

b) Bandwidth of the amplifier:
c) Gain-Bandwidth product:
EXPT NO: 8 DATE:
FREQUENCY RESPONSE OF CASCADE AMPLIFIER
AIM
To Design and Construct a Cascade Amplifier and to determine its:
a. DC Characteristics
b. Gain of the amplifier
c. Bandwidth of the amplifier
d. Gain –Bandwidth Product
APPARATUS REQUIRED

1. Transistor BC107 2
2. Resistor 33 KΩ, 10 KΩ, 2.2 KΩ, Each 2
1 KΩ
100 µF 2
3. Capacitor
4.7 µF 3
4. Regulated power supply (0-30)V 1
5. Signal Generator (0-3)MHz 1
6. DSO 30 MHz 1
7. Bread Board - As Required
THEORY
A cascade amplifier has many of the same benefits as a cascode. A cascade is

basically a differential amplifier with one input grounded and the side with the real input has
no load. It can also be seen as a common collector (emitter follower) followed by a common
base.
By cascading a CE stage followed by an emitter-follower (CC) stage, a good voltage

amplifier results. The CE input resistance is high and CC output resistance is low. The CC
contributes no increase in voltage gain but provides a near voltage-source (low resistance)
output so that the gain is nearly independent of load resistance. The high input resistance of
the CE stage makes the input voltage nearly independent of input-source resistance. Multiple
CE stages can be cascaded and CC stages inserted between them to reduce attenuation
due to inter-stage loading.
PROCEDURE
DC ANALYSIS
➢ Set Vin = 0 by reducing the amplitude of the input signal from signal generator.
➢ Open circuit the capacitors since it blocks DC voltage.
Q-P OINT CONDITION
𝑰𝑪 (𝑸) 𝒎𝒂𝒙
𝑰 𝑪 𝒎𝒂𝒙
𝑹𝑪+𝑹𝑬
𝑉 𝟐
=𝑉𝐶𝐶
𝐶𝐸(𝑄) 𝟐
➢ It is the amplitude of input for which the output is not distorted. Designed circuit
can’t handle any input more than this amplitude (output start to clipp)
➢ For the safer side the half of the amplitude of MSH will be given as input to the circuit
generator to common emitter amplifier. Monitor the sinusoidal output using CRO
across RL.
which produces the output without any distortion is maximum signal handling capacity.
VMSH = volts
FREQUENCY RESPONSE
➢ Connect the circuit as per the circuit diagram

➢ Set the input voltage Vin=V MSH /2 and vary the input signal frequency from 20Hzto
3MHz in incremental steps and note down the corresponding output voltage Vo
➢ Find the Bandwidth and Gain-Bandwidth Product from Semi-log graph taking frequency
on X-axis and gain in dB on Y-axis.
➢ Bandwidth, BW = f2-f1 where f1 and f2 is 3dB lower and upper cut-off frequencies.
CIRCUIT DIAGRAM:
MODEL GRAPH:
TABULATION Input voltage Vin= V
FREQUENCY OUTPUT
VOLTAGE
S. NO [Hz] GAIN= 20 log (vo/vin) dB
[ VO] in Volts
RESULT
The Cascade amplifier was constructed and the following results were determined.
a)Gain of the amplifier :

b)Bandwidth of the amplifier :
c)Gain-Bandwidth product:
EXP NO: 9 DATE:
TRANSFER CHARACTERISTICS OF DIFFERENTIAL AMPLIFIER

AIM
To Design and Construct a Differential Amplifier using BJT and to determine its:
1. TransferCharacteristics
2. Gain of the amplifier in commonmode
3. Gain of the amplifier in differentialmode
4. CMRR (Common Mode RejectionRatio)
APPARATUS REQUIRED
1 Transistor [Active] BC 107 2
2 Resistor [Passive] 1KΩ 3
470 Ω 1
5 CRO 30MHz 1
7 Bread Board - 1

THEORY
A differential amplifier is a type of electronic amplifier that amplifies the difference

between two voltages but does not amplify the particular voltages. The need for differential
amplifier arises in many physical measurements where response from D.C to any MHZ is
required. It is also used in input stage of integrated amplifier.
PROCEDURE
DC ANALYSIS
➢ Open circuit the capacitors since it blocks DCvoltage.
Q-QOINT CONDITION
𝑰𝑪 (𝑸) 𝒎𝒂𝒙 𝑰 𝑪 𝒎𝒂𝒙
𝑹𝑪+𝑹𝑬
𝑉 𝟐
=𝑉𝐶𝐶
𝐶𝐸(𝑄) 𝟐
➢ It is the amplitude of input for which the output is not distorted. Designed circuitcan’t
generator to common emitter amplifier. Monitor the sinusoidal output using CROacross
RL.
VMSH = volts
TRANSFER CHARACTERISTICS AND CMRR
1. Connect the circuit as per the circuit diagram
2. Determine the Q-point of the Differential amplifier using DCanalysis.
3. Determine maximum input voltage that can be applied to amplifier using ACanalysis.
4. Determine the Transfer characteristics of Differential amplifier by plotting the graph for
normalized differential input voltage [(Vi1 – Vi2) / VT] vs. Normalized collectorcurrent
[ Ic/Io], Where 𝑉𝑇 = 11600; T =300K, Io=10µA.
𝑇
5. Calculate the voltage gain of differential amplifier for differentialmode

as Ad= 20log (V0/Vi) , Where Vi= Vi1–Vi2
6. Calculate the voltage gain of differential amplifier for Commonmode

as AC= 20log (V0/Vi) , Where Vi= (Vi1+ Vi2 /2)
7. Find the Common mode rejection ratio of differential amplifier using theformula
givenbelow.
CMRR= 20 log10 ( Ad/Ac)
Where Ad- Differential mode gain in dB, Ac – Common Mode gain in dB.
CIRCUIT DIAGRAM
COMMON MODE
DIFFERENTIAL MODE
DIFFERENTIAL AMPLIFIER – TRANSFER CHARACTERISTICS:
TABULATION :
Transfer Characteristics Calculation:
S.No. Input Voltage Output Current Ic2 in

Vi= (Vi1 – Vi2) in Volts Ampere
1.
2.
3.
4.
5.
6.
CMRR Calculation
To Find Differential Gain (Ad )
INPUT OUTPUT VOLTAGE Differential gain in dB

VOLTAGE [ VO] inVolts
S. NO. in volts Ad= 20log (V0/Vi)
Where Vi= Vi1– Vi2

V
1. i1
V
2. i2
To Find Common Mode Gain (Ac )
INPUT OUTPUT VOLTAGE Common mode gain in dB

S. NO. VOLTAGE [ VO]in Volts AC= 20log (V0/Vi)
in volts where Vi= (Vi1+ Vi2 / 2 )
V
1. i1
V
2. i2
RESULT
The Differential amplifier was constructed and the following results were determined.
a) Differential mode gain in dB :
b) Common Mode Gain in dB :
c) CMRR in dB :
EXP NO: 10 DATE:
FREQUENCY RESPONSE OF COMMON DRAIN FET AMPLIFIER
AIM
To Design and Construct a Common Drain amplifier and to determine its:
➢ Gain of the amplifier
➢ Bandwidth of the amplifier
➢ Output Resistance
APPARATUS REQUIRED
1 FET BFW1O 10
2 Resistor 2.2 MΩ, 4.7 KΩ, Each 2
3 Resistor 1KΩ 1
3 Capacitor 47 µF 1
0.001 µF 1
5 DSO 30MHz 10

THEORY
The common drain FET amplifier is similar to the common collector configuration of the
bipolar transistor. A general common drain JFET amplifier, self-biased, is shown in the
circuit diagram below.This configuration, which is sometimes known as a source follower, is
characterized by a voltage gain of less than unity, and features a large current gain as a result
of having very large input impedance and a small output impedance.
PROCEDURE: -
Frequency Response:
1. Connect the circuit as per the Fig.1. Apply VDD of 15 V
2. Give a signal Vs of 100 mV(P-P) at 1KHz on the I/P side and observe the
O/P on CRO.
3. Vary the frequency from 50 Hz to 1MHz with proper intervals on the
input side and observe the output Vo on CRO
4. Draw a graph between frequency Vs Gain on Semi-log Graph Sheet and
find its Mid frequency Gain Amid
5. Draw a horizontal line across the graph at 0.707 Amid and find the Bandwidth.
To Find R0:
1. Keep Vs = 100mV (P-P) 1KHz Signal and find Corresponding output Vo.
2. Now without disturbing Vs Connect potentiometer across output and
observe the output on CRO.
3. Adjust the value of Potentiometer Such that the output falls to the Vo/2 value.
Note the value of the potentiometer resistance is the Ro of the JFET CD Amplifier.
CIRCUIT DIAGRAM
MODEL GRAPH :
TABULATION
VIN =
GAIN=20log(VO/Vin)
(dB)
RESULT
The Common Source amplifier was constructed and the following results were
observed.
1. Gain of the amplifier ------------- dB
2. Bandwidth of the amplifier ------------- Hz
3. Output Resistance

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19ec401 - Ec1 - 2021 - 2022 Lab Manual PDF

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19EC401-ELECTRONICSCIRCUITS-I LAB

EXPT DATE EXPERIMENT NAME MARKS SIGN

1 Regulated DC Power supply

2 Frequency Response of Common Emitter Amplifier

3 Frequency Response of Common Base Amplifier

4 Frequency Response of Common Drain Amplifier

5 Frequency Response of Common Source FETAmplifier

6 Frequency Response of Darlington Amplifier

7 Frequency Response of Cascode Amplifier

8 Frequency Response of Cascade Amplifier

9 Transfer Characteristics of Differential Amplifier

10 Frequency Response of Common Drain FET Amplifier

S.NO NAME RANGE QUANTITY

4 Transformer 230V/12-0-12; 500mA 1

5 Decade Resistance Box - 1

9 Connecting Wires Single strand As required

OUTPUT WITH FILTER

MODEL GRAPH (LOAD REGUALTION)

FREQUENCY RESPONSE OF COMMON EMITTER AMPLIFIER

S.NO NAME RANGE QUANTITY

2 Resistor 33 KΩ, 2.2 KΩ, 10 KΩ, 1 KΩ Each 1

4 Function Generator 0-1 MHz 1

7 Connecting Wires Single strand As required

FREQUENCY RESPONSE OF COMMON BASE AMPLIFIER

S.NO NAME RANGE QUANTITY

10 KΩ, 33 KΩ, 4.7 KΩ,

4 Signal Generator (0-1)MHz 1

6 Regulated DC power supply (0-30)V 1

7 Connecting Wires Single strand As required

MAXIMUM SIGNAL HANDLING (MSH) CAPACITY

FREQUENCY RESPONSE OF COMMON COLLECTOR AMPLIFIER

S.NO NAME RANGE QUANTITY

2 Resistor 33 KΩ, 6 KΩ, 10 KΩ Each 1

4 Function Generator (0-1)MHz 1

6 Regulated power supply (0-30)V 1

7 Connecting Wires Single strand As required

MAXIMUM SIGNAL HANDLING (MSH) CAPACITY

MAXIMUM SIGNAL HANDLING (MSH) CAPACITY

FREQUENCY RESPONSE OF COMMON SOURCE FET AMPLIFIER

S.NO NAME RANGE QUANTITY

2 Resistor 1MΩ, 2.2 KΩ, 10 KΩ, Each 1

6 Regulated power supply (0-30)V 10

7 Connecting Wires Single strand As required

FREQUENCY RESPONSE OF DARLINGTON AMPLIFIER

➢ Maximum signal handling capacity

S.No Name Range Quantity

2 Resistor 47 kΩ, 10 kΩ, 1 kΩ Each 1

4 Signal Generator (0-1)MHz 1

6 Regulated power supply (0-30)V 1

8 Connecting Wires Single strand As

The Darlington transistor (often called a Darlington pair) is compound structure

MAXIMUM SIGNAL HANDLING (MSH) CAPACITY

The Darlington amplifier was constructed and the following

FREQUENCY RESPONSE OF CASCODE AMPLIFIER

To Design and Construct a Cascode Amplifier and to determine its:

➢ Gain of the amplifier

S.No. Name Range Quantity

Q-P OINT CONDITION

MAXIMUM SIGNAL HANDLING (MSH) CAPACITY

➢ Connect the circuit as per the circuit diagram

TABULATION Input voltage constant VIN= V

Frequency Output Voltage Gain = 20 log (Vo / Vin)

a) Gain of the amplifier: