Fault Modeling

EE5375 – ADD II
Prof. MacDonald
Stuck At Fault Models

l Modeling of physical defects (faults)

– simplify to logical fault
l stuck high or low
– represents many physical defects
– easy to simulate
– technology independent
l More advanced models
– stuck open – more representative of wire defects
– bridging defects
– delay defects – subtle deep sub-micron defects
Fault Detection
Expected Output
definition of detection
Z(t) ^ Zf(t) = 1
Test Vector T
Vector T detects fault f Z(t) = 0
Zf(t) = 1
0
0
0
Fault Detection - Total

This test vector detects all Expected Output

shown defects individually.
Test Vector T Z(t) = 0
Zf(t) = 1
0
0
0
Fault Detection
a

Z = (A + B) C’ + D C
Zf= (A + B) C’ + D 0 = (A + B) C’

1 = Z ^ Zf = ((A + B) C’ + DC) ^ ((A + B) C’)

1 = DC
T = { 0011, 0111, 1011, 1111} all detect f
Fault Sensitization

l Fault must be activated

– site of fault must opposite of stuck value
l Fault path must be sensitized
– all other inputs to gates along path must be non-
controlling values.
– thus the error is propagated to output and is
manifest
– referred to as error or fault-effect propagation
l If no test vector exists to activate and sensitize
the fault is undetectable.
Fault Sensitization
a 1 Fault Sensitization
1 Vectors {1010,1110,0110}
b 0 will sensitize this fault.

0->1 0->1
c 1

d 0
0->1
0

Fault Activation
any vector XX1X will activate the fault
Fault Detectability and Redundancy

l Defect is undetectable if it doesn’t change

circuit function
l Undetectable faults are due to redundancy
l Redundancy is often useful
– provides fault tolerance
– can be used to avoid glitching
– can be used to create pulses (self-timed circuits)
l Must be handled with care during test
Fault detection and self-timing

l Pulse Generator
– creates pulse at rising edge of input
– pulse width is equal to propagation delay of inverter
l Difficult to test with logical DC test
– Output is always zero in static sense
– Avoid in logic design
Fault detection and redundancy
circuit A

voting
circuit B

circuit C

l Fault Tolerant Circuits use redundancy

l Must remove redundancy during test
l otherwise possible for 2 circuits to be bad and still pass
– loss of fault tolerance
– reliability problem if bad circuits have shorts and power
 redundancy and hazards
A
BC 0 1
00 0 0 a

01 1 0
b
11 1 1 c

10 0 1

l Can add redundancy to avoid static hazards

l 011 to 111 should stay high but glitch low without redundancy
Fault Equivalence and Collapsing

l 2(N+1) total faults per N-input gate

l Some faults are equivalent and indistinguishable
– all inputs stuck at 0
– output stuck at 1
l Thus total faults reduce to N+2 for most logical gates
– logical gates with controlling value (XOR is less reducible)
l For Fault Analysis, only consider the reduced cases
 Fault Dominance
l If fault detection is important and not location
(diagnosis) then faults can be further collapsed
l Useful for reducing the number of faults that are
targeted –
– reduces time for test pattern generation
– reduces the number of patterns needed to be stored
l F dominates G if vectors that detect G also detect F

Tf

Tg
Dominance Collapsing

y z
uncollapsed faults list
x

y Equivalence fault collapsing

z
Easy to implement going from
x
output to inputs on complex
circuit

y z
x Dominance fault collapsing
Isn’t guaranteed to work with
redundant circuits, but provides
very good collapsing (see check
point theorem later)
Equivalence Collapsing

y z
functional equivalent and
x
indistinguishable even if all
test vectors are applied.

XY Z Zf1 Zf2
0 0 1 1 1
0 1 1 1 1
1 0 1 1 1
1 1 0 1 1 vector proves detectability in both cases,
but no vector distinguishes between them.
Dominance Collapsing

y z
One fault dominates the other
x
so they can be collapsed.
Doing this means that you can
detect them both but won’t be
able to tell them apart unlike
XY Z Zf1 Zf2 equivalence fault collapsing
0 0 1 1 0d where you can not distinguish the
0 1 1 1 0d faults even with all the vectors.
1 0 1 0d 0d
1 1 0 0 0
vector proves detectability of both but
alone can not distinguish them (diagnosis).
 Structural Equivalence

l To detect if faults are equivalent, simplify circuit and

compare in both cases.
– If the circuit is the same, you have structural equivalence
– faults can be functional equivalent but not structurally equivalent

a
b c
d
c
d
 Structural Equivalence

l To detect if faults are equivalent, simplify circuit and

compare in both cases.
– If the circuit is the same, you have structural equivalence
– faults can be functional equivalent but not structurally equivalent

a
b c
d
c
d
 Structural Equivalence
l With reconvergence, some faults are still functionally
equivalent but not structural equivalent

a
b
 Structural Equivalence
l With reconvergence, some faults are still functionally
equivalent but not structural equivalent

b
 Three approaches for collapsing
l Functional equivalence
– requires full simulation at global level
– prove equivalent by proving for all vectors output is the same
– requires full truth table analysis – for 32 inputs, need 4G rows
– only technique that guarantees minimum fault list
l Structural can be done at local level – easier
– for fanout of 1 – gate output are SE to destination input
– for gates with controlling value, s-a-c is equal to output s-a-c^I
– retain one fault as representative from each group
– doesn’t collapse completely but gets low hanging fruit
– works even if reconvergence exists
l Checkpointing - by exploiting fault dominance, only need to detect
– primary inputs of fan-out free circuits
– checkpoints of fanout circuits assuming no redundancy
Structural Equivalence
a

b
Structural Equivalence
a

b
Structural Equivalence
a

b
Structural Equivalence
a

b
Structural Equivalence
a

reduced to 10 faults s

b
Branches
stem faults are equivalent to multiple branch faults
however, we only consider single faults

Branches and stems not equivalent or dominant so they must be

handed separately.

1 1 1

1 1

0
1 1

Here is a case of stem fault detectable and either Alternative case in which one branch is detected
branch not detected by test vector 111 but stem and other branch are not detected.
Circuits fanout free
l With fault dominance, possible to detect all SSF
by only detecting all faults at PIs

d
Circuits fanout free - proof
l If all faults at input of gate are detected than
with fault equivalence and dominance the
outputs are detected as well.

functional equivalence eliminates sa0

Circuits fanout free - proof
l If all faults at input of gate are detected than
with fault equivalence and dominance the
outputs are detected as well.

functional dominance eliminates sa1 in this case

Without fanout, process can extend to primary output
Irredundant Circuit
l Detect all SSF, if all checkpoints are tested –
alternative to structural approach
a

reduced to 10 faults like

a
structural case before but
generally better (as long
as there is no redundancy)
b
can now use structural approach
to reduce further c
Example from Book (4.8) uncollapsed
40 faults total (42 if you count PO)
Circuit is not fanout free
but it is irrudundant.
a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) structural
40 faults total (42 if you count PO)
Book mentions 24 regular and 14 check point faults?

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) structural
40 faults total (42 if you count PO)

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) structural
40 faults total (42 if you count PO)

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) structural
40 faults total (42 if you count PO)
.

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) structural
40 faults total (42 if you count PO)
reduced to 14

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) – Checkpoint
14 faults total – 10 at PIs and 4 at branch checkpoints

a f
b

j m
g
c
h
i
d
e
k
Example from Book (4.8) minimum faults
10 faults total after reducing checkpoint faults with further analysis

functional
equivalent functional
dominance
a f
b functional
equivalent

j m
g
c
h functional
functional dominance
equivalent i
d
e
functional
k
equivalent
 Automatic Test Pattern Generation
l Automatic Test Pattern Generation (ATPG)
– determine list of faults required to be detected
– generate list of test vectors that detect all or percentage
l Many algorithms
– activate and then sensitize defects
– random generation and then determine what is detected
– hybrid, multi pass approach
l Limited to combinational logic
– scan testing reduces sequential circuits to combinational
– ATPG generates input vectors and expect vectors