Winter Semester 2022-2023

MVLD505L–ASIC
M. Tech VLSI Design
School of Electronics Engineering
Vellore Institute of Technology

Team Members:
ANISHA KUMARI 22MVD0037
GOPIKA C RAJENDRAN 22MVD0006
ARTHI S 22MVD0133
Submitted By:
Name: Arthi S
Reg. No: 22MVD0133
ASIC Implementation Of An Array Multiplier Based On Repetitive
Addition Architecture

Abstract:
In today’s digital world, the multipliers found a fundamental component in many applications
like signal processing. Multiplier and the adders plays a vital role in every digital circuits and
these are the basic arithmetic unit of DSP. It is also an essential unit for all types of wireless
communication. In this paper, an ASIC implementation of a repetitive addition based multiplier
is presented and mainly focused on its low power consumption. An array multiplier includes an
array of adders to perform the direct multiplication. Design of this multiplier is simulated using
Quartus II synthesis software tool by using Verilog code. The ASIC implementation is done
using Synopsys software tool and standard cell library 180nm technology gpdk (generic process
design kit).
Keywords: ASIC, Verilog, Synthesis, DSP, gpdk.

Introduction:
The design of a customized integrated circuit that is solely responsible for carrying out
multiplication operations is referred to as an ASIC (Application-Specific Integrated Circuit)
implementation of a multiplier. When quick and effective multiplication is needed, this style of
implementation is frequently employed in digital signal processing (DSP) applications and other
high-performance computing systems. Multipliers are one of the primary elements needed to
construct a variety of simple and complex digital circuits. The circuit is created in an ASIC
multiplier implementation to perform multiplication operations using a particular algorithm or
architecture optimized for a particular purpose. As a result, multiplication is executed in a highly
effective and quick manner in hardware as opposed to more slowly in software.
The array multiplier, Booth multiplier, Wallace tree multiplier, and other multipliers can all be
implemented using different architectures in an ASIC. The performance, size, and power
consumption of these architectures is different. Many applications, including digital signal
processing, image processing, and cryptography, require multipliers implemented on ASICs. It
offers a multiplication operation that is extremely quick and efficient, which can greatly enhance
the performance of these applications. However, creating an ASIC version of a multiplier can be
difficult and time-consuming as it calls for a high level of circuit design skill.
The purpose of this research is to develop a quick and low-power sequential multiplier based on
a fresh interpretation of the fundamental concept of multiplication.
Data Path:
It includes the functional units where all computations should be carried out. Typically it
includes registers, multiplexers, adder, counters and other functional blocks.

Controller Path:
It implements a finite state machine which provides a control signal to data path in proper
sequence.