Fault models are means of abstractly representing manufacturing defects in the

logical model of your design.

? True
False
Correct
The most common fault model used in fault simulation is …..

Transition fault model

IDDQ fault model
UDFM fault model
?Stuck-at fault model
Correct
Timing defects which are detected in slow transistors, are classified as:

Functional defects
?At-speed defects
IDDQ defects
Correct
By default, the ATPG tool generates multiple detection pattern sets, where every
fault is detected multiple times.

True
?False
Incorrect
To enable EMD “Embedded Multi-Detect” functionality, use the command:

set_multiple_detection -guaranteed_atpg_detections <n>

set_multiple_detection -desired_atpg_detections <n>
? both answers are correct
Correct
Using the ……..fault model, each pin in tested for slow-to-rise and slow-to-fall
behavior.

?Transition
Stuck-at
Path delay
Correct
Transition fault models, have the following characteristics: (Select all that
apply)

? Used to detect delay defects at gate terminals

?Type of At-speed fault model
Do not have localized fault sites
? Behave as stuck-at faults for temporary period of time
Incorrect
The path topology describes a user-specified path from beginning, or launch point,
through a combinational path to the end, or capture point.

//??True
False
Correct
The only way to create UDFM files is by using Tessent CellModelGen tool.

True
? False
Correct
What is the correct order of commands used to create UDFM patterns? (Drag the
commands to order them)

set_fault_type udfm
read_fault_sites <filename>.udfm
add_faults -all
create_patterns
Correct
Cell-Aware model creation is done once per technology.

? True
False
Correct
The first step in cell-aware model creation flow is:

The analysis of the Cell's SPICE netlist

? The Layout Extraction
SPICE fault simulation
Correct
Tessent has the ability to:

model cell internal and interconnect defects

create patterns for cell internal and interconnect defects
/? both
Correct
Automotive-grade fault models are only needed in automotive designs.

True
? False
Incorrect
Automotive-grade fault models address: (Select all that apply)

? Cell internal defects

?Inter-cell bridges
? Critical area based interconnect bridges and opens
Correct
For interconnect bridge defects, Tessent can create both, static and delay test
patterns.

?? True
False
Correct
The LDB or Layout Database, is created once per:

Technology
?? Design
Correct
Which command in the following list is used to create a UDFM file for potential
interconnect bridges?

create_layout
?? extract_fault sites -defect_types bridges
set_fault_type udfm -static_faults
extract_inter_cell_data
Correct
The LDB used for extracting possible bridge defect locations cannot be used to
extract possible open defects locations.

True
??False
Incorrect
The critical area for opens and vias is calculated by: (Select all that apply)

?? analyzing all segments of nets in a design

measuring the length of adjacency of cells
?? measuring the width of nets in the design
Incorrect
Cell neighborhood defects are chip-dependent bridge defects located on the
interface from one instance of a standard cell to another neighboring cell.

??True
False
Correct
In the Cell-Neighborhood extraction flow, CellModelGen is responsible for: (Select
all that apply)

?? merging different views of neighboring cells into one view

creating a list of cell neighboring pairs
?? creating chip dependent UDFM file
creating chip dependent UDFM test patterns
Incorrect
Delay test patterns cannot be created for cell neighboring defects.

? True
False
Incorrect
The Tessent Diagnosis tool can be used to/for: (Select all that apply)

?? Layout-aware diagnosis
Create UDFM test patterns
??Create layout database
Correct
Test patterns can be created to combine different UDFM fault models into a single
set of test patterns.

?? True
False
Correct
Two nets that are close to each other for a long distance have:

?? High probability for bridging

Low probability for bridging
High probability for opens
Low probability for opens
Correct
A wide short net, has a:

High probability for bridging

Low probability for bridging
High probability for opens
?? Low probability for opens
Incorrect
By default, the create_patterns command reports the cumulative TCA coverage values
for each batch of simulated patterns.

True
?? False
Incorrect
The IDDQ fault model can detect CMOS transistor stuck-on or stuck-open defects.

?? True
 False
Correct
Toggle fault patterns: (Select all that apply)

?? Provide control to fault locations

Observe stimulus effects on fault locations
?? Are fast to generate
Do not provide high test coverage
Incorrect
For a fault to be considered timing-critical, it typically has a long propagation
path.

?? True
False
Incorrect
Which of the following designs are more applicable for timing-aware tests?

Designs with balanced path delays

?? Designs with widely varying path delays
Incorrect
Slack calculation is described by the following formula:

(Ta-Tms)/Ta
(max_static_interval – dynamic_slack) / (max_static_interval – static_slack) *
100%
??clock period – path delay
Incorrect

Timing defects which are detected in slow transistors, are classified as:

IDDQ defects
Functional defects
At-speed defects
Incorrect
The most common fault model used in fault simulation is …..

Stuck-at fault model

UDFM fault model
IDDQ fault model
Transition fault model
Incorrect
Cell neighborhood defects are chip-dependent bridge defects located on the
interface from one instance of a standard cell to another neighboring cell.

True
False
Correct
Transition fault models, have the following characteristics: (Select all that
apply)

Behave as stuck-at faults for temporary period of time

Do not have localized fault sites
Used to detect delay defects at gate terminals
Type of At-speed fault model
Correct
The LDB used for extracting possible bridge defect locations cannot be used to
extract possible open defects locations.

False
True
Correct
Which command in the following list is used to create a UDFM file for potential
interconnect bridges?

create_layout
extract_inter_cell_data
extract_fault sites -defect_types bridges
set_fault_type udfm -static_faults
Correct
To enable EMD “Embedded Multi-Detect” functionality, use the command:

both answers are correct

set_multiple_detection -desired_atpg_detections <n>
set_multiple_detection -guaranteed_atpg_detections <n>
Correct
The path topology describes a user-specified path from beginning, or launch point,
through a combinational path to the end, or capture point.

True
False
Correct
In the Cell-Neighborhood extraction flow, CellModelGen is responsible for: (Select
all that apply)

creating chip dependent UDFM test patterns

creating chip dependent UDFM file
merging different views of neighboring cells into one view
creating a list of cell neighboring pairs
Incorrect
Delay test patterns cannot be created for cell neighboring defects.

True
False
Incorrect
The IDDQ fault model can detect CMOS transistor stuck-on or stuck-open defects.

False
True
Incorrect
Toggle fault patterns: (Select all that apply)
 Provide control to fault locations
Observe stimulus effects on fault locations
Are fast to generate
Do not provide high test coverage
Incorrect
Two nets that are close to each other for a long distance have:

High probability for bridging

Low probability for bridging
High probability for opens
Low probability for opens
Correct
The Tessent Diagnosis tool can be used to/for: (Select all that apply)

Create layout database

Create UDFM test patterns
Layout-aware diagnosis
Correct
By default, the ATPG tool generates multiple detection pattern sets, where every
fault is detected multiple times.

True
False
Correct
Cell-Aware model creation is done once per technology.

True
False
Correct
Fault models are means of abstractly representing manufacturing defects in the
logical model of your design.

False
True
Incorrect
Tessent has the ability to:

create patterns for cell internal and interconnect defects

model cell internal and interconnect defects
both
Correct
A wide short net, has a:

Low probability for opens

High probability for bridging
?? Low probability for bridging
High probability for opens
Incorrect
Slack calculation is described by the following formula:

(Ta-Tms)/Ta
(max_static_interval – dynamic_slack) / (max_static_interval – static_slack) *
100%
?? clock period - path delay
Correct