A Second-Order VCO-Based  ADC with Fully

Digital Feedback Summation

Chaoyang Xing*, Yi Zhong*, Jin Shao**, Pengpeng Chen***, Lu Jie*, Nan Sun*
Email: xingcy21@mails.tsinghua.edu.cn, zhongyi1104@163.com, shaojin@sgitg.sgcc.com.cn, chenpp@vangotech.com,
jielu1995@outlook.com, nansun@mail.tsinghua.edu.cn
**
Beijing Smartchip Microelectronics Technology Co., Ltd, Beijing, China
2022 IEEE International Symposium on Circuits and Systems (ISCAS) | 978-1-6654-8485-5/22/$31.00 ©2022 IEEE | DOI: 10.1109/ISCAS48785.2022.9937991

*Department of Electronic Engineering, Tsinghua University, Beijing, China

***
Hangzhou Vango Technologies, Inc, Hangzhou, China
Abstract—This paper presents a second-order VCO-based
ΔΣ ADC with a fully digital feedback adder, which is highly
digital, area efficient and low power. Both the first and second
loop integrator are implemented by VCOs and are free of OTA.
A novel digital adder is proposed to realize the secondary
feedback, significantly reducing the power and area of the
second stage. The proposed ADC is designed in a 28nm CMOS
technology under 0.9V supply, consuming only 1.14mW. The
simulated SNDR and SFDR are 72.5dB and 84.1dB respectively
over a 5MHz signal bandwidth.
Keywords—ADC, Delta-Sigma, VCO-based, Time-domain,
Scaling-friendly
I. INTRODUCTION
Continuous-time (CT) delta-sigma (∆Σ) analog-to-
digital converters (ADCs) are widely used for
communication, audio and sensor applications due to their
high-resolution and low-power advantages. Compared with
the discrete-time (DT) ADCs, CT ∆Σ ADCs possess inherent
anti-aliasing capability and are free of settling behavior.
However, operational transconductance amplifiers (OTAs) in
conventional CT ∆Σ ADCs are power-hungry and difficult to
down-scale with process. To exploit CT ΔΣ ADCs in
advanced process, some works proposed using voltage-
controlled oscillators (VCOs) to replace the OTA-based
integrators and voltage comparators [1]-[12]. A VCO
provides intrinsic integration from frequency to phase, and
the DC integration gain is always infinity even under low
supply voltage. Moreover, VCO can be highly digital and
scaling-friendly (e.g., ring VCO), making them very
attractive for advanced process.
However, compared to the conventional counterparts,
most of the reported VCO-based CT ΔΣ ADCs are limited in
noise-shaping order (typically only 1st order) [1]-[3]. This
limits the SNR of this type of ADC given a reasonable
oversampling ratio (OSR).
Designing high order VCO-based ΔΣ ADC is inherently
challenging, as integrating a signal in phase domain directly
is not easily achievable. To solve this issue, some works
integrate signals in the voltage domain first by using OTA-
based integrators [4], losing the main advantages of VCO.
Using passive integrators [5] can avoid the scaling difficulty,
but they cannot provide enough loop gain for strong noise-
shaping. It is also feasible to use multi-stage noise shaping
(MASH) structure which is purely VCO-based [6], [7], but its
performance is limited by the noise leakage under NTF
mismatches. Another straightforward method is to cascade
VCO integrators directly, by converting a VCO’s output
phase to voltage first and then applying it to another VCO [8].
However, there are multiple DACs in [8] to convert phase
from the first stage and the feedback respectively at the
second stage, which takes extra power and area. A digitalized
method using an up-down counter is proposed in some works
[9], [10], but it is complicated and is only suitable for XOR-
based phase detection. Moreover, their open-loop structure
limits the linearity.
This paper presents a closed-loop second-order VCO-
based CT ΔΣ ADC with a fully digital feedback adder. It is
constructed by two cascaded VCO integrators without any
voltage-domain loop filter. Since the VCO is inside a ∆Σ loop,
its nonlinearity is naturally suppressed. A compact digital
adder is proposed to realize the secondary feedback summer,
saving ~50% power and area of the second stage compared
to [8]. The whole ADC is fully digital except for the feedback
DAC, and it is thus scaling-friendly.

Fig. 1. Proposed VCO-based second-order ΔΣ ADC.

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 2
(1−𝑧 −1 )
𝑁𝑇𝐹(𝑧) = 
1+𝑎·𝑧 −1 +𝑏·𝑧 −2 +𝑐·𝑧 −3

(𝑎+2)·𝑧 −1 +(𝑏−1)·𝑧 −2 +𝑐·𝑧 −3

𝑆𝑇𝐹(𝑧) = (1+𝑎·𝑧 −1 
+𝑏·𝑧 −2 +𝑐·𝑧 −3 )·𝐼𝐷𝐴𝐶1
(a) (b)
Fig. 2. (a) Conventional feedback method. (b) proposed feedback Where 𝐾1 = 𝐾𝐶𝐶𝑂2 · 2𝑁 · 𝑡𝑠 · 𝐼𝐷𝐴𝐶2 , 𝐾2 = 𝐾1 · 𝐾𝐶𝐶𝑂1 · 2𝑁 ·
method. 𝑡𝑠 · 𝐼𝐷𝐴𝐶1 , 𝑎 = −2 + 𝐾1 + 𝐾2 · (0.5 − 𝑡𝑑 + 0.5𝑡𝑑 2 ) , 𝑏 =
1 − 𝐾1 + 𝐾2 · (0.5 + 𝑡𝑑 − 𝑡𝑑 2 ) , and 𝑐 = 𝐾2 · 0.5𝑡𝑑 2 . Here,
𝐾1 and 𝐾2 represent loop gain of the inner feedback loop and
the outer feedback loop, respectively.
From (1), the proposed ADC provides 2nd-order noise
shaping to the quantization error. Proper design parameters
are chosen to guarantee its stability under given ELD. Besides
the quantization error, thermal noise (ET 1 and ET2) is
modeled and added to the first stage and the second stage,
respectively. SNR is vulnerable to ET1 due to its same
Fig. 3. Linear signal model of the whole system. transfer function as STF. However, SNR is less sensitive to
ET2 because it is 1st-order shaped at the ADC output.
This paper is organized as follows: Sec. II presents the
proposed ADC architecture. Sec. Ⅲ discusses the key circuit III. CIRCUIT IMPLEMENTATIONS
implementations. Sec. Ⅳ shows the simulation results. And A. Digital adder for the secondary feedback
finally, Sec. Ⅴ draws the conclusion.
Fig.4 shows the structure of a single PFD. It can detect the
II. ARCHITECTURE leading or lagging information between the phases of two
input signals, representing it by output digital codes “UP” and
Fig. 1 shows the block diagram of the proposed “DN”. Moreover, a DPFD block is formed by several PFDs.
architecture. In this architecture, current-controlled oscillators At the second feedback point, the output of DPFD1 and
(CCOs) are used in place of VCOs to achieve better linearity DPFD2 need to be summed and converted to the driving
and to better cooperate with current-steering feedback DACs current for CCO2. As mentioned in Section Ⅱ, two IDACs
(IDACs). Two input resistors convert the input voltage into are used to implement this in the previous work [8]. However,
current, and the current is then subtracted by the feedback since the area and power consumption of digital cells are
IDAC. The residue current flows into the first CCO (CCO1) much lower than analog ones in advanced CMOS processes,
and gets integrated into its output phase. A double phase our proposed method sums the signal in the digital domain
frequency detector (DPFD) [3] behind CCO1 extracts the and only uses one IDAC, saving up to 50% area and power.
phase information and outputs a pulse-width-modulated Fig.5 shows the power comparison of the two methods in
(PWM) digital signal. Previously in [8], the output PWM simulation.
signal of the first stage is then converted back to current by an
IDAC, such that it can be connected to the second stage in the
same structure (Fig. 2a). In the proposed architecture, a digital
adder is used to directly sum the PWM signal from the 1st stage
and the digital feedback. After that, a group of bi-level IDACs
converts the digital summation and drives the second CCO
(CCO2) directly (Fig. 2b). In this way, there is no need for a
2nd analog feedback DAC. Since the DC output current of
IDAC1 is zero, an extra current source is applied to bias CCO1
properly. The biasing current for CCO2 is merged in IDAC2 Fig. 4. PFD structure and operation.
as a DC offset to save power. The output of the 2nd stage is
directly sampled and exported.
Fig. 3 illustrates the linear signal model of the proposed
ADC. The CCO is approximately modeled as a continuous
integrator with a gain of 2𝜋 · 𝐾𝑐𝑐𝑜 · 𝑇𝑠 , where 𝐾𝑐𝑐𝑜 is the
CCO tuning gain and 𝑇𝑠 is the sampling period. The up-
modulated tones in the CCO’s output are filtered out by the
secondary integrator [11], and thus are ignored in the linear
model. For an N-stage DPFD, the phase detection range is
[−2π, 2π] and the digital output range is [−2N, 2N], thus it
is modeled as a linear gain of 4N/4π at low frequency [3].
Finally, the IDAC is simply modeled as a linear gain block
and 𝑡𝑑 is the excessive loop delay (ELD) caused by the
retiming block (𝑡𝑑 = 0.25 in this design). As shown in Fig.3,
the whole system is in a 2nd-order cascade of integrators with
Fig. 5. Power consumption of two methods.
feedback (CIFB) ΔΣ structure. Using impulse invariance
method, the discrete-time noise transfer function (NTF) and
signal transfer function (STF) of the ADC can be derived as:

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 TABLE Ⅰ. TRUTH TABLE OF DIGITAL ADDER
UP2 DN2
UP1 DN1 00 01 11 10
00 0 +1 0 -1
01 +1 0 -1 -2
11 0 +1 0 -1
10 +1 +2 +1 0 Fig. 9. 15-stage CCO.

Fig. 6. Signal in 2nd-order CIFB ΔΣ ADC.

Fig. 10. Tri-level IDAC.

(a)

Fig. 7. SQNR comparison in behavioral simulation.

(b)
Fig. 11. (a) ISI error example. (b) ISI cancellation loop.

(a) (b)
Fig.8. (a) Digital adder cell. (b) Logic equation & feedback
truth table. (c) Driven bi-level IDAC.
Table Ⅰ shows the truth table between the input (output
codes of DPFD1 and DPFD2) and output of the adder. Since
the IDAC is bi-level, it is not able to output +2/-2 that the
adder may generate. Fortunately, in a 2nd-order CIFB ΔΣ
ADC, the input of the second-stage integrator is nearly 0
under steady-state, as shown in Fig.6. Thus, the occurrence
rate of ±2 from the adder is considerably low. We simply
saturate the adder’s output to ±1. An extra feedback error is
induced when the saturation occurs, but it is negligible
because of the low probability of occurrence, and also
because the error introduced into the second stage is 1st-
order shaped. Fig.7 shows the behavioral simulation result of
the same ADC with and without the saturation respectively.
SQNR degradation is less than 0.3dB. Fig.8 shows the final
implementation of the adder, whose power and area benefits
are obvious from its simplicity
B. Remaining blocks
Fig.9 shows the implementation of CCO. 15 differential
(c) current-starved delay cells are connected tail-to-head,
forming a ring oscillator. Each delay cell consists of two
simple pseudo-differential inverters, and is loaded with a
cross-coupled PMOS diode load for fast transitions and lower
phase noise [2]. The VDDs of all delay cells are connected
together as the CCO’s input port. When the input current
increases, the delay of each cell decreases, increasing its free-
running frequency. This 15-stage ring oscillator provides 30
different output phases in total, dividing the 2π phase evenly
into 30 fractions. 30 PFD cells form a DPFD block to detect
the phase of CCO, outputting a digital code with intrinsic
CLA (Clock-Level Averaging) capability that avoid using
explicit DEM [8].
The thermal noise of the first stage dominates the overall
SNR. It is contributed by both the input resistors, CCO1 and
IDAC1, where IDAC1 noise is dominating. To reduce the
noise from it, a tri-level IDAC is used, as shown in Fig.10. At
the “0” output state, the IDAC is shorted internally and
presents a high impedance output, contributing no noise into
the loop. Thus, the IDAC’s thermal noise is reduced by at
least 50% on average given a full-scale input [1], and by even
more in cases of small input-signal swing.

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 An ideal DAC’s output is with zero rising and falling The digital part consumes 372μW and the analog part
time, but a real DAC inevitably has output transitions. Worse consumes 769μW from a 0.9V supply. Fig.13 shows the
still, the rising and falling edges are not symmetrical, causing power consumption breakdown. Finally, TABLE Ⅱ compares
inter-symbol-interference (ISI) that leads to distortion our work with other published VCO-based ΔΣ ADCs in the
eventually, as shown in Fig.11(a). Digital off-chip calibration MHz-bandwidth.
is applied to cancel the ISI error by detecting the transitions
in output code and making compensation in the digital V. CONCLUSIONS
domain [5], as shown in Fig.11(b). This paper presents a second-order VCO-based CT ΔΣ
ADC with a fully digital secondary adder which saves up to
IV. SIMULATION RESULTS
50% area and power of the 2nd stage, and it can be easily
The proposed ADC is designed in a 28nm CMOS extended to a higher order. Wide phase detection range and
technology and is simulated using Spectre. Fig.12 shows an high quantizer resolution are achieved by using DPFD; DAC
8192-point FFT of the ADC output with an 1MHz input mismatch is reduced by CCO’s intrinsic CLA capability; ISI
signal at -3dBFS and a 250MHz sampling rate. The noise error is canceled by digital calibration; and, thermal noise is
floor is flat at low frequency due to thermal noise and a suppressed by using tri-level DAC. It does not require any
40dB/dec slope is clear at high frequency, proving a 2nd-order
OTA-based integrator as in conventional ΔΣ ADCs, resulting
noise shaping capability of the ADC. The simulated SNDR is
in good process-scaling compatibility. The potential of this
72.5dB over 5MHz bandwidth, and the SFDR is 84.1dB after
ISI calibration. structure can be expected in advanced CMOS technologies.
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