Experiment-3:

Simulations of Universal
Gates NAND, NOR, and a
mathematical function

Name: Meet Patel

Roll no: 2101EE44
Date: 30th Jan & 7th Feb, 2024
Objective:
1. Transistors sizing for optimal performance and effective rise and
fall resistances equal to a unit inverter for 2-input NAND/NOR gates
or any Boolean function.
2. Estimate the worst- and best-case rising and falling time and
compare the delay with Elmore delay model.
3. Estimate the power and operating frequency for different
configurations (process corners) and their dependence on supply
voltage and sizing of MOSFETs.
4. Optimize/trade-off of different design metrics for specific
applications.
Tool Required:
Cadence Tool
Procedure:
1) 1.Design 2-input NAND and NOR gates having effective rise and
fall resistances equal to a unit inverter. Vdd=1.8V, and load
capacitance CL=10ff.
2. Perform transient analysis and estimate the propagation delay for
both configurations for different input patterns.
3. Identify the worst and best input patterns for both configurations.
4. Calculate the maximum switching speed and average power
(dynamic and static) if both configurations are operating at 100MHz
and 500MHz.
2) 1.Alice asks Bob to Design a circuit that computes a function F(x)
so that she can authenticate the (x, F(x)) pairs as (username,
password). Assume that F(x)=x^2 for x=0,1,2, 3....9.
2. Simulate both designs, using the cell libraries developed in this lab
with nominal transistor sizing.
3. Re-design both the Bob’s design using static complementary
approach.
Circuit Diagram:

Figure 1

Figure 2
Figure 3
Schematics:

Figure 4: NAND Gate

Figure 5: NOR Gate

Figure 6: Bob Design 1

Figure 7: Bob Design 2

Figure 8: Bob Design 1 using static cmos

 Figure 9: Bob Design 2 using static cmos
Observations:

Figure 10: DC response of NAND gate

Figure 11: DC response of NAND gate

Figure 12:Transient response of NAND gate

Figure 13: DC response of NOR gate

Figure 14: DC response of NOR gate

Figure 15: Transient response of NOR gate

Figure 16: Transient response of Bob Design 1

Figure 17: Transient response of Bob Design 2

Figure 18: Transient response of Bob Design 1 using static cmos

Figure 19: Transient response of Bob Design 2 using static cmos

Observation Table:
DC Analysis of NAND Gate: (Vdd=1.8V)

NMOS PMOS VOH VOL VIH VIL NMH NML

Width Width High Output Low Output High Input Low Input Noise Noise Margin
Voltage Voltage Voltage Voltage Margin High Low

2u 2u 1.8v 0v 0.866v 0.62v 0.934v 0.62v

2u 4u 1.8v 0v 0.965v 0.699v 0.835v 0.699v
4u 2u 1.8v 0v 0.791v 0.574v 1.009v 0.574v

DC Analysis of NOR Gate: (Vdd=1.8V)

NMOS PMOS VOH VOL VIH VIL NMH NML

Width Width High Output Low Output High Input Low Input Noise Noise Margin
Voltage Voltage Voltage Voltage Margin High Low

1u 4u 1.8v 0v 0.988v 0.699v 0.72v 1.08v

1u 2u 1.8v 0v 0.945v 0.617v 0.855v 0.617v
1u 8u 1.8v 0v 1.092v 0.843v 0.708v 0.843v

Transient Analysis of NAND Gate:

NMOS Width PMOS Width Propagation delay Propagation Propagation
time from high to delay time Delay time
low from low to tp
high

2u 2u 0.02nS 0.00503nS 0.03515nS

2u 4u 0.06nS 0.06nS 0.06nS
4u 2u 0.029nS 0.087nS 0.058nS
Transient Analysis of NOR Gate:
NMOS Width PMOS Width Propagation Propagation Propagation
delay time delay time Delay time
from high to from low to tp
low high

1u 4u 0.06nS 0.05nS 0.055nS

1u 2u 0.045nS 0.0821nS 0.06355nS
1u 8u 0.067nS 0.042nS 0.0545nS

Conclusions:
1. We here implemented CMOS NAND gate and CMOS NOR gate
design in cadence software and performed its dc as well as transient
analysis for their various configurations.
Best input pattern for Nand gate is when both are low i.e. 0 and worst
is when both are high i.e. 1.
Best input pattern for Nor gate is when both are high i.e 1.and worst is
when both are low i.e 0.
2. Implemented bob design1 and design 2 using gates as well as static
cmos technique.
We should choose design 1 over design 2,because in design 1
Z2=X2X3 while in design 2 Z2=(X1+X2)*X3.There is an extra term
of X1*X3 in design 2 because of which it will also give correct
output for x more than 9 which could also be verified from the graph
obtained during transient analysis of its designs. Thus, it would
breach the security system because as per the statement, it should
have worked only for 0 to 9 and not more than that. Thus, we should
choose design 1 over design 2.