Laboratory Manual SUIIT VLSI Lab.

EXPERIMENT NO: 02
Aim of the Experiment: VHDL IMPLEMENTATION OF LOGIC GATES USING
UNIVERSAL GATES (NOR, NAND).

Requirements: 1.Computer
2. Xilinx ISE – VLSI Design Software

Department of Electronics and Communication Engineering

11
Laboratory Manual SUIIT VLSI Lab.

Design Entry: Same as experiment no.1

Test Bench Creation: Same as experiment no.1
Functional Verification: Same as experiment no.1
Procedure: Same as experiment no.1
Test Bench Creation: Same as experiment no.1
Simulation: Same as experiment no.1

Department of Electronics and Communication Engineering

12
Laboratory Manual SUIIT VLSI Lab.

VHDL code for logic gate using NAND gate:

Write by your own

RTL schematic:

Attach RTL schematic figure

Simulation result:

Attach simulation figure

VHDL code for logic gate using NOR gate

Write by your own

RTL schematic:

Attach RTL schematic figure

Simulation result:

Attach simulation figure

Conclusion

Department of Electronics and Communication Engineering

13