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Edited by
An Chen
IBM Research – Almaden, CA, USA
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Contents
Preface xi
List of Contributors xv
5.7 Conclusion 91
Acknowledgments 91
References 91
6 Organic Electronics 93
Hagen Klauk
6.1 Introduction 93
6.2 Organic Light-Emitting Diodes 94
6.3 Organic Solar Cells 96
6.4 Organic Thin-Film Transistors 97
6.5 Outlook 101
References 102
Index 343
xi
Preface
Since the invention of the solid-state transistors, the semiconductor technologies have advanced
at an exponential pace and become the foundation for numerous industries, e.g. computing,
communication, consumer electronics, autonomous systems, and defense. Guided by Moore’s
law, the scaling of transistors has provided new generations of chips every one to two years, with
ever-increasing density and better performance. Today, silicon transistors are approaching some
fundamental limits of dimensional scaling. The semiconductor industry has also transformed
through several phases and foundational technologies. The emergence of Internet of Things (IoT),
big data, artificial intelligence (AI), and quantum computing has created new opportunities for
advanced semiconductor technologies. The complementary metal-oxide-semiconductor (CMOS)
technology dominates the semiconductor industry today, but there are numerous technologies and
active research beyond conventional CMOS. Although semiconductors are often associated with
high-performance computing chips such as central processing unit (CPU) and graphics processing
unit (GPU), there is a wide range of applications beyond computing for semiconductor products,
e.g. sensors, displays, and power electronics. Silicon (Si) is the most important semiconductor, but
the semiconductor research also covers a variety of materials, e.g. germanium (Ge), III–V com-
pounds, organic materials, carbon nanotube, 2D materials, magnetic materials, and topological
materials.
This book is a collection of articles reviewing advanced semiconductor technologies beyond con-
ventional Si CMOS for various applications. These articles written by the experts in the fields can
be read independent of each other. The variety of topics reflects the breadth of the semiconductor
R&D and applications today, but these articles only cover a very small fraction of semiconductor
technologies.
With the transistor scaling approaching the fundamental limits, heterogeneous integration is a
promising direction to sustain the improvement of performance and functionalities without relying
on reducing transistor sizes. Chapter 1, “Heterogeneous Integration at Scale,” provides a compre-
hensive review of technologies, design/architecture considerations, reliability issues, applications,
and future directions of large-scale heterogeneous integration.
While technology innovation has been a primary driver for the semiconductor industry, the
future of semiconductor systems will increasingly resort to novel computing paradigms. Chapter 2,
“Hyperdimensional Computing: An Algebra for Computing with Vectors,” presents an example of
entirely new ways of computing inspired by the information processing in the brain. Instead of
traditional model of computing with numbers, hyperdimensional (HD) computing encodes infor-
mation in a holographic representation with wide vectors and unique operations. HD computing
is extremely robust against noise, matches well with 3D circuits, and is uniquely suitable to process
a variety of sensory signals without interference with each other.
xii Preface
The majority of semiconductor chips are digital circuits; however, analog and mixed-signal
circuits are crucially important. The physical world is analog; therefore, analog circuits are always
needed to connect digital chips with real world, e.g. sensory data, power management, and
communication. Although digital circuit design is highly automated, analog circuit design still
relies on manual effort. Chapter 3, “CAD for Analog/Mixed-Signal Integrated Circuits,” reviews
the progress toward automated computer-aided design (CAD) of analog and mixed-signal circuits.
Modern computers are built based on the von Neumann architecture with separate logic/
computing units and memory/storage units. Emerging memory devices not only provide new
technologies to improve memory systems but also enable novel computing architectures, e.g.
in-memory computing. One of the most promising emerging memories is based on magnetic
materials and properties. Chapters 4 and 5 focus on a so-called magnetoelectric field effect
transistor (MEFET) based on the programming of the polarization in a 2D semiconductor channel
with large spin-orbit coupling, via the proximity effect of a magnetoelectric gate. Chapter 4,
“Magnetoelectric Transistor Devices and Circuits with Steering Logic,” presents various logic gate
designs based on a one-source two-drain MEFET configured with a steering function. Chapter 5,
“Nonvolatile Memory Based Architectures Using Magnetoelectric FETs,” describes MEFET
memory designs with the performance and size suitable to fulfill the application space between
static random-access-memory (SRAM) and dynamic random-access-memory (DRAM).
Novel materials beyond Si, Ge, and III–V compounds may enable new semiconductor products
and applications. Among them, organic semiconductors are promising materials for low-cost, flex-
ible, and bio-compatible electronics. Chapter 6, “Organic Electronics,” discusses the opportunities
of organic semiconductors for large-area flexible electronics, including organic light-emitting diode
(OLED), organic displays, organic solar cells, and thin-film transistors. Chapter 7, “Active-Matrix
Electroluminescent Displays,” delves into the details of flat panel electroluminescent displays
based on light-emitting diodes (LEDs) that have been utilized in a wide range of applications
including smart phones, tablets, laptops, and TVs. Various underlying LED technologies, associ-
ated circuits, and design considerations are reviewed. Another interesting application of organic
materials is memory. Chapter 8, “Organic and Macromolecular Memory – Nanocomposite Bistable
Memory Devices,” discusses the mechanisms, characteristics, and current status of organic mem-
ories. One of the advantages of organic materials is their low-cost processing and the potential
to stack up multiple layers. Chapter 9, “Next Generation of High-Performance Printed Flexible
Electronics,” summarizes different printing technologies for flexible electronics, showcases
the state-of-the-art printed flexible electronic circuits, and discusses the challenges and future
directions of large-scale cost-effective printed electronics. The vision of integrating electronic
components onto polymer foils leads to the flexible electronics version of systems-on-chip (SoC),
known as systems-in-foil (SiF). A wide range of applications can benefit from SiF, e.g. smart labels,
intelligent electronic skin, and implanted devices. Chapter 10 “Hybrid Systems-in-Foil” reviews
the opportunities of SiF and challenges in materials, integration, and testing.
The electronic systems need an interface with the physical world. Semiconductor chips rely on
sensors to “see,” “hear,” and “smell.” Optical sensing is utilized in a wide range of applications, e.g.
camera, fiber optics and communication, light source and laser, data storage, medical monitoring
and diagnostics, and manufacturing. Chapter 11, “Optical Detectors,” reviews the photodiodes
based on Si, III–V, and emerging materials as the essential components for highly sensitive
detectors for a broad spectrum of wavelengths. Chapter 12, “Environmental Sensing,” covers com-
prehensively different air pollution sources, air quality metrics, and various sensing approaches
for particulate matters and volatile organic compounds. The advancement of semiconductor
Preface xiii
technologies contributes to the miniaturization of the sensing equipment and the improvement of
their performance.
Unlike computer chips operating with very low voltage and current, power electronics handle
very high voltage (e.g. thousands of volt or higher) and current required to operate machinery,
vehicles, appliances, etc. Special device designs and unique material properties are required to
sustain such high voltage and current in semiconductor chips. Chapter 13, “Insulated Gate Bipolar
Transistors (IGBTs),” reviews an important high-power device known as Si insulated gate bipolar
transistors (IGBTs). IGBT not only dominates power electronics today but also continues to be
innovated for further gains in power density and efficiency. At the same time, significant progress
has been made on wide bandgap semiconductors. Chapter 14, “III–V and Wide Bandgap,” reviews
promising materials (e.g. diamond, GaN) and their applications in high-frequency power conver-
sion and high-temperature electronics. While wide bandgap power modules may be combined with
Si-based control circuits in near-term solutions, considerable effort is made to advance integrated
circuits based on wide bandgap semiconductors. Chapter 15, “SiC MOSFETs,” reviews SiC-based
power semiconductor devices including diodes and transistors. SiC is well positioned to fulfill the
requirements of power electronics, e.g. energy efficiency, scaling, system integration, and reliability.
The unique ability of SiC to form a native SiO2 as the gate dielectric makes it particularly attractive
for power metal-oxide-semiconductor field-effect-transistors (MOSFETs). At the end, Chapter 16,
“Multiphase VRM and Power Stage Evolution,” provides a detailed overview of the evolution of
CPU power delivery technologies and explains the reasons driving the technology shifts.
This book could be considered as a small-scale reference of advanced semiconductor
technologies, which may potentially be expanded into a large-scale reference with more
comprehensive coverage. It is our wish that this collection of chapters will provide useful tutorials
on selected topics of advanced semiconductor technologies.
An Chen
IBM Research – Almaden, CA, USA
September 2022
xv
List of Contributors
Tarek Zaki
Munich, Germany
1
1.1 Introduction
Microelectronics has made tremendous progress over the last several decades adhering to what is
popularly called Moore’s Law. One measure of Moore’s law is the scaling factor of minimum fea-
tures on a silicon integrated circuit (IC). This trend is shown in the dark gray (left-hand y-axis) curve
in Figure 1.1 [1] exhibiting over a 1,000-fold decrease in minimum feature size, corresponding to a
million-fold transistor density improvement. This improvement corresponds to reduction in power
per function as well as reduction of cost and price per function. Nonetheless, until recently, pack-
aging did not scale as seen in the light gray (right-hand y-axis) curve in Figure 1.1. For example,
in 1967, when flip-chip bonding was first introduced, the bump pitch was 400 μm. Even today, the
pitch of the bump (die to laminate) has scaled to about 130 μm, while ball grid array (BGA) pitch
and trace pitch on laminates and printed circuit boards (PCBs) have not fared better. However, in
the last few years, we have seen an acceleration of these metrics as shown in the inset in Figure 1.1.
Note that the silicon (Si) scale is in nanometers, while the packaging scale is in micrometers. There
are two key factors that have mediated this acceleration: (i) the adoption of silicon-like process-
ing materials and methods to achieve scaling, including silicon interposers, and, importantly, (ii)
fan-out wafer-level packaging (FOWLP).
This trend has manifested itself in two ways: (i) The extensive use of interposers, which is an
additional level in the packaging hierarchy as shown in Figure 1.2. At a basic level, interposers pro-
vide a first-level platform for the integration of several (eight) heterogeneous dielets on a thinned
silicon substrate that is then further packaged on a laminate and attached to a PCB. This allows
the dielets on the interposer to communicate intimately within the interposer, though communi-
cation outside the interposer is more conventional. (ii) Three-dimensional (3D) integration, where
dies are stacked one on top of the other, typically face to back with through silicon vias (TSVs)
or alternatively face to face through surface connections. These face-to-face connections can be at
high bandwidth and low latency. Both of these techniques have transformed packaging, especially
when it comes to the memory subsystem. A roadmap using the memory subsystem as a paradigm
for advanced packaging is depicted in Figure 1.3. Another area in which interposers and 3D inte-
gration can play a big role is the integration of analog and mixed signal functions. Moore’s law
scaling does a good job in scaling digital logic, but is at best marginal when it comes to analog and
mixed signal functions. This is shown in Figure 1.4, where the analog/mixed signal components
can occupy an increasing percentage of real estate at finer geometries. In these cases, retaining the
Advances in Semiconductor Technologies: Selected Topics Beyond Conventional CMOS, First Edition. Edited by An Chen.
© 2023 The Institute of Electrical and Electronics Engineers, Inc. Published 2023 by John Wiley & Sons, Inc.
2 1 Heterogeneous Integration at Scale
25 160
(nm) (μm)
Advanced 1400
10,000 20
2
350 packaging 120
15 100
300
μ
60
Si scaling (nm)
250
40
5
200 20
100 Chiplet/dielet revolution
0 0
2011 201
2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
20
202
150
Pack
10 100
5500
1 0
1960 1970 1980 1990 2000 2010 0
2020 2030
Year
Figure 1.1 Scaling trends for CMOS features as well as package features. Package scaling has lagged
significantly as compared to Si scaling. Adoption of silicon-like technology for packaging has somewhat
accelerated scaling.
μ-bumps
MCM Die Die
Interposer
C4 bumps
TSV
Laminate Laminate
BGA
analog/mixed signal functions in an older node makes sense as long as one can provide compatible
voltage domains and ensure low latency as well as low analog signal distortion. These are not very
difficult to do on interposers.
Why is it important to scale packaging? Packaging dimensions determine the size of the sys-
tem especially since the scale is 10–100 times larger than chip dimensions. Power too is a major
consideration. Communication power between chips accounts for 30–40% of total system power.
So for size, weight, and power (SWaP), as well as cost, scaling the package has advantages. The
key parameters that affect SWaP are dominated by packaging metrics, and scaling the package has
greater impact on SWaP than additional Si scaling. For flexible hybrid electronics (FHE), form fac-
tor and power play a critical role. Most FHE devices are mobile and dependent on battery power.
As such, FHE packages will benefit immensely from scaling.
1.1 Introduction 3
Integration
“Prehistoric” Future
Stacked die
Stacked memory
Now Wafer stacking
Time
100 100%
90 90%
80 80%
70 70%
60 60%
Die area (%)
Analog (%)
50 50%
40 40%
30 30%
20 20%
10 10%
0 0%
0 50 100 150 200
Node (nm)
Figure 1.4 Percent of area dedicated to analog circuits is increasing with scaling (squares). Thus, practical
die area (normalized to 180 nm technology) is increasing with scaling (rhombuses) as compared to ideal die
area (triangles).
4 1 Heterogeneous Integration at Scale
Another aspect of advanced packaging that has the focus of attention in recent years is hetero-
geneous integration. This term requires some clarification. Most packaging constructs do in fact
achieve heterogeneous integration via the integration of diverse packaged chips on an extended
substrate such as a PCB. Heterogeneous integration, therefore, in general and in itself, is not new.
However, in the context of advanced packaging, heterogeneous integration refers to the integration
of bare dies on a first-level packaging substrate. This could be an organic, ceramic, or silicon inter-
poser. The key features that distinguish heterogeneous integration from classical or conventional
packaging are the pitch of the connections between the bare die and the substrate, the number
of connections between the interconnected bare dies, the size of the dies, and hence a significant
simplification in the communication protocols of interdie signaling. It is generally accepted that
for bump pitches <50 μm, interdie spacing of <2 mm, and trace pitches (wiring between the dies)
of <5 μm, the integration is considered in the regime of advanced packaging.
Finally, “chiplets” and “dielets” are another feature of advanced packaging. A complex system or
large chip design is fragmented into smaller entities called chiplets and then instantiated in Si as
dielets. These dielets are then intimately reintegrated at fine pitch (bump and trace) as well as short
interdie spacing, as previously described, to synthesize a subsystem or a module. This construct can
be further assembled on a PCB or, in the case of wafer scale systems, and can represent the entire
system [2, 3].
Figure 1.5 (a) A 50 mm diameter Cu pillar capped with solder. (b) After mass reflow with compression
showing the solder extrusions. (c) Micrograph showing extrusions that cause adjacent pillars to become
electrically shorted. Source: Photo courtesy: Eric Perfecto.
solder is shown in Figure 1.5a, a cross section after mass reflow is shown in Figure 1.5b, and a
micrograph of two shorted pillars is shown in Figure 1.5c. Shorting of neighboring solder balls is
the main challenge to the continuous scaling of solder-based interconnects below about 50 μm.
Another possible integration approach is to attach dielets directly to a substrate without solder
(or other intermetallics), using direct metal-to-metal thermal compression bonding (TCB). In this
integration approach, two metals are bonded together by applying pressure and temperature for
a certain amount of time. After this process, a very strong low-contact resistance bond is formed.
To ensure high-quality connections using TCB, the surfaces of the metals must be pristine and
atomically smooth. Additional conditions must be met when bonding Cu for example, such as
surface preparation to avoid oxidation of the Cu prior to bonding (by using plasma or formic acid).
Alignment is another challenge in small pitch connections for heterogeneous integration.
Solder-based interconnects are easier to align due to the larger dimensions and since they exhibit
a form of self-alignment property due to surface tension at solder melting temperature. Unlike
solder, direct metal-to-metal integration requires a high level of alignment accuracy which is
difficult to achieve by optical means since the die and substrate are typically not transparent. A
second-order optical alignment is therefore required, where the die and the substrate are aligned to
a virtual reference. For example, in the silicon interconnect fabric (Si-IF) technology, an alignment
accuracy of ±1 μm has been achieved [4]. Although this alignment accuracy is good, it is still about
an order of magnitude worse than die-level conventional optical lithography.
Table 1.1 Key structural and thermal properties of Si and other relevant materials.
Organic 0.1–20 2,000–3,000 14–70 0.3–1 High Low Large horizontal and
(FR4) vertical interconnect pitch
Glass 50–90 33–3,500 4–9 1–2 Low High Low electrical losses.
Metallization is difficult
Silicon 130–185 5,000–9,000 3–5 148 Low Low High electrical losses
Steel 190–200 400–500 11–13 16–25
Copper 128 200–350 17 400
The Si-IF [2] is a silicon wafer-scale platform that supports integration of small dies at fine vertical
pitch (2–10 μm). Si is a highly mature substrate that benefits from decades of technology opti-
mization. Furthermore, passive Si with micrometer size interconnects is a relatively inexpensive
construct.
Figure 1.6 Parametric space to determine optimal die size for heterogeneous integration. The key plotted
parameters are: intellectual property (IP) reuse, die handling, yield, I/O complexity/power, and testing
complexity. Those parameters are plotted as a function of the die size. An optimal parametric space in the
center of the figure drives the optimal die size to be 1–100 mm2 .
Since integration at fine pitch and small inter-component spacing is enabled at the package level
by various heterogeneous integration platforms, the components (or dies) need not be very large.
Several parameters are key to determine the optimal die size for integration, as shown in Figure 1.6.
The optimal die size is represented by the light gray block in the center of Figure 1.6, driven by the
optimal parametric space. Following is a discussion of the parameters that determine the die size
for heterogeneous integration.
● IP reuse: Enables reduced nonrecurring engineering (NRE) cost and faster time to market. Abil-
ity to reuse IP significantly increases with smaller die size. The smaller the die, the simpler and
potentially more fundamental the function, the higher probability to reuse the die. For example,
at the leftmost side of the bar in Figure 1.6, a simple logic block (e.g. multiplexer), has a high
probability to be reused many times in a other projects or systems. Alternatively, a very large
system (e.g. an entire SoC), will not likely to be reused in other projects or systems. Therefore,
according to the IP reuse parameter, the smaller the die, the better.
● Handling: This parameter prefers large dies since handling very small dielets (smaller than
1 mm2 ) is difficult. Special tools, alignment techniques, and handling procedures are required
to handle such small dies. On the other hand, handling large dies is easy and established tooling
can be used.
● Yield: A key parameter and potentially the main driver of any fabrication facility. Statistically,
large dies are prone to high probability of defects leading to low yield and therefore high cost.
Alternatively, small dies typically exhibit a very high yield in an established process, driving down
the cost of the dies and the entire system. Small dies are therefore preferred to optimize the yield
parameter.
● I/O complexity/power: Rent’s rule drives this parameter, i.e. the number of I/Os is related to
the complexity of the component (further described in Section 1.2.5). Small components (or
dies) require fewer I/Os and therefore less I/O-related power. Integration of small dies sup-
ports local highly parallel communication, as compared to large dies that required high-speed
8 1 Heterogeneous Integration at Scale
integration pad pitches and materials. Heterogeneous integration platforms must support integra-
tion of these disparate technologies within the same platform. For example, the Si-IF technology
supports integration of dies of different height, area, pad pitches, and attachment material, i.e.
solder-based and direct metal). This feature supports utilization of hardened legacy IP and elimi-
nates the need to redesign circuits in newer technologies unnecessarily, significantly reducing NRE.
{61}
"When the Liberal party for the first time for eighteen years
found itself in power at Ottawa, Mr. Laurier at once opened
negotiations with Manitoba. The result was a settlement which,
although it might work well in particular districts, could not be
accepted as satisfactory by the Catholic authorities. It arranged
that where in towns and cities the average attendance of
Catholic children was forty or upwards, and in villages and
rural districts the average attendance of such children was
twenty-five or upwards, one Catholic teacher should be
employed. There were various other provisions, but that was
the central concession. … Leo the Thirteenth, recognising the
difficulties which beset Mr. Laurier's path, mindful, perhaps,
also that it is not always easy immediately to resume friendly
conference with those who have just done their best to defeat
you, has sent to Canada an Apostolic Commissioner."
J. G. Snead Cox,
Mr. Laurier and Manitoba
(Nineteenth Century, April, 1897).
CANADA: A. D. 1895.
Northern territories formed into provisional districts.
CANADA: A. D. 1895.
Negotiations with Newfoundland.
CANADA: A. D. 1896-1897.
Policy of the Liberal Government.
Revision of the tariff, with discriminating duties
in favor of Great Britain, and provisions for reciprocity.
"When the Minister of Finance laid the tariff before the House
of Commons, he declared that the 'National Policy,' as it had
been tried for eighteen years, was a failure; and … claimed
that lowering the tariff wall against England was a step in
the direction of a tariff 'based not upon the protective
system but upon the requirements of the public service.'
During the first fifteen months of the new tariff, the
concession to England consists of a reduction by one-eighth of
the duties chargeable under the general list. At the end of
that time, that is on the last of July, 1898, the reduction
will be one-fourth. The reductions do not apply to wines, malt
liquors, spirits and tobacco, the taxes on which are
essentially for revenue. While England was admitted at once to
the advantages of the reduced tariff, this tariff is not to be
applicable to England alone. In July, it was extended to the
products of New South Wales, the free-trade colony of the
British Australasian group; and any country can come within
its provisions whose government can satisfy the Comptroller of
Customs at Ottawa, that it is offering favourable treatment to
Canadian exports, and is affording them as easy an entrance
through its customs houses as the Canadians give by means of
the reciprocal tariff. It is also possible, under a later
amendment to the Tariff Act, for the Governor in Council to
extend the benefits of the reciprocal tariff to any country
entitled thereto by virtue of a treaty with Great Britain.
{62}
Numerous alterations were made in the general list of import
duties. Some of these involved higher rates; others lowered
the duties. But if the changes in the fiscal system had been
confined to these variations, the new tariff would not have
been noteworthy, and it would have fulfilled few of the
pledges made by the Liberals when they were in Opposition. It
owes its chief importance to the establishment of an inner
tariff in the interests of countries which deal favourably
with Canada."
E. Porritt,
The New Administration in Canada
(Yale Review, August, 1897).
CANADA: A. D. 1898-1899.
The Joint High Commission for settlement of all unsettled
questions between Canada and the United States.
CANADA: A. D. 1899-1900.
Troops to reinforce the British army in South Africa.
Nova Scotia. 15 5
0 20
New-Brunswick. 9 5
0 14
Prince Edward Island. 3 2
0 5
Quebec. 57 8
0 65
Ontario. 33 54
5 92
Manitoba. 2 3
2 7
Northwest Territories. 2 0
2 4
British Columbia. 3 2
1 6
Totals. 124 79
10 213