Princess Sumaya Univ.

Computer Engineering Dept.

Chapter 1:
Combinational Logic Review
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Combinational Circuits

 Output is function of input only

i.e. no feedback

Combinational
n inputs • • m outputs
• Circuits •
• •


When input changes, output may change (after a delay)

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Adder

 Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Adder

 Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Adder

 Full Adder S = xy'z'+x'yz'+x'y'z+xyz = x  y  z

x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Adder
x3x2x1x0 y3y2y1y0
c3 c2 c 1 .
+ x3 x2 x1 x0
Carry + y3 y2 y1 y0
Cy Binary Adder C0 Propagate ────────
Addition Cy S3 S2 S1 S0
S3S2S1S0

x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Subtractor

 Use 2’s complement with binary adder

● x – y = x + (-y) = x + y’ + 1

x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Binary Adder/Subtractor

 M: Control Signal (Mode)

● M=0  F = x + y x3 x2 x1 x0 y3 y2 y1 y0 M
● M=1  F = x – y

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Decoders

 Extract “Information” from the code Only one

lamp will
 Binary Decoder turn on
● Example: 2-bit Binary Number

0 1
x1 0
Binary
x0 0 Decoder 0
0

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Decoders

 2-to-4 Line Decoder

Y3

y3 Y2

Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0

I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3  I1 I 0 Y2  I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1  I1 I 0 Y0  I1 I 0
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Decoders

 3-to-8 Line Decoder Y7  I 2 I1 I 0

Y6  I 2 I1 I 0
Y7 Y5  I 2 I1 I 0
Y6
Y5 Y4  I 2 I1 I 0
Decoder
Binary

I2 Y4 Y3  I 2 I1 I 0
I1 Y3
I0 Y2 Y2  I 2 I1 I 0
Y1 Y1  I 2 I1 I 0
Y0
Y0  I 2 I1 I 0

I2
I1
I0
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Decoders

 “Enable” Control Y3

Y3

Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Decoders

 Expansion I2 I 1 I0

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7

Decoder
I0

Binary
0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1 Y1 Y5
0 1 1 0 0 0 0 1 0 0 0 E
1 0 0 0 0 0 1 0 0 0 0 Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3

Decoder
I0

Binary
1 1 1 1 0 0 0 0 0 0 0 Y2 Y2
I1 Y1 Y1
E Y0 Y0

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Implementation Using Decoders

 Each output is a minterm Binary

Decoder
 All minterms are produced
Y7
 Sum the required minterms Y6
Y5
x I2 Y4
y I1 Y3
Example: Full Adder
z I0 Y2
S(x, y, z) = ∑(1, 2, 4, 7) Y1
Y0
C(x, y, z) = ∑(3, 5, 6, 7)

S C 13 / 26
Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Multiplexers

S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Multiplexers

 2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
 4-to-1 MUX I1
Y
I0 I2

I1 I3
MUX Y
I2
I3
S1 S0
S1 S0 15 / 26
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Implementation Using Multiplexers

 Example
F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Implementation Using Multiplexers

 Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Implementation Using Multiplexers

 Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Multiplexer Expansion

 8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

1 0 0
S2 S1 S0 20 / 26
 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework

 Mano
4-2 Obtain the simplified Boolean expressions for output F
and G in terms of the input variables in the circuit:
A
F

B
C
G
D

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework

4-5 Design a combinational circuit with three inputs, x, y, and

z, and three outputs, A, B, and C. When the binary input
is 0, 1, 2, or 3, the binary output is one greater than the
input. When the binary input is 4, 5, 6, or 7, the binary
output is one less than the input.

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework
4-13 The adder-subtractor circuit has the following values for
mode input M and data inputs A and B. In each case,
determine the values of the four SUM outputs and the
carry C.
M A B
(a) 0 0111 0110
(b) 0 1000 1001
(c) 1 1100 1000
(d) 1 0101 1010
(e) 1 0000 0001

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework
4-27 A combinational circuit is specified by the following three
Boolean functions:
F1(A, B, C) = ∑(2, 4, 7)
F2(A, B, C) = ∑(0, 3)
F3(A, B, C) = ∑(0, 2, 3, 4, 7)
Implement the circuit with a decoder. Use a block
diagram for the decoder. Minimize the number of inputs
in the external gates.

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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework
4-28 A combinational circuit is defined by the following three
Boolean functions:
F1 = x’ y’ z’ + x z
F2 = x y’ z’ + x’ y
F3 = x’ y’ z + x y
Design the circuit with a decoder and external gates.

4-31 Construct a 16  1 multiplexer with two 8  1 and one

2  1 multiplexers. Use block diagrams.

4-32 Implement the following Boolean function with a

multiplexer:
F(A, B, C, D) = ∑(0, 1, 3, 4, 8, 9, 15)
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 Princess Sumaya University 4241 – Digital Logic Design Computer Engineering Dept.

Homework
4-33 Implement a full adder with two 4  1 multiplexers?

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