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ADITYA ENGINEERING COLLEGE (A)

Digital Circuits and Logic Design


Synchronous Counters
By

B.V.V.L.KALA BHARATHI
Dept of ELECTRICAL AND ELECTRONICS ENGINEERING
Aditya Engineering College(A)
Surampalem.
Aditya Engineering College (A)

What is a Synchronous Counter?


Synchronous counter is counter in which all the FFs are triggered simultaneously
by the clock input signals.
Other name is Parallel counter.
Therefore propagation delay decreases when compared to Asynchronous
Counters.
Types of S synchronous Counters:
 synchronous up counters
 synchronous down Counters
 Ring counters
 Johnson counters(Twisted ring counter)

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

Logic diagram of a 4 bit Synchronous Up counter

 Q1 changes state(toggles) for every clock pulse.

 Q2 changes its state whenever Q1 is 1.

 Q3 changes its state whenever Q1 =1 and Q2=1.

 Q4 changes its state whenever Q1=1,Q2=1 and Q3=1.

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

TRUTH TABLE AND TIMING DIAGRAM OF 4 BIT SYNCHRONOUS UP


COUNTER

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

Logic diagram of a 4 bit Synchronous Down counter

 Q1 changes state(toggles) for every clock pulse.

 Q2 changes its state whenever Q1’ is 1.

 Q3 changes its state whenever Q1’ =1 and Q2’=1.

 Q4 changes its state whenever Q1’=1,Q2’=1 and Q3’=1.

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

TRUTH TABLE OF 4 BIT SYNCHRONOUS DOWN COUNTER

Digital circuits and logic


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design
Aditya Engineering College (A)

LOGIC DIAGRAM OF 4 BIT RING COUNTER

Initially Q1 is preset to 1. that means initially


Q1=1, Q2=0, Q3=0 ,Q4=0.

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

TIMING DIAGRAM AND TRUTH TABLE OF A 4 BIT RING COUNTER

Digital circuits and logic


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design
Aditya Engineering College (A)

• LOGIC DIAGRAM OFA 4 BIT RING COUNTER USING J-K FLIP


FLOPS

Digital circuits and logic


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design
Aditya Engineering College (A)

LOGIC DIAGRAM OFA 4 BIT TWISTED RING COUNTER (JOHNSON COUNTER)

 Initially all the FFs are reset i.e., Q1=0,Q2=0,Q3=0,Q4=0.


 The sequence repeats for every 8 clock pulses

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

TRUTH TABLE AND TIMING DIAGRAM OF 4 BIT JOHNSON COUNTER

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

Revision on J –K flip flop

Digital circuits and logic


5/10/20
design
Aditya Engineering College (A)

THANK YOU

Digital circuits and logic


5/10/20
design

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