Microelectronics (EC 305)

B Tech ECE 5th semester

L 6 to L10
 Unit I
• Introduction to IC technology Topics
• • MOS, PMOS, NMOS, CMOS and BiCMOS
Technologies:
• • Oxidation
• • Lithography
• • Diffusion
• • Ion implantation
• • Metallization
• • Encapsulation • Probe testing • Integrated
Resistors and Capacitors
 Diffusion
The process of junction formation, that is transition
from p to n type or vice versa, is typically
accomplished by the process of diffusing the
appropriate dopant impurities in a high
temperature furnace.
Impurity atoms are introduced onto the surface of a
silicon wafer and diffuse into the lattice because of
their tendency to move from regions of high to low
concentration. Diffusion of impurity atoms into
silicon crystal takes place only at elevated
temperature, typically 900 to 1100°C.
Although these are rather high temperatures, they are
still well below the melting point of silicon, which is
at 1420°C.
The rate at which the various impurities diffuse into
silicon will be of the order of 1 micro meter per
hour at a temperature range stated above, and the
penetration depth that are involved in most
diffusion processes will be of the order of 0.3 to 30
micro meter.
At room temperature the diffusion process will be so
extremely slow such that the impurities can be
considered to be essentially frozen in place.
 Nature of Impurity Diffusion
The diffusion of impurities into a solid is basically the
same type of process as occurs when excess
carriers are created non-uniformly in a
semiconductor which cause carrier gradient.
In each case, the diffusion is a result of random
motion, and particles diffuse in the direction of
decreasing concentration gradient The random
motion of impurity atoms in a solid is, of course,
rather limited unless the temperature is high. Thus
diffusion of doping impurities into silicon is
accomplished at high temperature.
 Substitutional Diffusion
At high temperature many atoms in the semiconductor
move out of their lattice site, leaving vacancies into
which impurity atoms can move.
The impurities, thus, diffuse by this type of vacancy motion
and occupy lattice position in the crystal after it is cooled.
Thus, substitutional diffusion takes place by replacing the
silicon atoms of parent crystal by impurity atom.
In other words, impurity atoms diffuse by moving from a
lattice site to a neighbouring one by substituting for a
silicon atom which has vacated a usually occupied site as
shown in the figure below.
Substitutional Diffusion By Dopant Impurities
• Substitutional diffusion mechanism is applicable to the most
common diffusants, such as boron, phosphorus, and arsenic.
These dopants atoms are too big to fit into the interstices or
voids, so the only way they can enter the silicon crystal is to
substitute for a Si atom.
• In order for such an impurity atom to move to a neighbouring
vacant site, it has to overcome energy barrier which is due to
the breaking of covalent bonds. The probability of its having
enough thermal energy to do this is proportional to an
exponential function of temperature. Also, whether it is able
to move is also dependent on the availability of a vacant
neighbouring site and since an adjacent site is vacated by a Si
atom due to thermal fluctuation of the lattice, the probability
of such an event is again an exponent of temperature.
 Interstitial Diffusion
• In such, diffusion type, the impurity atom does not replace the
silicon atom, but instead moves into the interstitial voids in the
lattice. The main types of impurities diffusing by such
mechanism are Gold, copper, and nickel. Gold, particularly, is
introduced into silicon to reduce carrier life time and hence
useful to increase speed at digital IC’s.
• Because of the large size of such metal atoms, they do not
usually substitute in the silicon lattice. To understand interstitial
diffusion, let us consider a unit cell of the diamond lattice of the
silicon which has five interstitial voids. Each of the voids is big
enough to contain an impurity atom. An impurity atom located
in one such void can move to a neighbouring void, as shown in
the figure below.
Interstitial Diffusion of Impurity Atom
• If the diffused impurity type is different from the resistivity
type of the substrate material, a junction is formed at the
points where the diffused impurity concentration is equal to
the background concentration already present in the
substrate.
• In the fabrication of monolithic IC’s, constant source
diffusion is commonly used for the isolation and the emitter
diffusion because it maintains a high surface concentration
by a continuous introduction of dopant.
• There is an upper limit to the concentration of any impurity
that can be accommodated at the semiconductor wafer at
some temperature. This maximum concentration which
determines the surface concentration in constant source
diffusion is called the solid solubility of the impurity.
Limited Source Diffusion or Gaussian Diffusion
• Here a predetermined amount of impurity is introduced into the crystal
unlike constant source diffusion. The diffusion takes place in two steps.
• 1. Predeposition Step – In this step a fixed number of impurity atoms are
deposited on the silicon wafer during a short time.
• 2. Drive-in step – Here the impurity source is turned off and the amounts
of impurities already deposited during the first step are allowed to diffuse
into silicon water.
• The essential difference between the two types of diffusion techniques is
that the surface concentration is held constant for error function diffusion.
It decays with time for the Gaussian type owing to a fixed available doping
concentration Q. For the case of modelling the depletion layer of a p-n
junction, the erfc is modelled as a step junction and the Gaussian as a
linear graded junction. In the case of the erfc, the surface concentration is
constant, typically the maximum solute concentration at that temperature
or solid solubility limit.
 Parameters which affect diffusion profile
• Solid Solubility – In deciding which of the availability
impurities can be used, it is essential to know if the
number of atoms per unit volume required by the specific
profile is less than the diffusant solid solubility.
• Diffusion temperature – Higher temperatures give
more thermal energy and thus higher velocities, to the
diffused impurities. It is found that the diffusion
coefficient critically depends upon temperature.
Therefore, the temperature profile of diffusion furnace
must have higher tolerance of temperature variation over
its entire area.
• Diffusion time – Increases of diffusion time, t, or diffusion
coefficient D  have similar effects on junction depth as can be
seen from the equations of limited and constant source
diffusions. For Gaussian distribution, the net concentration will
decrease due to impurity compensation, and can approach
zero with increasing diffusion time. For constant source
diffusion, the net Impurity concentration on the diffused side of
the p-n junction shows a steady increase with time.
• Surface cleanliness and defects in silicon crystal - The
silicon surface must be prevented against contaminants
during diffusion which may interfere seriously with the
uniformity of the diffusion profile. The crystal defects such as
dislocation or stacking faults may produce localized impurity
concentration. This results in the degradation of junction
characteristics. Hence silicon crystal must be highly perfect
 Dopants and their Characteristics
• The dopants selection affects IC characteristics.
• Boron and phosphorus are the basic dopants
of most ICs.
• Arsenic and antimony, which are highly soluble
in silicon and diffuse slowly, are used before
epitaxial processing or as a second diffusion.
• Gold and silver diffuse rapidly. They act as
recombination centres and thus reduce carrier
life time.
Boron is almost an exclusive choice as an acceptor
impurity in silicon since other p-type impurities have
limitations as follows :
Gallium has relatively large diffusion coefficient in Si02,
and the usual oxide window-opening technique for
locating diffusion would be inoperative,
Indium is of little interest because of its high acceptor
level of 0.16 eV, compared with 0.01 eV for boron,
which indicates that not all such acceptors would be
ionized at room temperature to produce a hole.
Aluminium reacts strongly with any oxygen that is
present in the silicon lattice.
The choice of a particular n-type dopant is not
so limited as for p-type materials. The n-type
impurities, such as phosphorus, antimony and
arsenic, can be used at different stages of IC
processing. The diffusion constant of
phosphorus is much greater than for Sb and
As, being comparable to that for boron, which
leads to economies resulting from shorter
diffusion times.
 Diffusion Systems
• Impurities are diffused from their compound
sources as mentioned above. The method
impurity delivery to wafer is determined by
the nature of impurity source; Two-step
diffusion is widely technique. Using this
technique, the impurity concentration and
profiles can be carefully controlled. The type
of impurity distribution (erfc or Gaussian) is
determined by the choice of operating
conditions.
The two-step diffusion consists of a deposition step and a drive-
in step.
In the former step a constant source diffusion is carried out for a
short time, usually at a relatively low temperatures, say,
1000°C. In the latter step, the impurity supply is shutoff and
the existing dopant is allowed to diffuse into the body of the
semiconductor, which is now held at a different temperature,
say 1200°C, in an oxidizing atmosphere.
The oxide layer which forms on etire surface of the wafer during
this step prevents further impurities from entering, or those
already deposited, from diffusing out. The final impurity
profile is a function of diffusion condition, such as
temperature, time, and diffusion coefficients, for each step.
 Diffusion Furnace
For the various types of diffusion (and also
oxidation) processes a resistance-heated tube
furnace is usually used. A tube furnace has a
long (about 2 to 3 meters) hollow opening into
which a quartz tube about 100,150 mm in
diameter is placed as shown in the figure
below.
Diffusion system
The temperature of the furnace is kept about
1000°C. The temperature within the quartz
furnace tube can be controlled very accurately
such that a temperature within 1/2°C of the
set-point temperature can be maintained
uniformly over a “hot zone” about 1 m in
length. This is achieved by three individually
controlled adjacent resistance elements. The
silicon wafers to be processed are stacked up
vertically into slots in a quartz carrier or
“boat” and inserted into the furnace tube.
Diffusion of Dopants
 ION IMPLANTATION
• Ion Implantation is an alternative to a
deposition diffusion and is used to produce a
shallow surface region of dopant atoms
deposited into a silicon wafer.
• In this process a beam of impurity ions is
accelerated to kinetic energies in the range of
several tens of kV and is directed to the
surface of the silicon.
As the impurity atoms enter the crystal, they
give up their energy to the lattice in collisions
and finally come to rest at some average
penetration depth, called the projected range
expressed in micro meters.
Depending on the impurity and its implantation
energy, the range in a given semiconductor
may vary from a few hundred angstroms to
about 1micro meter.
Typical distribution of impurity along the
projected range is approximately Gaussian. By
performing several implantations at different
energies, it is possible to synthesize a desired
impurity distribution, for example a uniformly
doped region.
 Ion implantation
• Ion implantation is an alternative to diffusion for producing n-
or p-type material by introducing dopants into a
semiconductor through its surface
• With ion implantation, dopant atoms are injected into the
wafer not by the application of thermal energy, but by ionizing
the atoms, accelerating the ions to a high velocity, and
implanting them into the wafer by virtue of their high kinetic
energy.
• Ion implantation has several advantages over diffusion,.
 Ion Implantation
High Energy Accelerator

Force on charged particle 

F q vx B 
2mV
Magnetic Field B
qr 2

T
1
Implanted Dose Q
mqA
 It dt
0

1. Ion Source m  mass

2. Mass Spectrometer v = velocity
3. High-Voltage Accelerator (Up to 5 MeV) V  acceleration potential
4. Scanning System A = wafer area
5. Target Chamber

A gas containing the desired impurity is ionized within
the ion source. The ions are generated and repelled
from their source in a diverging beam that is
focussed before if passes through a mass separator
that directs only the ions of the desired species
through a narrow aperture.
A second lens focuses this resolved beam which then
passes through an accelerator that brings the ions to
their required energy before they strike the target
and become implanted in the exposed areas of the
silicon wafers. The accelerating voltages may be from
20 kV to as much as 250 kV.
In some ion implanters, the mass separation occurs
after the ions are accelerated to high energy.
Because the ion beam is small, means are provided
for scanning it uniformly across the wafers. For this
purpose the focussed ion beam is scanned
electrostatically over the surface of the wafer in the
target chamber.
Repetitive scanning in a raster pattern provides
exceptionally uniform doping of the wafer surface.
The target chamber commonly includes automatic
wafer handling facilities to speed up the process of
implanting many wafers per hour.
 Ion Implantation
• Wafer is Target in High Energy Accelerator
• Impurities “Shot” into Wafer
• Preferred Method of Adding Impurities to Wafers
– Wide Range of Impurity Species (Almost Anything)
– Tight Dose Control (A few % vs. 20-30% for high temperature pre-
deposition processes)
– Low Temperature Process
• Expensive Systems
• Vacuum System
Ion Implantation
Mathematical Model
Gaussian Profile

 x  R 2 
N x   N p exp
 p  
 2R p2 
 

R p  Projected Range

R p  Straggle


Dose Q=  N xdx  2 N p R p
0


 Annealing after Implantation
After the ions have been implanted they are lodged principally in
interstitial positions in the silicon crystal structure, and the
surface region into which the implantation has taken place
will be heavily damaged by the impact of the high-energy
ions.
The disarray of silicon atoms in the surface region is often to the
extent that this region is no longer crystalline in structure, but
rather amorphous.
To restore this surface region back to a well-
ordered crystalline state and to allow the
implanted ions to go into substitutional sites
in the crystal structure, the wafer must be
subjected to an annealing process.
The annealing process usually involves the
heating of the wafers to some elevated
temperature often in the range of 1000°C for a
suitable length of time such as 30 minutes.
Laser beam and electron-beam annealing are also
employed. In such annealing techniques only the
surface region of the wafer is heated and re-
crystallized. An ion implantation process is often
followed by a conventional-type drive-in diffusion, in
which case the annealing process will occur as part of
the drive-in diffusion.
Ion implantation is a substantially more expensive
process than conventional deposition diffusion, both
in terms of the cost of the equipment and the
throughput, it does, however, offer following
advantages:
Advantages of Ion Implantation:
Ion implantation provides much more precise control over the
density of dopants deposited into the wafer, and hence the
sheet resistance. This is possible because both the
accelerating voltage and the ion beam current are electrically
controlled outside of the apparatus in which the implants
occur.
Also since the beam current can be measured accurately during
implantation, a precise quantity of impurity can be
introduced. Small control over doping level, along with the
uniformity of the implant over the wafer surface, make ion
implantation attractive for the IC fabrication, since this causes
significant improvement in the quality of an IC.
Due to precise control over doping concentration, it is
possible to have very low values of dosage so that
very large values of sheet resistance can be obtained.
These high sheet resistance values are useful for
obtaining large-value resistors for ICs. Very low-
dosage, low-energy implantations are also used for
the adjustment of the threshold voltage of MOSFET’s
and other applications.
An obvious advantage of implantation is that it can be
done at relatively low temperatures, this means that
doped layers can be implanted without disturbing
previously diffused regions. This means a lesser
tendency for lateral spreading.
 Introduction
• Dope semiconductor
• Two way to dope
– Diffusion
– Ion implantation
• Other application of ion implantation

39
 Dope Semiconductor: Diffusion
• Isotropic process
• Can’t independently control dopant profile
and dopant concentration
• Replaced by ion implantation after its
introduction in mid-1970s.

40
 Dope Semiconductor: Diffusion
• First used to dope semiconductor
• Performed in high temperature furnace
• Using silicon dioxide mask
• Still used for dopant drive-in
• R&D on ultra shallow junction formation.

41
Dopant Oxide Deposition

Deposited Dopant Oxide

SiO2

Si Substrate

42
 Oxidation

SiO2

Si Substrate

43
 Drive-in

SiO2

Doped junction
Si Substrate

44
 Strip and Clean

SiO2

Doped junction
Si Substrate

45
Dope Semiconductor: Ion Implantation
• Used for atomic and nuclear research
• Early idea introduced in 1950’s
• Introduced to semiconductor
manufacturing in mid-1970s.

46
Dope Semiconductor: Ion Implantation
• Independently control dopant profile (ion
energy) and dopant concentration (ion
current times implantation time)
• Anisotropic dopant profile
• Easy to achieve high concentration dope of
heavy dopant atom such as phosphorus
and arsenic.

47
 Misalignment of the Gate

Gate Oxide
Metal Gate Metal Gate

p+ S/D n-Si p+ S/D

n-Si

Aligned Misaligned

48
 Comparison of
Implantation and Diffusion

Doped region

SiO2 PR

Si Si

Junction depth

Diffusion Ion implantation

49
 Comparison of
Implantation and Diffusion
Diffusion Ion Implantation

High temperature, hard mask Low temperature, photoresist mask

Isotropic dopant profile Anisotropic dopant profile

Cannot independently control of the dopant Can independently control of the dopant
concentration and junction depth concentration and junction depth

Batch process Both Batch and single wafer process

50
 Stopping Mechanism
• Ions penetrate into substrate
• Collide with lattice atoms
• Gradually lose their energy and stop
• Two stop mechanisms

51
 Two Stopping Mechanism
• Nuclear stopping
– Collision with nuclei of the lattice atoms
– Scattered significantly
– Causes crystal structure damage.
• Electronic stopping
– Collision with electrons of the lattice atoms
– Incident ion path is almost unchanged
– Energy transfer is very small
– Crystal structure damage is negligible

52
 Stopping Mechanism
• The total stopping power
Stotal = Sn + Se
• Sn: nuclear stopping, Se: electronic stopping
• Low E, high A ion implantation: mainly
nuclear stopping
• High E, low A ion implantation, electronic
stopping mechanism is more important

53
 Stopping Mechanisms

Ion
Random Collisions (S=Sn+Se)

Channeling
(SSe)

Back Scattering (SSn)

54
Ion Trajectory and Projected Range

Vacuum Substrate
Collision

Ion Trajectory

Ion Beam

Projected Range

Distance to the Surface

55
Implantation Processes: Channeling
• If the incident angle is right, ion can travel long
distance without collision with lattice atoms
• It causes uncontrollable dopant profile

Lots of collisions

Very few collisions

56
 Channeling Effect
Lattice Atoms

Channeling Ion

Collisional Ion

Wafer
Surface

57
 Post-collision Channeling
Collisional Channeling Collisional

Wafer
Surface

58
 Post-collision Channeling
Collisional Channeling Collisional
Dopant Concentration

Distance from surface

59
 Damage Process

• Implanted ions transfer energy to lattice atoms

– Atoms to break free
• Freed atoms collide with other lattice atoms
– Free more lattice atoms
– Damage continues until all freed atoms stop
• One energetic ion can cause thousands of
displacements of lattice atoms

60
 Lattice Damage With One Ion

Light Ion

Damaged Region

Heavy Ion

Single Crystal Silicon

61
 Implantation Processes: Damage
• Ion collides with lattice atoms and knock them
out of lattice grid
• Implant area on substrate becomes amorphous
structure

Before Implantation After Implantation

62
 Implantation Processes: Anneal
• Dopant atom must in single crystal structure
and bond with four silicon atoms to be
activated as donor (N-type) or acceptor (P-
type)

• Thermal energy from high temperature helps

amorphous atoms to recover single crystal
structure.

63
 Thermal Annealing

Lattice Atoms Dopant Atom

64
 Thermal Annealing

Lattice Atoms Dopant Atom

65
 Thermal Annealing

Lattice Atoms Dopant Atom

66
 Thermal Annealing

Lattice Atoms Dopant Atom

67
 Thermal Annealing

Lattice Atoms Dopant Atom

68
 Thermal Annealing

Lattice Atoms Dopant Atom

69
 Thermal Annealing

Lattice Atoms Dopant Atom

70
 Thermal Annealing

Lattice Atoms Dopant Atoms

71
Implantation Processes: Annealing

Before Annealing After Annealing

72
 Rapid Thermal Annealing (RTA)

• At high temperature, annealing out pace

diffusion
• Rapid thermal process (RTP) is widely used
for post-implantation anneal
• RTA is fast (less than a minute), better
uniformity, better thermal budget control,
and minimized the dopant diffusion

73
 RTP and Furnace Annealing

Gate
Poly Si Poly Si
Gate
SiO2

Si Si
Source/Drain

RTP Annealing Furnace Annealing

74
 Metallization
Metallization is the final step in the wafer
processing sequence. Metallization is the
process by which the components of IC’s are
interconnected by aluminium conductor. This
process produces a thin-film metal layer that
will serve as the required conductor pattern
for the interconnection of the various
components on the chip.
Another use of metallization is to produce
metalized areas called bonding pads around the
periphery of the chip to produce metalized
areas for the bonding of wire leads from the
package to the chip.
The bonding wires are typically 25 micro meters
diameter gold wires, and the bonding pads are
usually made to be around 100×100 micro
meters square to accommodate fully the
flattened ends of the bonding wires and to allow
for some registration errors in the placement of
the wires on the pads.
Metallization: Contact to devices, interconnections
between devices and to external

Signal (V or I) intensity and speed (frequency response, delay)

 Aluminium
Aluminium
• Aluminium (Al) is the most commonly used material for the metallization
of most IC’s, discrete diodes, and transistors. The film thickness is as
about 1 micro meters and conductor widths of about 2 to 25 micro
meters are commonly used. The use of aluminium offers the following
advantages:
• It has as relatively good conductivity.
• It is easy to deposit thin films of Al by vacuum evaporation.
• It has good adherence to the silicon dioxide surface.
• Aluminium forms good mechanical bonds with silicon by sintering at
about 500°C or by alloying at the eutectic temperature of 577°C.
• Aluminium forms low-resistance, non-rectifying (that is, ohmic) contacts
with p-type silicon and with heavily doped n-type silicon.
• It can be applied and patterned with a single deposition and etching
process.
 Aluminium limitations:
Aluminium has certain limitations:
• During packaging operation if temperature
goes too high, say 600°C, or if there is
overheating due to current surge, Al can fuse
and can penetrate through the oxide to the
silicon and may cause short circuit in the
connection. By providing, adequate process
control and testing, such failures can be
minimized.
 Electromigration
Aluminium suffers from electromigration which can cause
considerable material transport in metals.
It occurs because of the enhanced and directional mobility of
atoms caused by the direct influence of the electric field and the
collision of electrons with atoms, which leads to momentum
transfer.
In thin-film conductors that carry sufficient current density during
device operations, the mode of material transport can occur at
much lower temperature (compared to bulk metals) because of
the presence of grain boundaries, dislocations and point defects
that aid the material transport. Eecctromigration-induced failure
is the most important mode of failure in Al lines.
 Desired properties: Metallization
The desired properties of the metallization for IC can be listed as follows.
• Low resistivity.
• Easy to form.
• Easy to etch for pattern generation.
• Should be stable in oxidizing ambient , oxidizable.
• Mechanical stability; good adherence, low stress.
• Surface smoothness.
• Stability throughout processing including high temperature sinter, dry or wet oxidation,
gettering, phosphorous glass (or any other material) passivation, metallization.
• No reaction with final metal, aluminium.
• Should not contaminate device, wafers, or working apparatus.
• Good device characteristics and life times.
• For window contacts-low contact resistance, minimum junction penetration, low
electromigration.
 Metallization Application in VLSI
• Gates for MOSFET
• Contacts, and
• Interconnects.
Interconnection metallization interconnects thousands of
MOSFETs or bipolar devices using fine-line metal patterns. It is
also same as gate metallization for MOSFET.
All metallization directly in contact with semiconductor is called
contact metallization. Polysilicon film is employed in the form
of metallization used for gate and interconnection of MOS
devices.
Aluminium is used as the contact metal, on devices and as the
second-level inter-connection to the outside world.
Several new schemes for metallization have been suggested to
produce ohmic contacts to a semiconductor.
In several cases a multiple-layer structure involving a diffusion
barrier has been recommended.
 Metallization Processes

Metallisation process can be classified info two

types:
• CVD and
• Physical Vapour Deposition
CVD offers three important advantages.
Excellent step coverage
Large throughput
Low-temperature processing
The basic physical vapour deposition methods
are
Evaporation
Sputtering
Both these methods have three identical steps.
• Converting the condensed phase (generally a solid)
into a gaseous or vapour phase.
• Transporting the gaseous phase from the source to
the substrate, and
• Condensing the gaseous source on the substrate.
In both methods the substrate is away from the source.
• In cases where a compound, such as silicide, nitride,
or carbide, is deposited one of the components is as
gas and the deposition process is termed reactive
evaporation or sputtering.
 Deposition Apparatus
• The metallization is usually done in vacuum
chambers. A mechanical pump can reduce the
pressure to about 10 to 0.1 Pa. Such pressure
may be sufficient for LPCVD. An oil-diffusion
pump can bring the pressure down to 10-5 Pa and
with the help of a liquid nitrogen trap as low as
10-7 Pa. A turbomolecular pump, can bring the
pressure down to 10-8-10-9 Pa. Such pumps are
oil-free and are useful molecular-beam epitaxy
where oil contamination must be avoided.
• Besides the pumping system, pressure gauges
and controls, residual gas analyzers,
temperature sensors, ability to clean the
surface of the wafers by backsputtering,
contamination control, and gas manifolds, and
the use of automation should be evaluated.
• As typical high-vacuum evaporation apparatus
is shown in the figure below.
The apparatus consists of a hell jar, a stainless-
steel cylindrical vessel closed at the top and
sealed at the base by a gasket. Beginning at
atmospheric pressure the jar is evacuated by a
roughing pump, such as a mechanical rotary-
van pump reducing pressure to about 20 Pa or
a combination mechanical pump and liquid-
nitrogen-cooled molecular pump (reducing
pressure lo about 0.5 Pa).
• At the appropriate pressure, the jar is opened
to a high-vacuum pumping system that
continues to reduce the pressure.
• The high-vacuum, pumping system may
consist of a liquid nitrogen-cooled trap and an
oil-diffusion pump, a trap and a
turbomolecular pump, or a trap and a closed-
cycle helium refrigerator cryopump.
The cryopump acts as a trap and must be
regenerated periodically, the turbomolecular
and diffusion pumps act  as transfer  pumps,
expelling their gas t a forepump. The high
vacuum pumping system brings the jar to a
low pressure that is tolerable for the
deposition process.
 Metallization Patterning
• Once the thin-film metallization has been
done the film must be patterned to produce
the required interconnection and bonding pad
configuration. This is done by a
photolithographic process of the same type
that is used for producing patterns in
Si02 layers.
Aluminium can be etched by a number of acid
and base solutions including HCl, H3PO4, KOH,
and NaOH. The most commonly used
aluminium etchant is phosphoric acid with the
addition of small amounts of HN03 (nitric acid)
and acetic acid, to result a moderate etch rate
of about 1 micro meter per minute at 50°C.
Plasma etching can also be used with
aluminium.
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