DIODES BJT AND FET

DIODE

• A diode is a semiconductor device that essentially acts as a one-way

switch for current. It allows current to flow easily in one direction, but
severely restricts current from flowing in the opposite direction.
• Diodes are also known as rectifiers because they change alternating
current (ac) into pulsating direct current (dc). Diodes are rated according
to their type, voltage, and current capacity.
• Diodes have polarity, determined by an anode (positive lead)
and cathode (negative lead). Most diodes allow current to flow only when
positive voltage is applied to the anode. A variety of diode configurations
are displayed in this graphic:
Diodes are available in various configurations. From left: metal
case, stud mount, plastic case with band, plastic case with
chamfer, glass case.
When a diode allows current flow, it is forward-biased. When
a diode is reverse-biased, it acts as an insulator and does not
permit current to flow.
BIPOLAR JUNCTION TRANSISTORS (BJT)

NPN PNP
COMMON-EMITTER NPN TRANSISTOR

Reverse bias the CBJ

Forward bias the BEJ

• Plot IB as f(VBE, VCE)

• As VCE increases, more VBE required to

turn the BE on so that IB>0.

• Looks like a pn junction volt-ampere

characteristic.
• Plot IC as f(VCE, IB)
• Cutoff region (off)
• both BE and BC reverse biased
• Active region
• BE Forward biased
• BC Reverse biased
• Saturation region (on)
• both BE and BC forward biased
TRANSFER
CHARACTERISTIC
S
LARGE-SIGNAL
MODEL OF A BJT
•KCL >> IE = IC + IB

•βF = hFE = IC/IB

•IC = βFIB + ICEO

•IE = IB(1 + βF) + ICEO

•IE = IB(1 + βF)

•IE = IC(1 + 1/βF)

•IE = IC(βF + 1)/βF

 FORMULA

I E  I B  IC
IC
 F  hFE 
IB
IC   F I B  I CEO
IE  I B (1   F )  I CEO  I B (  F  1)
 1  F 1
IE  I C 1    I
  F 
C
F
IC  F IE
F F
F   F 
F 1 1F
TRANSISTOR OPERATING POINT

VB  VBE
IB 
RB
VCE VCC
IC   
RC RC
VCE  VCC  IC RC
DC LOAD LINE
BJT
TRANSISTO
R SWITCH
VB  VBE
IB 
RB
VCE  VCC  I C RC
VCE  VCB  VBE
VCB  VCE  VBE
BJT IN SATURATION

VCC  VCE ( sat )

I CS 
RC
I CS
I BS 
F
IB
ODF 
I BS
I CS
 forced 
IB
MODEL WITH
CURRENT GAIN
MILLER
EFFECT
MILLER EFFECT (CONTINUED)

d d
iout  Ccb (vbe  vce )  Ccb (vbe  Avbe )
dt dt
d d
iout  Ccb [1  A]vbe   Ccb [1  A]  vbe 
dt dt
Ccb  Ccb [1  A]
MILLER EFFECT (CONTINUED)

• Miller Capacitance, CMiller = Ccb(1 – A)

• since A is usually negative (phase inversion), the Miller capacitance
can be much greater than the capacitance Ccb

• This capacitance must charge up to the base-emitter forward bias voltage,

causing a delay time before any collector current flows.
 THE SATURATING CHARGE

• The saturating charge, Qs

storage time constant of the transistor

20
TRANSISTOR
SWITCHING
TIMES
POWER LOSS DUE TO IC FOR TON = TD + TR

• During the delay time, 0 ≤t ≤td

• Instantaneous Power Loss

Pc (t )  vCE iC  VCC I CEO
Pc (t )  (250V )(3mA)  0.75W
• Average Power Loss
td td
1 VCC I CEO
Pd   Pc (t )dt   dt  VCC I CEO f st d
T 0 T 0

Pd  (250V )(3mA)(10kHz )(0.5 s)  3.75mW

 DURING THE RISE TIME, 0 ≤T ≤TR

Pc (t )  vCE ic
 t  I CS
Pc (t )  VCC  (Vce ( sat )  VCC )  t
 tr  tr
dPc (t ) Vce ( sat )  VCC I CS  t  I CS
 t  VCC  (Vce ( sat )  VCC ) 
dt tr tr  tr  tr
Pc (t )  Pmax @ t  t m
trVCC
tm 
2[VCC  Vce ( sat ) ]
 (1 s )(250V )
tm   0.504  s
2[250V  2V ]
2
V I CS
Pmax  CC
4[VCC  VCE ( sat ) ]
(250V ) 2 (100 A)
Pmax   6300W
4[250V  2V ]
 AVERAGE POWER DURING RISE TIME

tr
1  VCC VCE ( sat )  VCC 
Pr 
T 0 Pc (t ) dt  f s I CS t r 
 2

3


 (250V ) (2V  250V ) 
Pr  (10kHz )(100 A)(1 s )   
 2 3 
Pr  42.33W
 TOTAL POWER LOSS DURING TURN-ON

Pon  Pd  Pr
Pon  0.00375  42.33  42.33375W
Pon  42.33W
POWER
LOSS
 POWER LOSS DURING
THE CONDUCTION PERIOD
0  t  tn
ic (t )  I CS  100 A
vCE (t )  VCE ( sat )  2V
Pc (t )  ic vCE  (100 A)(2V )  200W
tn tn
1
Pn 
T  P (t )dt
0
c  VCE ( sat ) I CS f s  dt  VCE ( sat ) I CS f s t n
0

Pn  (2V )(100 A)(10kHz )(48.5  s )  97W

POWER LOSS
 POWER LOSS DURING TURN OFF
STORAGE TIME
0  t  ts
ic (t )  I CS  100 A
vCE (t )  VCE ( sat )  2V
Pc (t )  vCE ic  VCE ( sat ) I CS  (2V )(100 A)
Pc (t )  200W
ts ts
1
Ps 
T  P (t )dt
0
c  VCE ( sat ) I CS f s  dt
0
 VCE ( sat ) I CS f s ts

Ps  (2V )(100 A)(10kHz )(5  s )  10W

INSTANTANEOUS
POWER FOR
EXAMPLE 4.2
BJT SWITCH
WITH AN
INDUCTIVE
LOAD
LOAD
LINES
INTRODUCTION
TO FET
CURRENT
CONTROLLED VS
VOLTAGE
CONTROLLED
DEVICES
TYPES OF FET’S

• JFET – Junction Field Effect Transistor

• MOSFET – Metal Oxide Semiconductor Field Effect Transistor
• D-MOSFET - Depletion Mode MOSFET
• E- MOSFET - Enhancement Mode MOSFET
TRANSFER CHARACTERISTICS

• The input-output transfer characteristic of the JFET is not as straight forward as it is for the
BJT

• In a BJT,  (hFE) defined the relationship between IB (input current) and IC (output current).

•
In a JFET, the relationship (Shockley’s Equation) between VGS (input voltage) and ID (output
current) is used to define the transfer characteristics, and a little more complicated (and not
linear):
 AS A RESULT, FET’S ARE OFTEN REFERRED TO A SQUARE LAW
DEVICES

2
 VGS 
ID = IDSS  1 - 
 VP 
JFET
CONSTRUCTION
There are two types of JFET’s:
n-channel and p-channel.
The n-channel is more widely
used.
JFET OPERATING CHARACTERISTICS

• There are three basic operating conditions for a JFET:

• JFET’s operate in the depletion mode only

A.VGS = 0, VDS is a minimum value depending on IDSS and the drain and source resistance
B.VGS < 0, VDS at some positive value and
C.Device is operating as a Voltage-Controlled Resistor

• For an n channel JFET, VGS may never be positive*

• For an p channel JFET, VGS may never be negative*
SAMPLES
N-CHANNEL
JFET
OPERATION
JFET SYMBOL
SATURATION

•At the pinch-off point:

• • any further increase in
VGS does not produce any
increase in ID. VGS at
pinch-off is denoted as
Vp.
• • ID is at saturation or
maximum. It is referred to as IDSS.
• • The ohmic value of the channel
is at maximum.
ID  IDSS
• As VGS becomes more negative:
• • the JFET will pinch-off at a lower voltage (Vp).

• • ID decreases (ID < IDSS) even though VDS is increased.

• • Eventually ID will reach 0A. VGS at this point is called Vp or VGS(off).

• • Also note that at high levels of VDS the JFET reaches a breakdown
situation.
ID will increases uncontrollably if VDS > VDSmax.
 FET AS A VOLTAGE-
CONTROLLED RESISTOR

•The region to the left of the pinch-

off point is called the ohmic region.
•The JFET can be used as a variable
resistor, where VGS controls the
drain-source resistance (rd). As VGS
becomes more negative, the
resistance (rd) increases.
(TRANSCONDUCTANCE)
CURVE
PLOTTING THE
TRANSCONDUCTANCE
CURVE
CASE
CONSTRUCTION
AND TERMINAL
IDENTIFICATION
P-CHANNEL
JFET’S
P-CHANNEL
JFET
CHARACTE
RISTICS