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Processor Organization
Datapath Design
Review
• ISA and Instruction Format of MIPS
– Instruction set
– Instruction format
– Addressing modes
Overview
• Computer organization (microarchitecture)
• Processor organization
– Datapath
– Control
– Register file
• Processor implementation overview
• Clocking methodologies
• Sequential circuits
– Latches
– Registers
Review: The Processor
• Processor (CPU)
– Active part of the computer
– Does all the work
• Data manipulation
• Decision-making
• Datapath
– Hardware that perform all required operations
– ALU + registers + internal buses
– The brawn
• Control
– Hardware which tells the datapath what needs to be done
– The brain
Review: Processor Organization
Address bus Data bus
Control bus signals
Control signals
Control
Unit Data values
Registers
Control signals
Instruction rd Data
memory
rs Address
PC
+4 Data
imm
Opcode,
funct
Controller
Read ports
Write port
Register File Read Ports
Register File Write Ports
Core Topic –Datapath Design
• Datapath implements fetch-decode-
execute
• Design Methodology
Determine instruction classes and formats
Build datapath sections for each instr.fmt.
Compose sections to yield MIPS datapath
+
PC 4
Read Addr
Instruction
fetch
Instruction
Memory
R-format Datapath
• Format: opcode r1, r2, r3
ALU op
Register File 3
Write ALU
Register Read
Write Data Data 2
Result
Register
Write
Animating the Datapath
add rd, rs, rt
Instruction
op rs rt rd shamt funct R[rd] <- R[rs] + R[rt];
5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD
RD2
RegWrite
Load/Store Datapath Issues
• lw $t1, offset($t2)
– Memory at base $t2 with offset
– lw: Read memory, write into register $t1
– sw: Read from register $t, write to memory
• Address computation – ISA says:
– Sign-extend 16-bit offset to 32-bit signed value
MemWrite
16 32
Sign
Address Extend
Read data
Data
Write data Memory
1101 … 0011
1111 1111 1111 1111 1101 … 0011
MemRead
Load/Store Datapath Actions
WD
MemWrite
RD2 ADDR
RegWrite
Memory
E WD RD
16 X 32
T
N MemRead
D
Animating the Datapath
op rs rt offset/immediate sw rt, offset(rs)
MEM[R[rs]
16
+ sign_extend(offset)] <- R[r
5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD
MemWrite
RD2 ADDR
RegWrite
Memory
E WD RD
16 X 32
T
N MemRead
D
Branch Datapath Issues
• beq $t1, $t2, offset
– Two registers ($t1, $t2) compared for equality
– 16-bit offset to compute branch target address
• Branch target address – ISA says:
– Add sign-extended offset to PC
– Base address is instruction after branch (PC+4)
– Shift offset left 2 bits => word offset
• Jump to target
– Replace lower 26 bits of PC with lower 26 bits
of instruction shifted left 2 bits
Branch Datapath Actions
WD
RD2
RegWrite
16
E
X 32
beq rs, rt, offset
T
N
D
if (R[rs] == R[rt]) then
PC <- PC+4 + s_extend(offset<
Delayed Branch (MIPS)
• MIPS ISA: Branches always delayed
- Instr. Ib following branch is always executed
- condition = false => Normal branch
- condition = true => Ib executed
Why bother?
1. Improves efficiency of pipelining
2. Branch not taken (false condition) can be
common case
Conclusions
• MIPS ISA: Three instruction formats (R,I,J)
• Datapath designed for each instruction format
• Datapath Components:
-- R-format: ALU, Register File
-- I-format: Sign Extender, Data Memory
-- J-format: ALU #2 for target address comp’n.
Trick: Delayed branch to make pipeline efficient
End!!