TYPES OF SIGNALS

• ANALOG OR CONTINUOUS
TIME SIGNAL
• DISCRETE TIME SIGNAL
• DIGITAL SIGNAL

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 1

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 LOGIC GATES
• A logic gate is a basic building block of a
digital circuit.
• It is an electronic circuit that has one or
more than one inputs and one output.
• The relationship between the i/p and
the o/p is based on a certain logic.
• Logic gates perform basic logical
functions.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 2
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 TYPES OF LOGIC GATES
BASIC GATES:
• AND
• OR
• NOT
UNIVERSAL GATES:
• NAND
• NOR PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 3
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SPECIAL PURPOSE GATES:
• Ex-OR
• Ex-NOR

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 4

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DEMORGAN’S THEOREM
• The complement of the sum is equal
to product of individual
complements.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 5

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• The complement of the
product is equal to sum of
individual complements.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 6

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 DESIGN ALL
GATES USING
NAND GATE
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 7
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 DESIGN ALL
GATES USING
NOR GATE
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 8
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BOOLEAN ALGEBRA
• It is a mathematical logic which is used to
analyze and simplify the logic circuit.
• It uses the binary numbers 0 & 1. It is
also called as Binary Algebra or logical
Algebra.
• It has its own set of rules or laws to
simplify the complex expressions and to
reduce the number of logic gates.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 9
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 LAWS OF BOOLEAN ALGEBRA

1. AND LAWS:
• A.0 = 0
• A.1 = A
• A.A = A
• A.A = 0
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 10
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2. OR LAWS:
• A+0 = A
• A+1 = 1
• A+A = A
• A+A = 1
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 11
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3. COMMUTATIVE LAW:
• A.B = B.A
• A+B = B+A

4. ASSOCIATIVE LAW:
• (A.B).C = A.(B.C)
• (A+B)+C = A+(B+C)
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 12
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5. DISTRIBUTIVE LAW:
• A.(B+C) = AB + AC
• A+BC = (A+B).(A+C)

6. ABSORPTION LAW:
A+AB = A
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 13
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7. INVERSION LAW:

•A = A

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 14

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NUMERICALS
ON BOOLEAN
ALGEBRA
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 15
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 HALF ADDER
• It is a combinational circuit with
two inputs and two outputs sum
and carry.
• It is the basic building block for
addition of two single bit
numbers.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 16
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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 17
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 FULL ADDER
• It is a combinational circuit
used for the addition of 3
single bit numbers.
• It has 3 inputs and 2 outputs
sum and carry.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 18

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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 19
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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 20
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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 21
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FULL ADDER USING HALF ADDER

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 22

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 SR LATCH
SR Latch is a circuit with:
• 2 cross-coupled NOR gate or 2 cross-
coupled NAND gate.
• 2 inputs S for SET and R for RESET.
• 2 outputs Q, Q’.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 23

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SR LATCH USING NOR GATE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 24

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TRUTH TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 25

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 FLIP FLOP
• It is a sequential circuit in which output
depends not only on present inputs but
also on past inputs and outputs.
• It has two states logic 1 and logic 0.
• It is also called digital memory circuit.
• These circuit can flip from one state to
another and flop back thats’why called
flip flop.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 26
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 TYPES OF FLIP FLOPS
• SR FLIP FLOP
• JK FLIP FLOP
• T FLIP FLOP
• D FLIP FLOP

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 27

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SYMBOL OF SR FLIP FLOP

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 28

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SR FLIP FLOP USING NOR GATE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 29

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FUNCTION TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 30

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 EQUATION OF SR FLIP FLOP

• Qn+1 = S + R’Q

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 31

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JK FLIP FLOP
SYMBOL

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 32

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 JK FLIP FLOP CIRCUIT
DIAGRAM USING NOR GATE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 33

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FUNCTION TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 34

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EQUATION OF JK FLIP FLOP

• Qn+1 = JQ’ + K’Q

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 35

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T FLIP FLOP SYMBOL

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 36

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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 37
T UNIVERSITY, PUNE [BASICS OF ELECTRICA
CIRCUIT DIAGRAM OF T FLIP FLOP
USING NOR GATE

J
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 38
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FUNCTION TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 39

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EQUATION OF T FLIP FLOP

• Qn+1 = TQ’ + T’Q

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 40

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D FLIP FLOP SYMBOL

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 41

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PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 42
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CIRCUIT DIAGRAM OF D FLIP FLOP
USING NOR GATE

J
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 43
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FUNCTION TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 44

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EQUATION OF D FLIP FLOP

• Qn+1 = D

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 45

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 SHIFT REGISTERS
• Flip flops are to store a single bit of binary
data (1or 0). In order to store multiple bits
of data, multiple flip flops are required.
• Shift Register is a device consisting of a
group of flip flops connected in series to
store multiple bits of data.
• Used in calculators, computers etc. for
storage & movement of data.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 46
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 TYPES OF SHIFT REGISTERS
1. Serial in Serial out Shift Register
(SISO)
2. Serial In Parallel out shift Register
(SIPO)
3. Parallel in Parallel out Shift Register
(PIPO)
4. Parallel in Serial out Shift Register
(PISO)
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 47
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 Serial-in Serial-out (SISO)
• Data is entered serially and output is
also taken serially.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 48

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 CIRCUIT DIAGRAM
LET THE DATA TO BE TRANSMITTED IS 1101

D3
. D2 D1 D0 .
FF3 Q3 FF2 Q2 FF1 Q1 FF0 Q0

CLK

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 49

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TRUTH TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 50

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 Serial-in Parallel-out (SIPO)
• Data is entered serially and but
output is taken in parallel manner.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 51

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 CIRCUIT DIAGRAM
LET THE DATA TO BE TRANSMITTED IS 1101

D3
. D2 D1 D0 .
FF3 FF2 FF1 FF0

CLK

Q3 Q2 Q1 Q0
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 52
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TRUTH TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 53

T UNIVERSITY, PUNE [BASICS OF ELECTRICA
 Parallel-in Serial-out (PISO)
• Data is entered parallelly and but
output is taken in serially.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 54

T UNIVERSITY, PUNE [BASICS OF ELECTRICA
 CIRCUIT DIAGRAM
D3 D2 D1 D0

. .
FF3 Q3 FF2 Q2 FF1 Q1 FF0 Q0

CLK
LET THE DATA TO BE TRANSMITTED IS 1101

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 55

T UNIVERSITY, PUNE [BASICS OF ELECTRICA
TRUTH TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 56

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 Parallel-in Parallel-out (PIPO)
• Data is entered parallelly and but
output is also taken in parallel
manner.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 57

T UNIVERSITY, PUNE [BASICS OF ELECTRICA
 CIRCUIT DIAGRAM
D3 D2 D1 D0

. .
FF3 FF2 FF1 FF0

CLK
Q3 Q2 Q1 Q0

LET THE DATA TO BE TRANSMITTED IS 1101

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 58
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TRUTH TABLE

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 59

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 COUNTERS
• It is a sequential circuit consisting of a set of
flip flops connected together with a clock
signal applied.
• It is a digital circuit capable of counting the
clock pulses arriving at its clock input.
• On arrival of each clock pulse counter is
incremented by one for up counter .
• In case of down counter it is decremented by
one.
PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 60
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 TYPES OF COUNTERS
Asynchronous or Serial or Ripple Counter:
• External clock signal is applied to one flip flop
and the output of prceeding flip flop is
connected to the clock input of next flip flop.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 61

T UNIVERSITY, PUNE [BASICS OF ELECTRICA
Synchronous or Parallel Counters :
• Clock pulses are applied
simultaneously to all the flip flops
are called Synchronous Counters.

PROF. AMIT KUMAR PATIL, MITSOE, MIT AD 62

T UNIVERSITY, PUNE [BASICS OF ELECTRICA