Low-Voltage Pulsewidth ControlLoops for SOC Applications
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 10, OCTOBER 2002
Po-Hui Yang
,
Jinn-Shyan WangSpeaker: Wen-Lung ChangDate: 10. 28.2009
Outline
Abstract & Introduction
Circuit architecture
Experimental results
Conclusion
Abstract & Introduction
In this paper, adopts the conventional PWCL,but with a new duty-cycle detector and a pulsegenerator.
Using this architecture, the output of PWCLhas fixed rising edge.
This architecture can combine PLL/DLL withPWCL to perform phase locking and adjustpulsewidth.
of 00
Low-Voltage Pulsewidth Control Loops for SOC Applications
476 Reads
Info and Rating
| Category: | |
| Rating: | |
| Upload Date: | 11/25/2009 |
| Copyright: | Attribution Non-commercial |
| Tags: |
Free download as PDF File (.pdf), Powerpoint Presentation (.ppt), text file (.txt) or view presentation slides online.
Leave a Comment